CN103996702A - 一种提高超结功率器件雪崩耐量的终端结构 - Google Patents
一种提高超结功率器件雪崩耐量的终端结构 Download PDFInfo
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Abstract
本发明涉及半导体技术,具体的说是涉及一种提高超结功率器件雪崩耐量的终端结构。本发明在器件终端区中提出终端击穿区,将雪崩击穿点限定在终端击穿区中,从而既避免了元胞击穿的寄生BJT导通问题,又避免了常规终端击穿时的雪崩电流路径过长,造成局部温升的问题,因此能够提高超结功率器件的雪崩耐量和可靠性。本发明的有益效果为,有效的缩短了器件雪崩击穿点在终端时的雪崩电流路径,在不影响器件击穿电压的前提下,提高了器件的抗UIS失效能力,提高了器件的可靠性。本发明尤其适用于超结功率器件。
Description
技术领域
本发明涉及半导体技术,具体的说是涉及一种提高超结功率器件雪崩耐量的终端结构。
背景技术
功率MOSFET(金属氧化物半导体场效应晶体管)以其具有开关速度高、开关损耗低、驱动损耗低等优点,在各种功率变换特别是在高频功率变换中起着重要作用。非箝位感性负载下的开关过程(Unclamped Inductive Switching,UIS)通常被认为是功率器件在***应用中所能遭遇的最极端电应力情况。因为在回路导通时存储在电感中的能量必须在关断瞬间全部由功率器件释放,同时施加于功率器件的高电压和大电流极易造成器件失效。雪崩耐量是衡量器件抗UIS能力的重要参数。
功率MOSFET的UIS失效模式主要有两种:一种是功率MOSFET的寄生BJT导通损坏,另一种是热损坏。寄生BJT导通损坏是指当反向大电流流过器件基区时,会使得基区温度升高,而基区电阻为正温度特性,从而降落在基区的压降增大,如果该压降增大至接近寄生BJT的基区和发射极之间的自建电势,导致寄生BJT开启。开启的BJT会进一步的放大流过基区的大电流,进而使结温升高,形成一个正反馈,最后导致器件过热而失效。热损坏是指功率MOSFET工作在大功率情况下,导致结温升高,当器件某薄弱部分的结温升高到器件材料所允许的最大值时过热而失效。针对前一种功率MOSFET失效模式,抑制寄生BJT的开启便可提高功率MOSFET可靠性,通常适当增大MOSFET源区下体区掺杂浓度,减低寄生BJT基区电阻,抑制其开启。而对于后一种功率MOSFET失效模式,可适当优化设计,减少器件的弱单元(薄弱区)或者缩短雪崩击穿电流的路径,减少器件的发热量,减少UIS失效的概率。
具有超结结构的功率MOSFET器件是当代重要的功率器件之一,其基本原理是电荷平衡原理,通过在传统MOSFET的轻掺杂漂移区引入重掺杂交错排列的P、N柱,大大的改善了传统MOSFET击穿电压和导通电阻之间的矛盾关系,因而其在功率***中获得了广泛的应用。功率器件的设计除了元胞设计很重要外终端的设计也很重要,好的终端设计能有效的提高器件耐压、可靠性和降低器件漏电。在传统的终端技术中,通常采用场限环、场板和结终端延伸等技术削弱器件主结的曲率效应,最后达到提高器件耐压能力的目的。由于超结结构特点,传统功率器件的终端结构不再适用超结功率器件。目前应用最广泛的超结功率器件终端结构是采用和元胞相同的P、N柱,同样利于P、N柱之间的相互耗尽提高击穿电压。
雪崩耐量同样是超结MOSFET器件可靠性的重要指标。目前采用的器件终端结构,当器件的雪崩击穿点在终端时,由于终端电位浮空,没有通过电极引出,雪崩击穿电流必须从击穿点开始流经很长的距离才能到达源电极(如图1所示),造成终端局部温度过高,不利于提高器件的雪崩耐量。当击穿点在器件元胞处时,雪崩电流通过元胞的源极接触泄放,电流泄放通路较宽;但是,雪崩电流流经元胞体区时有可能造成寄生三极管开启(如图2所示),同样影响器件的雪崩耐量。
发明内容
本发明所要解决的,就是针对传统超结功率器件存在的雪崩耐量较差的问题,提出一种提高超结功率器件雪崩耐量的终端结构。
本发明解决上述技术问题所采用的技术方案是:一种提高超结功率器件雪崩耐量的终端结构,该终端结构包括第一导电类型半导体衬底2、设置在第一导电类型半导体衬底2下层的金属漏极1、设置在第一导电类型半导体衬底2上层的第一导电类型半导体外延区3,所述第一导电类型半导体外延区3上层远离器件元胞的一端设置有场限环12;其特征在于,该终端结构包括终端击穿区和终端耐压区,其中终端击穿区位于器件元胞和终端耐压区之间;位于终端耐压区中的第一导电类型半导体外延区3中设置有多个第二导电类型半导体掺杂柱4,位于终端击穿区中的第一导电类型半导体外延区3中设置有多个第二导电类型半导体掺杂柱5,且位于终端击穿区中的第二导电类型半导体掺杂柱5的掺杂深度比位于终端耐压区中的第二导电类型半导体掺杂柱4的掺杂深度缩短10%~20%;位于终端击穿区的第二导电类型半导体掺杂柱5的上层设置有第二导电类型半导体区10,所述第二导电类型半导体区10与器件金属源极连接。
本发明总的技术方案,在器件终端区中提出终端击穿区,将雪崩击穿点限定在终端击穿区中,从而既避免了元胞击穿的寄生BJT导通问题,又避免了常规终端击穿时的雪崩电流路径过长,造成局部温升的问题,因此能够提高超结功率器件的雪崩耐量和可靠性。
具体的,所述位于终端击穿区中的第二导电类型半导体掺杂柱5为1个。
具体的,所述位于终端耐压区中的第二导电类型半导体掺杂柱4的上表面设置有多晶硅场板。
具体的,所述位于终端耐压区中的第二导电类型半导体掺杂柱4的上表面设置有金属场板。
本发明的有益效果为,有效的缩短了器件雪崩击穿点在终端时的雪崩电流路径,在不影响器件击穿电压的前提下,提高了器件的抗UIS失效能力,提高了器件的可靠性。
附图说明
图1是普通超结功率器件终端结构剖面结构、雪崩击穿电流路径和雪崩击穿点示意图;
图2是超结MOSFET器件元胞剖面结构、其寄生BJT和雪崩电流路径示意图;
图3是本发明提出的超结功率器件终端结构剖面结构、雪崩击穿电流路径和雪崩击穿点示意图;
图4是普通超结功率器件终端结构在器件终端发生雪崩击穿时的雪崩电流分布和击穿点示意图;
图5是本发明提出的提高超结功率器件雪崩耐量的终端结构在器件终端发生雪崩击穿时的雪崩电流分布和击穿点示意图;
图6是图4中普通超结MOSFET器件终端工作在阻断模式下的I-V特性曲线示意图;
图7是图5中本发明提出的超结MOSFET器件终端工作在阻断模式下的I-V特性曲线示意图;
图8是将终端击穿区的P型半导体掺杂柱深度相对于终端耐压的P型半导体掺杂柱4深度依次缩减(以5cm为间隔)后通过仿真工具Tsuprem4和Medic仿真得到的超结MOSFET器件耐压下降百分比图;
图9是终端击穿区Ⅱ的P型半导体掺杂柱相对于终端耐压III的P型半导体掺杂柱缩短了6cm时的雪崩电流分布图;
图10是本发明提出的一种超结终端结构。
具体实施方式
下面结合附图和实施例,详细描述本发明的技术方案:
如图1所示,为普通超结MOSFET终端结构示意图,当器件雪崩击穿发生在终端时,击穿点位置随机,雪崩电流将从击穿点流过终端表面到达器件源极,击穿点越远离元胞,则雪崩电流流经路径越长。图4为采用仿真工具Tsuprem4和Medic仿真得到的普通超结MOSFET终端雪崩电流分布图,从图可以看出雪崩电流会横向流经终端表面路径较长。雪崩电流路径越长,雪崩电流流过路经的电阻就越大,器件的发热量越大,大热量会使器件温度大幅度升高,数据显示:电子元器件温度每升高2%其可靠性会下降约10%,那么温度升高50℃时,器件的寿命只有其温度升高25℃时的1/6左右。显然,长的雪崩电流路径不利于对器件雪崩耐量和可靠性的提高。另一方面,大量雪崩电流从终端表面经过,会影响到终端表面硅和氧化层界面质量,也可能给终端氧化层引入大量电荷或缺陷,对器件可靠性是极为不利的。
如图3所示,为本发明的超结功率器件雪崩耐量的终端结构,包括第一导电类型半导体衬底2、设置在第一导电类型半导体衬底2下层的金属漏极1、设置在第一导电类型半导体衬底2上层的第一导电类型半导体外延区3;与终端相邻的器件元胞中包括位于第一导电类型半导体外延区3中的第二导电类型半导体掺杂柱41、位于第二导电类型半导体掺杂柱41上方的第二导电类型半导体体区6、位于体区6中的相互独立的第二导电类型半导体短路区7和第一导电类型半导体源区8,以及位于体区6之上的栅电极9和金属源极11;该终端结构包括终端击穿区和终端耐压区,其中终端击穿区位于器件元胞和终端耐压区之间;位于终端耐压区中的第一导电类型半导体外延区3中设置有多个第二导电类型半导体掺杂柱4,位于终端击穿区中的第一导电类型半导体外延区3中设置有多个第二导电类型半导体掺杂柱5,且位于终端击穿区中的第二导电类型半导体掺杂柱5的掺杂深度比位于终端耐压区中的第二导电类型半导体掺杂柱4的掺杂深度缩短10%~20%;位于终端击穿区的第二导电类型半导体掺杂柱5的上层设置有第二导电类型半导体区10,所述第二导电类型半导体区10与金属源极11连接。
本发明的工作原理为:
当所述第一导电类型半导体为N型半导体、第二导电类型半导体为P型半导体时,所述超结MOSFET器件为N沟道超结MOSFET器件;反之,所述超结MOSFET器件为P沟道超结MOSFET器件。现以N沟道超结MOSFET终端为例,说明本发明的工作原理。
当N沟道超结MOSFET器件工作在阻断状态(栅极和源极接地,漏极接高压)时,元胞区由电荷补偿区的超结结构承受高压。而对于终端击穿区和终端耐压区,既要考虑垂直方向的耐压又要考虑水平方向的耐压,其垂直方向的耐压原理与元胞相似,而水平方向的耐压原理与传统平面MOSFET终端结构的场限环相同。
当器件雪崩击穿发生在终端时,击穿点始终被限定在终端结构的终端击穿区。图5为采用仿真工具Tsuprem4和Medic仿真得到的本发明超结MOSFET器件终端的雪崩电流分布图。从图中可以看出雪崩电流路径相对较短,且不会经过终端表面。本发明提出的提高超结功率器件雪崩耐量的终端结构能够缩短当器件击穿点在终端的时的雪崩电流路径的原理是:超结MOSFET器件终端结构的终端击穿区和终端耐压区的P型半导体掺杂柱深度设计不一样。终端击穿区的P型半导体掺杂柱5的深度相对终端耐压区的P型半导体掺杂柱4的深度较浅,则终端击穿区的耐压能力相对终端耐压区的耐压能力较弱。当超结功率器件雪崩击穿发生在终端部分时,击穿点被限制在终端击穿区。由于击穿点限定,防止了雪崩击穿随机发生在终端耐压区,缩短了雪崩击穿时的雪崩电流路径,减少了器件的发热量,从而减少超结功率器件UIS失效的概率,提高了超结功率器件的可靠性。
由于超结MOSFET器件终端的耐压能力大小与电荷补偿区的掺杂浓度无关,而与P型半导体掺杂柱5或4的深度密切相关;P型半导体掺杂柱5或4的深度越深超结MOSFET器件终端的耐压能力越大。本发明提出的提高超结功率器件雪崩耐量的终端结构将终端终击穿区的P型半导体掺杂柱5的深度减小,会在一定程度上影响超结MOSFET器件的耐压;但是,由于元胞的耗尽区扩展到了终端耐压区,器件耐压主要由终端耐压区承担,因此击穿电压的降低并不会很明显。
为了验证本发明的有益效果,以N沟道超结MOSFET器件终端为例,利用仿真工具Tsuprem4和Medic进行模拟。图4为普通超结MOSFET终端在雪崩击穿时的雪崩电流分布和耗尽区分布图。在该模拟结构中,器件元胞区包含一个元胞,终端击穿区包含一个P型柱5,终端耐压区包含11个P型柱4。元胞区、终端击穿区和终端耐压区的N型柱浓度即N型外延层的浓度为1*1015cm-3;其P型柱的浓度均为2.4*1015cm-3,宽度为5um,柱间距为12um,柱深度均为60um。图6是图4中超结MOSFET终端工作在阻断模式下的I-V特性曲线,从图可以读出器件耐压约为1169V。图5为本发明的超结MOSFET器件终端的在雪崩击穿时的雪崩电流分布和耗尽区分布图。该模拟结构中,除了终端击穿区的P型柱5的深度为50um以外,其他结构和参数均与上模拟的普通超结MOSFET器件终端结构一样。图7是图5中超结MOSFET终端工作在阻断模式下的I-V特性曲线,从图可以读出器件耐压约为1148V。将图4和图5进行对比可以发现本发明提出的提高超结功率器件雪崩耐量的终端结构的击穿点在终端击穿区,故其雪崩电流路径更短,则器件的可靠性更高。同时将图6与图7对比发现本发明提出的提高超结功率器件雪崩耐量的终端结构的耐压能力有所下降,但仅下降约2%。
图8为将终端击穿区的P型半导体掺杂柱5深度相对于终端耐压的P型半导体掺杂柱4深度依次缩减(以5cm为间隔)后通过仿真工具Tsuprem4和Medic仿真得到的超结MOSFET器件耐压下降百分比图,且仿真结构中终端耐压区的P柱4深度为60cm。从图中发现超结MOSFET器件的耐压降低的百分比与终端击穿区的P型半导体掺杂柱5的深度减小的百分比近似呈正比关系。当P型半导体掺杂柱5的深度缩短20%时,其耐压仅减少约3%。可见,超结MOSFET器件终端击穿区的P型半导体掺杂柱5的深度减小对器件耐压能力影响不大。
另一方面,如果终端击穿区的P型半导体掺杂柱5相对于终端耐压的P型半导体掺杂柱4的深度减小量不够,击穿点将不能被限制在终端击穿区。如图9所示,该结构中终端击穿区的P型半导体掺杂柱5相对于终端耐压的P型半导体掺杂柱4缩短了6cm(占P型半导体掺杂柱4总长度的10%),则雪崩电流也会在终端耐压区出现。因此,最佳的条件是:终端击穿区的P型半导体掺杂柱5相对于终端耐压的P型半导体掺杂柱4的深度减小10%~20%之间,这样既能限定雪崩击穿点,又不影响器件的耐压。
本发明中位于元胞中的第二导电类型半导体掺杂柱41、位于终端耐压区中的第二导电类型半导体掺杂柱4和位于终端击穿区中的第二导电类型半导体掺杂柱5可利用挖槽-外延填充或多次离子注入-外延的方法得到。如果利用挖槽-外延填充法,需通过两次挖槽工艺,获得深度不同的槽区,再进行外延填充;如果采用多次离子注入-外延的方法,则要通过不同的离子注入掩膜版,实现深度不同的位于元胞中的第二导电类型半导体掺杂柱41、位于终端耐压区中的第二导电类型半导体掺杂柱4和位于终端击穿区中的第二导电类型半导体掺杂柱5。
其中,终端击穿区的第二导电类型半导体体区10与元胞区的第二导电类型半导体体区6可用同一步扩散工艺得到。
其他工艺步骤,与常规超结功率MOSFET的工艺步骤相同。
在具体的实施过程中,保持本发明基本结构不变的情况下,可以根据具体情况做一些变通设计。比如终端击穿区的第一导电类型半导体掺杂柱或第二导电类型半导体掺杂柱的宽度与器件元胞的第一导电类型半导体掺杂柱或第二导电类型半导体掺杂柱的宽度相等或者不相等。除此之外,如图10所示,耐压区第二导电类型半导体掺杂柱上方可添加金属或者多晶场板结构。
Claims (4)
1.一种提高超结功率器件雪崩耐量的终端结构,该终端结构包括第一导电类型半导体衬底(2)、设置在第一导电类型半导体衬底(2)下层的金属漏极(1)、设置在第一导电类型半导体衬底(2)上层的第一导电类型半导体外延区(3),所述第一导电类型半导体外延区(3)上层远离器件元胞的一端设置有场限环(12);其特征在于,该终端结构包括终端击穿区和终端耐压区,其中终端击穿区位于器件元胞和终端耐压区之间;位于终端耐压区中的第一导电类型半导体外延区(3)中设置有多个第二导电类型半导体掺杂柱(4),位于终端击穿区中的第一导电类型半导体外延区(3)中设置有多个第二导电类型半导体掺杂柱(5),且位于终端击穿区中的第二导电类型半导体掺杂柱(5)的掺杂深度比位于终端耐压区中的第二导电类型半导体掺杂柱(4)的掺杂深度缩短10%~20%;位于终端击穿区的第二导电类型半导体掺杂柱(5)的上层设置有第二导电类型半导体区(10),所述第二导电类型半导体区(10)与器件金属源极连接。
2.根据权利要求1所述的一种提高超结功率器件雪崩耐量的终端结构,其特征在于,所述位于终端击穿区中的第二导电类型半导体掺杂柱(5)为1个。
3.根据权利要求1所述的一种提高超结功率器件雪崩耐量的终端结构,其特征在于,所述位于终端耐压区中的第二导电类型半导体掺杂柱(4)的上表面设置有多晶硅场板。
4.根据权利要求1所述的一种提高超结功率器件雪崩耐量的终端结构,其特征在于,所述位于终端耐压区中的第二导电类型半导体掺杂柱(4)的上表面设置有金属场板。
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