CN103996416B

CN103996416B - A kind of reusable FTL verification method

Info

Publication number: CN103996416B
Application number: CN201410226573.6A
Authority: CN
Inventors: 杨萌; 李风志; 姚香君; 戴绍新
Original assignee: Shandong Sinochip Semiconductors Co Ltd
Current assignee: Shandong Sinochip Semiconductors Co Ltd
Priority date: 2014-05-27
Filing date: 2014-05-27
Publication date: 2017-03-08
Anticipated expiration: 2034-05-27
Also published as: CN103996416A

Abstract

The invention discloses a kind of reusable FTL verification method, including building bus-structured verification platform, in order to build the flash controller model with USB model；The excitation injecting described verification platform comprises two parts, the firmware of the corresponding flash controller of a part, and another part is FTL sequence；Wherein, the compiler calling CPU is compiled to firmware, produces target program, and injects internal memory；FTL sequence is then injected by USB model, and by carrying out to FTL sequence verifying in order to simulate USB device at random, and the random of FTL sequence is obtained using the random fashion based on SV；SV is System Verilog.The debugging efficiency of FTL checking can be improved according to the present invention.

Description

A kind of reusable FTL verification method

Technical field

The present invention relates to the method that one kind is verified for FTL (Flash Translation Layer, flash translation layer (FTL)).

Background technology

Flash memory（Flash Memory, full name is flash memory）Read/write unit be page, and the size of page is generally 4KB Or 8KB, but operating system read-write data is by HDD（Hard Disk Drive, hard disk drive）Sector size carry out （As 512Byte（Byte））, more troublesome is that flash memory is wiped with block office, and does not wipe and just cannot write, and this leads to grasp SSD cannot be managed as the file system that system currently uses at all（Solid State Disk, solid state hard disc）, need to change more Advanced, complicated file system goes to solve this problem, but thus can increase the burden of operating system.

And in order to not increase the burden of operating system, SSD invents disk the operation of flash memory by the way of software Independent sector operates, here it is FTL.Because FTL is present in file system and physical medium（Flash memory）Between, operating system only need to be with Originally equally operate LBA（Logical Block Address, logical block addresses, abbreviation logical address）, and LBA arrives PBA（Physics Block Address, physical block address, abbreviation physical address）All conversion work, just entirely transfer to FTL is responsible for.

Understand, FTL is between NAND according to aforesaid content（NAND gate）Flash chip（It is the movement core of solid state hard disc Piece）With base file system（As FAT32）Between a conversion layer, it enables operating system and file system hard as accessing Disk equally accesses NAND flash memory equipment.

FTL Algorithm constitution firmware and configure on such as flash controller, be to FTL layer output FTL sequence process Algorithm.Good FTL algorithm, while ensureing read or write speed, by monitoring write and the erasing times of the page, allows each page The write in face and erasing times are kept in balance, and the life-span of nand flash memory chip can be significantly increased.Thus, FTL is except for LBA To outside the mapping of PBA, garbage reclamation also to be taken into account, many contents such as wear leveling.

In the conventional digital SoC based on FTL（System on Chip, SOC(system on a chip)）In development process, FTL firmware Debugging cycle will be far above hardware, and reason is exactly that firmware is debugged invisible it is impossible to be carried out by the waveform of similar hardware designs The precise positioning of mistake, adds FTL algorithm itself, as previously mentioned the work such as address of cache to be processed, garbage reclamation and wear leveling Make, complexity is higher, and debugging efficiency is very low.

Content of the invention

Therefore, it is an object of the invention to provide a kind of reusable FTL verification method, to improve the debugging of FTL checking Efficiency.

The present invention employs the following technical solutions：

A kind of reusable FTL verification method, including

Build bus-structured verification platform, in order to build the flash controller model with USB model；

The excitation injecting described verification platform comprises two parts, the firmware of the corresponding flash controller of a part, another part For FTL sequence；

Wherein, the compiler calling CPU is compiled to firmware, produces target program, and injects internal memory；

FTL sequence is then injected by USB model, by carrying out to FTL sequence testing in order to simulate USB device at random Card, and the random random fashion acquisition adopting based on SV of FTL sequence；SV is System Verilog.

Above-mentioned reusable FTL verification method, the acquisition of FTL sequence also includes finding in selecting or test Problem by firmware personnel input.

Above-mentioned reusable FTL verification method, described FTL sequence is deposited in the way of file, and during checking, USB model is read FTL sequential file is taken to obtain FTL sequence.

Above-mentioned reusable FTL verification method, described USB model is the USB model based on SV.

The interface of above-mentioned reusable FTL verification method, USB model and RTL is realized in program (program), from And it is divided into different time domains in a program；Wherein RTL is register-transfer level, i.e. Method at Register Transfer Level.

Above-mentioned reusable FTL verification method, emulates to RTL in front end, executes firmware with it.

According to the present invention, FTL sequence random, the random fashion based on SV obtains, and can change sequence ground by constraint The scope of location, data package size and reading and writing data direction, thus there is more preferable motility, convenient debugging, thus improve Debugging efficiency.

Brief description

Fig. 1 is a kind of Organization Chart of verification platform.

Specific embodiment

With reference to Fig. 1, the verification platform framework corresponding to this verification method, by CPU, RAM, USB, Flash, AHB_ The module composition bus apparatus such as Arbiter, DMA, hang over bus AHB（Advanced High performance Bus）, overall Constitute bus structures, corresponding to flash controller, constitute the model of flash controller.

The external drive of verification platform is divided into two parts, firmware（firmware）With FTL sequence.Wherein firmware is with file side Formula is deposited, and forms firmware file, in order to deposit firmware, before emulation starts, configuration script is from this firmware file Read firmware, call the compiler of CPU to be compiled firmware, the target program that compiling produces simultaneously injects RAM（Internal memory）It is central, Running environment is depicted.FTL sequential file is to USB model（USB model）The FTL sequence that it sends is provided.

USB model is used for simulating USB, sends the read-write of FTL sequence and analog data.

Before emulation starts, script calls compiler, and firmware is compiled, and changes into the file format that CPU can execute, The i.e. executable target program of CPU.

FTL sequence for emulation has two kinds：The first, by firmware, personnel provide, for running specific emulation, for sending out The FTL sequence of existing problem, the rapid position positioning bug；Second, is obtained by randomly generating mode, this mode be used for into The substantial amounts of random test of row.

Wherein for some empirical test objects, FTL sequence can be added to, for some the new problems finding, Directly can be provided by firmware personnel.

In addition, for some in FTL sequence the less object of weight, the probability directly being arrived at random when random is relatively Little it is also possible to directly be provided by firmware personnel.

The random of FTL sequence is obtained using the random fashion based on SV (System Verilog), can be changed by constraint Become sequence address scope, data package size, and reading and writing data direction, thus there is more preferable motility.

In addition, for constraint, can opening to tester, carry out artificial modification or correction, worked as with meeting Front test needs.

With regard to SV, it is a kind of concept combining from Verilog, VHDL, C++, also verification platform language and asserting Language is that is to say, that it is by hardware description language（HDL）With modern high-level language（C++）Combine.Make it for entering The checking engineer of the design verification of trade the present high complexity has sizable captivation.

These all make System Verilog improve the ability of design setting model on a higher abstraction hierarchy.It It is primarily located within the realization and checking flow process of chip.System Verilog has needed for chip design and checking engineer Entire infrastructure, it is integrated with the characteristics such as OOP, dynamic thread and inter-thread communication, as a kind of industrial standard language Speech, SV Comprehensive RTL design, test platform, asserts and coverage rate, is system-level design and checking provides powerful Hold effect.

SystemVerilog is for RTL（Method at Register Transfer Level）, abstract model and advanced verification platform exploitation for Full blast, because it possesses the architecture of execution this respect required by task, for example, is restricted arbitrary excitation generation, function Cover or assert.

With regard to RTL, in RTL, IC is to be made up of one group of logical operation between depositor and depositor.Why such as This, be because that most of circuit can be seen as storing binary data by depositor, by the logic between depositor Operate and to complete the process of data, the flow process of data processing to be controlled by sequential state machine, these process and control can be with firmly Part description language is describing.

RTL and the simple difference of gate leve are, RTL is to use hardware description language（Verilog or VHDL）Describe you to think The function of reaching, gate leve is then to use specific logical block（Rely on the storehouse of producer）To realize your function, gate leve may finally It is processed into the hardware of reality in semiconductor factory, in short, RTL and gate leve are to design the different phase on realizing, and RTL is through logic After synthesis, just obtain gate leve.

RTL description is to be expressed as a finite state machine, or one can be on a predetermined clock cycle side The more generally sequential state machine of register transfer is carried out on boundary, usual tri- kinds of language of VHDL/verilog/SV are described.

RTL circuit structure is simple, and element is few.

FTL sequence is passed through to read the acquisition of FTL sequential file；Data passes through random acquisition.

USB model is write using SV and forms, and class-based characteristic makes it have very high reusability, the interface with RTL In program（program）Middle realization, program passes through to divide different time domains（timing region）, can be prevented effectively from disorderly Disorderly（race）Problem.And this USB model has cast aside the state machine flow process within USB, compared with traditional model There is simple high speed.

Program is used for dividing the region of time domain for one that synopsys provides, and emulator can be with area in the region Divide different time domains, for processing the sequential of RTL and TB, it is to avoid race problem

Emulation is carried out using nc-sim, and emulation starts rear wave file and can pass through the instruments such as verdi under emulation catalogue Open, the emulation to FTL algorithm is debugged.

In sum, the method invented herein, can be carried out for specific FTL sequence or random FTL sequence FTL algorithm simulating, and debugging waveform is provided.Compare traditional FTL adjustment method, there is location of mistake accurately, debugging is efficient Feature.In firmware debugging process, using this method, the debugging efficiency of FTL algorithm can be greatly improved, reduce required for debugging Each side resource consumption.

Claims

1. a kind of reusable FTL verification method is it is characterised in that include

The excitation injecting described verification platform comprises two parts, the firmware of the corresponding flash controller of a part, and another part is FTL Sequence；

FTL sequence is then injected by USB model, by carrying out to FTL sequence verifying in order to simulate USB device at random, and The random of FTL sequence is obtained using the random fashion based on SV；SV is System Verilog；

Described USB model is the USB model based on SV；

The interface of USB model and RTL is realized in a program, thus being divided into different time domains in a program；Wherein RTL is Register-transfer level, i.e. Method at Register Transfer Level；

In front end, RTL is emulated, execute firmware with it.

2. reusable FTL verification method according to claim 1 is it is characterised in that the acquisition of FTL sequence also includes pin To selected or test in find problem by firmware personnel input.

3. reusable FTL verification method according to claim 1 and 2 is it is characterised in that described FTL sequence is with file Mode deposit, during checking, USB model read FTL sequential file obtain FTL sequence.