CN103986439A - Ultra-wide-band five-digit active phase shifter based on orthogonal vector modulation - Google Patents
Ultra-wide-band five-digit active phase shifter based on orthogonal vector modulation Download PDFInfo
- Publication number
- CN103986439A CN103986439A CN201410200749.0A CN201410200749A CN103986439A CN 103986439 A CN103986439 A CN 103986439A CN 201410200749 A CN201410200749 A CN 201410200749A CN 103986439 A CN103986439 A CN 103986439A
- Authority
- CN
- China
- Prior art keywords
- road
- pipe
- voltage control
- signal
- control amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
The invention discloses an ultra-wide-band five-digit active phase shifter based on orthogonal vector modulation. An input signal forms an I-branch differential signal and a Q-branch differential signal after passing through an orthogonal signal generator, wherein the I-branch differential signal and the Q-branch differential signal are orthogonal with each other, the I-branch signal arrives at one end of an adder after passing through an I-branch phase quadrant controller and an I-branch voltage-controlled gain amplifier, and the Q-branch signal arrives at the other end of the adder after passing through a Q-branch phase quadrant controller and a Q-branch voltage-controlled gain amplifier; the two signals are output through an output end after being added together by the adder; a logic encoder is mainly used for encoding a five-digit control signal output from the outside to control a DAC, the I-branch phase quadrant controller and the Q-branch phase quadrant controller; the DAC controls the I-branch voltage-controlled gain amplifier, the Q-branch voltage-controlled gain amplifier and the adder. The ultra-wide-band five-digit active phase shifter based on orthogonal vector modulation has the advantages that by the adoption of the passive phase shifting device, an extremely high integration level can be achieved, the occupied area is small, and the loss is small.
Description
Technical field
The invention belongs to active phase shifter technical field, relate to a kind of five active phase shifters of ultra broadband based on orthogonal vector modulation.
Background technology
Phase shifter all has a wide range of applications in numerous technical fields such as radar, communication, instrument and meter, heavy ion avcceleration, missile attitude controls.Phase shifter is a kind of two-port network, be direct current biasing as the circuit of control signal, mainly make to produce between input and output signal phase difference.No matter be digital phase shifter or analog phase shifter, its basic function is all by direct current biasing, as control signal, to change the transmission phase place of pending signal, so electronically controlled phase shifter is one of critical component of all phased array radars.By the control mode of the topmost feature-phase shifter of phase shifter, phase shifter can be divided into analog phase shifter and digital phase shifter.Analog phase shifter according to actual needs, changes phase shift is continuously changed continuously by control signal is corresponding, and the feature of this phase shifter should be adjustable continuously to be summarised as phase shift; The most basic difference of digital phase shifter and analog phase shifter is, its phase shift can only change according to predetermined centrifugal pump, i.e. its phase shift be quantized, phase place can only step change, phase shifter phase-stepping of the present invention is 11.25.The energy index of mainly thinking of phase shifter has: (1) working band; (2) amount of phase shift; (3) phase shifting accuracy; (4) discrepancy loss; (5) input vswr; (6) bear power.Traditional digital phase shifter is mainly divided into switching wiring phase shifter, load linear phase shifter, height pain type phase shifter and emission type phase shifter, these structures mainly realize phase shift by passive network, passive network not only has insertion loss, but also takies larger area, is unfavorable for integrated.Phase shifter of the present invention is realized by active phase-shift network, has certain gain, and area occupied is little, is beneficial to integrated.What microwave band digital phase shifter adopted now mostly is GaAs technique, and GaAs material price is expensive, and particularly, when passive component (as filter, duplexer, antenna) takies a large amount of area, its cost is higher.Relative other semi-conducting material, silicon has the advantages such as growing large-size, highly purified crystal and hot property are enriched, are easy to cheapness and mechanical performance is good.Yet in decades microwave integrated circuit always GaAs or the InP of use value costliness make backing material, and developed a set of brand-new processing technology and logic design method for this reason.If this is because silicon, as the substrate of microwave circuit, thinks that it has two obvious defects traditionally: the one, two kinds of important transistor silicon BJT that electronic technology development relies on and the operating rate of MOSFET are too low, do not reach the spectrum requirement of microwave circuit; The 2nd, the resistivity too little (1-100 Ω cm) of conventional silicon, will cause too high dielectric loss, makes the attenuation ratio GaAs substrate of silicon substrate microwave transmission line and passive component on average exceed an order of magnitude, can not drop into actual use.Recent years, along with frequency is up to the silicon diode of 100GHz and succeeding in developing of SiGeHBT, and find by add can the debase the standard loss of silicon transmission line of plural layers dielectric between silicon substrate and signal conductor, proved that silicon is suitable for replacing GaAs or InP completely as the substrate of microwave integrated circuit.What phase shifter of the present invention adopted is BiCMOS technique, has advantage cheaply.
Traditional digital phase shifter phase-shift network is mainly to adopt passive network, and the passive network that utilizes switching tube to change between input and output changes phase shift value.Due to not gain of passive network, there is certain insertion loss, the passive device in passive network occupies larger area in circuit in addition, is unfavorable for integrated.Phase-shift network of the present invention utilizes active device to realize, and has certain gain, and active device area occupied is than little many of passive device, has greatly reduced the area of phase shifter, is conducive to highly integrated.
Summary of the invention
The object of the present invention is to provide a kind of five active phase shifters of ultra broadband based on orthogonal vector modulation, solved the problem that existing phase shifter insertion loss is large, area occupied is large.
The technical solution adopted in the present invention is to comprise orthogonal signal generator, analog adder, DAC and logic encoder;
Wherein, input signal forms differential signal I road signal and the Q road signal of two-way quadrature after orthogonal signal generator;
Orthogonal signal generator is exported to analog adder by I road signal and Q road signal, and analog adder is comprised of I road phase quadrant controller, Q road phase quadrant controller, I road voltage control Amplifier, Q road voltage control Amplifier and adder; Wherein I road signal arrives one end of adder after I road phase quadrant controller, I road voltage control Amplifier, and Q road signal arrives one end, adder Ling road after Q road phase quadrant controller, Q road voltage control Amplifier; Adder is exported from output after two paths of signals is added;
Logic encoder mainly completes the coding to the five digit number control signal of outside input, and its output is used for controlling DAC, I road phase quadrant controller and Q road phase quadrant controller;
DAC is converting analog signal to from the digital signal of logic encoder input, and the analog signal after conversion is used for controlling I road voltage control Amplifier and Q road voltage control Amplifier and adder.
Further, what described orthogonal signal generator adopted is second order passive RLC resonant network, has a pair of differential input end V
in+, V
in-, two couples of difference output end V
oI+, V
oI-and V
oQ+, V
oQ-, two inductance L 1, L2, two capacitor C 1, C2, two resistance R 1, R2; Differential input end V wherein
in+be connected with one end of L1 and C1, V
in-be connected with one end of L2, C2, V
oI+be connected V with one end of R1 and the other end of C1
oI-be connected V with one end of R2 and the other end of C2
oQ+be connected with the other end of L1 and the other end of R2, V
oQ-be connected with the other end of L2 and the other end of R1.
Further, described DAC consists of 7 modules, 19 modules, 28 modules, 37 modules, 91 modules and four NMOS transistors M1, M2, M3, M4, wherein 7 modules have two input port S0, S0N and two output port I1 and Q1, input port S0, S0N connect the digital signal of logic encoder, S0N is the non-of S0, output port I1 is connected with I road input current node, and Q1 is connected with Q road input current node;
19 modules have two input port S1, S1N and two output port I2 and Q2, and S1, S1N are the digital signals fetching from logic encoder, and S1N is the non-of S1, and I2 is connected with I road input current node, and Q2 is connected with Q road input current node;
28 modules have two input port S2, S2N and two output port I3 and Q3, and S2, S2N are the digital signals fetching from logic encoder, and S2N is the non-of S2, and I3 is connected with I road input current node, and Q3 is connected with Q road input current node;
37 modules have two input port S3, S3N and two output port I4 and Q4, and S3, S3N are the digital signals fetching from logic encoder, and S3N is the non-of S3, and I3 is connected with I road input current node, and Q3 is connected with Q road input current node;
91 modules have two input port S4, S4N and two output port I4 and Q4, and S4, S4N are the digital signals fetching from logic encoder, and S4N is the non-of S4, and I4 is connected with I road input current node, and Q4 is connected with Q road input current node; The drain electrode of M1 pipe is connected with the grid level of the source class of M3, M1, and the source class of M1 pipe is connected to the ground, and the grid level of M1 pipe is connected with the grid level of the drain electrode of M1, M5; The drain electrode of M3 pipe is connected with the grid level of I1, I2, I3, I4, I5, M3 pipe, and the source class of M3 pipe is connected with the drain electrode of M1 pipe; The grid level of M3 pipe is connected with the drain electrode of M3 pipe, and Ibias is connected with the biasing of I road voltage control Amplifier; The drain electrode of M2 pipe is connected with the grid level of the source class of M4, M2, and the source class of M2 pipe is connected to the ground, and the grid level of M2 pipe is connected with the grid level of 41 drain electrode, M6; The drain electrode of M4 pipe is connected with the grid level of Q1, Q2, Q3, Q4, Q5, M4 pipe, and the source class of M4 pipe is connected with the drain electrode of M2 pipe; The grid level of M4 pipe is connected with the drain electrode of M4 pipe, and Qbias is connected with the biasing of Q road voltage control Amplifier.
Further, described analog adder is comprised of I road phase quadrant controller, I road voltage control Amplifier, Q road phase quadrant controller, Q road voltage control Amplifier and adder, and adder is comprised of two nmos pass transistor M5 and M6;
M5 and M6 are respectively the tail current of I road voltage control Amplifier, Q road voltage control Amplifier, be used for controlling the gain of I road voltage control Amplifier and Q road voltage control Amplifier, adder is added the output current of I road voltage control Amplifier and Q road voltage control Amplifier, and adder is output as the differential signal after phase shift.
The invention has the beneficial effects as follows and adopt passive phase shifting device, can realize very high integrated level, area occupied is little, and loss is little.
Accompanying drawing explanation
Fig. 1 is electrical block diagram of the present invention;
Fig. 2 is orthogonal signal generator structure chart of the present invention;
Fig. 3 is DAC structural representation of the present invention;
Fig. 4 is analog adder structural representation of the present invention.
In figure, 1. orthogonal signal generator, 2. analog adder, 3.DAC, 4. logic encoder, 201.I road phase quadrant controller, 202.I road voltage control Amplifier, 203.Q road phase quadrant controller, 204.Q road voltage control Amplifier, 205. adder, 301.7 modules, 302.19 modules, 303.28 modules, 304.37 module, 305.91 modules.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
The present invention comprises orthogonal signal generator 1 as shown in Figure 1, analog adder 2, DAC3 and logic encoder 4;
Wherein, input signal forms differential signal I road signal and the Q road signal of two-way quadrature after orthogonal signal generator 1;
Orthogonal signal generator 1 is exported to analog adder 2 by I road signal and Q road signal, and analog adder 2 is comprised of I road phase quadrant controller 201, Q road phase quadrant controller 203, I road voltage control Amplifier 202, Q road voltage control Amplifier 204 and adder 205; Wherein I road signal arrives one end of adder 205 after I road phase quadrant controller 201, I road voltage control Amplifier 202, and Q road signal arrives one end, adder 205Ling road after Q road phase quadrant controller 203, Q road voltage control Amplifier 204; Adder 205 is exported from output after two paths of signals is added;
Logic encoder 4 mainly completes the coding to the five digit number control signal of outside input, and its output is used for controlling DAC3, I road phase quadrant controller 201 and Q road phase quadrant controller 203;
DAC3 is converting analog signal to from the digital signal of logic encoder 4 inputs, and the analog signal after conversion is used for controlling I road voltage control Amplifier 202 and Q road voltage control Amplifier 204 and adder 205.
With reference to Fig. 2, orthogonal signal generator 1 has two inputs and four outputs, and two inputs are used for input differential signal, and four outputs are used for producing differential signal I road and the Q road of two-way quadrature.
What the orthogonal signal generator 1 in the present invention adopted is second order passive RLC resonant network, has a pair of differential input end V
in+, V
in-, two couples of difference output end V
oI+, V
oI-and V
oQ+, V
oQ-, two inductance L 1, L2, two capacitor C 1, C2, two resistance R 1, R2; Differential input end V wherein
in+be connected with one end of L1 and C1, V
in-be connected with one end of L2, C2, V
oI+be connected V with one end of R1 and the other end of C1
oI-be connected V with one end of R2 and the other end of C2
oQ+be connected with the other end of L1 and the other end of R2, V
oQ-be connected with the other end of L2 and the other end of R1;
L1=L2=L wherein, C1=C2=C, R1=R2=2R, the quality factor of the passive RLC resonant network of second order are less than at 1 o'clock, two couples of difference output V in very wide bandwidth
oI+, V
oI-and V
oQ+, V
oQ-amplitude equal and opposite in direction, quadrature in phase, quadrature error is very little.
With reference to Fig. 3, DAC3 in the present invention consists of 7 module 301,19 module 302,28 module 303,37 module 304,91 modules 305 and four NMOS transistors M1, M2, M3, M4, wherein 7 modules 301 have two input port S0, S0N and two output port I1 and Q1, input port S0, S0N connect the digital signal of logic encoder, S0N is the non-of S0, output port I1 is connected with I road input current node, and Q1 is connected with Q road input current node;
19 modules 302 have two input port S1, S1N and two output port I2 and Q2, and S1, S1N are the digital signals fetching from logic encoder 4, and S1N is the non-of S1, and I2 is connected with I road input current node, and Q2 is connected with Q road input current node;
28 modules 303 have two input port S2, S2N and two output port I3 and Q3, and S2, S2N are the digital signals fetching from logic encoder 4, and S2N is the non-of S2, and I3 is connected with I road input current node, and Q3 is connected with Q road input current node;
37 modules 304 have two input port S3, S3N and two output port I4 and Q4, and S3, S3N are the digital signals fetching from logic encoder 4, and S3N is the non-of S3, and I3 is connected with I road input current node, and Q3 is connected with Q road input current node;
91 modules 305 have two input port S4, S4N and two output port I4 and Q4, and S4, S4N are the digital signals fetching from logic encoder 4, and S4N is the non-of S4, and I4 is connected with I road input current node, and Q4 is connected with Q road input current node;
I outputs to I road voltage control Amplifier,, Q outputs to Q road voltage control Amplifier;
When S0 is high level, I1 is selected, and 7 flow out from I1, and the electric current that Q1 flows out is 0, and when S0 is low level, Q1 is selected, and 7 flow out from Q1, and the electric current that I1 flows out is 0;
When S1 is high level, I2 is selected, and 19 flow out from I2, and the electric current that Q2 flows out is 0, and when S1 is low level, Q2 is selected, and 19 flow out from Q2, and the electric current that I2 flows out is 0;
When S2 is high level, I3 is selected, and 28 flow out from I3, and the electric current that Q3 flows out is 0, and when S2 is low level, Q3 is selected, and 28 flow out from Q3, and the electric current that I3 flows out is 0;
When S3 is high level, I4 is selected, and 37 flow out from I4, and the electric current that Q4 flows out is 0, and when S3 is low level, Q4 is selected, and 37 flow out from Q4, and the electric current that I4 flows out is 0;
When S4 is high level, I5 is selected, and 91 flow out from I4, and the electric current that Q4 flows out is 0, and when S4 is low level, Q4 is selected, and 91 flow out from Q4, and the electric current that I4 flows out is 0.
In DAC, the drain electrode of M1 pipe is connected with the grid level of the source class of M3, M1, and the source class of M1 pipe is connected to the ground, and the grid level of M1 pipe is connected with the grid level of the drain electrode of M1, M5; The drain electrode of M3 pipe is connected with the grid level of I1, I2, I3, I4, I5, M3 pipe, and the source class of M3 pipe is connected with the drain electrode of M1 pipe; The grid level of M3 pipe is connected with the drain electrode of M3 pipe, and Ibias is connected with the biasing of I road voltage control Amplifier; The drain electrode of M2 pipe is connected with the grid level of the source class of M4, M2, and the source class of M2 pipe is connected to the ground, and the grid level of M2 pipe is connected with the grid level of 41 drain electrode, M6; The drain electrode of M4 pipe is connected with the grid level of Q1, Q2, Q3, Q4, Q5, M4 pipe, and the source class of M4 pipe is connected with the drain electrode of M2 pipe; The grid level of M4 pipe is connected with the drain electrode of M4 pipe, and Qbias is connected with the biasing of Q road voltage control Amplifier.
With reference to Fig. 4, analog adder 2 is comprised of I road phase quadrant controller 201, I road voltage control Amplifier 202, Q road phase quadrant controller 203, Q road voltage control Amplifier 204 and adder 205, and adder 205 is comprised of two nmos pass transistor M5 and M6;
M5 and M6 are respectively the tail current of I road voltage control Amplifier, Q road voltage control Amplifier, are used for controlling the gain of I road voltage control Amplifier and Q road voltage control Amplifier.Analog adder is added the output current of I road voltage control Amplifier and Q road voltage control Amplifier at node 1,2.
Adder 205 is output as the differential signal after phase shift; DAC3 output is connected with Q road voltage control Amplifier 204 with I road voltage control Amplifier 202; Logic encoder 4 inputs are connected with outside five digit number control signal, and logic encoder 4 output Yi roads are connected with DAC3 input, and another road of logic encoder 4 outputs is connected with Q road phase quadrant controller 203 with I road phase quadrant controller 201;
Under whole phase shifter five digit number signal controlling externally, one has 32 operating states, 32 corresponding 32 phase shift values of operating state, and phase shift value is 0 ° from minimum, stepping is 11.25 °.
I road phase quadrant controller 201 has four inputs and two outputs, wherein the difference output end V of two inputs and orthogonal signal generator 1
oI+, V
oI-be connected, another two input SI, SIN are the digital signals that receive from logic encoder 4, and wherein SIN is the non-of SI, and the output of I road phase quadrant controller 201 is connected with I road voltage control Amplifier 202;
Q road phase quadrant controller 203 has four inputs and two outputs, wherein the difference output end V of two inputs and orthogonal signal generator 1
oQ+, V
oQ-be connected, another two input SQ, SQN are the digital signals that receive from logic encoder 4, and wherein SQN is the non-of SQ, and the output of Q road phase quadrant controller 203 is connected with I road voltage control Amplifier 202;
The source of M5 is connected with the IDAC of DAC3 end, the source of M6 is connected with the end of the QDAC of DAC3, M5 and M6 be respectively as the tail current of I road voltage control Amplifier 202, Q road voltage control Amplifier 204, and the drain current of M5 and M6 has determined the gain of I road voltage control Amplifier 202, Q road voltage control Amplifier 204;
Phase shift value is to be determined by the gain of I road voltage control Amplifier 202 and Q road voltage control Amplifier 204, and the gain of I road voltage control Amplifier 202 and Q road voltage control Amplifier 204 is by the output voltage of DAC3 with determined by the electric current that flows into M1, M2 drain electrode.
Invention integrated circuit is comprised of orthogonal signal generator 1, analog adder 2, digital to analog converter DAC3 and logic encoder 4 herein; Circuit major part realizes with active device, and analog adder, the DAC of circuit the inside realize with active device, and metal-oxide-semiconductor is active device, so can realize very high integrated level; There is goodish gain simultaneously, in the situation that having power constraint, have very high numerical control precision; Input signal forms the differential signal of two-way quadrature after orthogonal signal generator 1; I road signal arrives one end of adder after phase quadrant controller, voltage control Amplifier, and Q road signal arrives one end, adder Ling road after phase quadrant controller, voltage control Amplifier; Adder is added the two paths of signals from I, Q, is then transferred to output; DAC3 converts analog signal to digital signal, and the analog signal after conversion is used for controlling voltage control Amplifier; Logic controller mainly completes the coding to five digit number control signal, and its output is used for controlling DAC and phase quadrant controller.
Phase shift value of the present invention is to be determined by the gain of I, Q two-way voltage control Amplifier, and the gain of I, Q two-way voltage control Amplifier is determined by the output voltage of DAC, is again by the electric current, the decision that flow into M1, M2 drain electrode.Orthogonal signal generator in the present invention adopts the passive RLC resonant network of second order, has higher linearity.For what realize orthogonal signal generator 1 two-way output difference sub-signal, keep the characteristic of quadrature in wider bandwidth, the quality factor of the passive RLC resonant network of second order can not be too large, preferably Q=1.
When the phase shifter in the present invention works in different conditions, in DAC3, flow into M1, M2 drain electrode electric current ,+remain unchanged, the amplitude of the differential signal of phase shifter output is also constant.
Tool of the present invention has the following advantages:
What phase-shift network in the present invention adopted is active network, has certain gain, and phase-shift network all has active device to form, and area occupied is little, can be highly integrated.The ratio of phase shift of the present invention by I road, Q road two-way realized, novel structure, and traditional phase shifter phase shift to be the passive network structure changing between input and output by switching tube realize.Phase shifter bandwidth of operation of the present invention is wide, and phase shifting accuracy is high.What the present invention adopted is CMOS technique, can utilize current silicon work to design and manufacture, can be for ultra broadband system on chip, and cost is low.
Claims (4)
1. five the active phase shifters of ultra broadband based on orthogonal vector modulation, is characterized in that: comprise orthogonal signal generator (1), analog adder (2), DAC (3) and logic encoder (4);
Wherein, input signal forms differential signal I road signal and the Q road signal of two-way quadrature after orthogonal signal generator (1);
Orthogonal signal generator (1) is exported to analog adder (2) by I road signal and Q road signal, and analog adder (2) is comprised of I road phase quadrant controller (201), Q road phase quadrant controller (203), I road voltage control Amplifier (202), Q road voltage control Amplifier (204) and adder (205); Wherein I road signal arrives one end of adder (205) after I road phase quadrant controller (201), I road voltage control Amplifier (202), and Q road signal arrives one end, adder (205) Ling road after Q road phase quadrant controller (203), Q road voltage control Amplifier (204); Adder (205) is exported from output after two paths of signals is added;
Logic encoder (4) mainly completes the coding to the five digit number control signal of outside input, and its output is used for controlling DAC (3), I road phase quadrant controller (201) and Q road phase quadrant controller (203);
DAC (3) is converting analog signal to from the digital signal of logic encoder (4) input, and the analog signal after conversion is used for controlling I road voltage control Amplifier (202) and Q road voltage control Amplifier (204) and adder (205).
2. according to a kind of five active phase shifters of ultra broadband based on orthogonal vector modulation described in claim 1, it is characterized in that: what described orthogonal signal generator (1) adopted is second order passive RLC resonant network, has a pair of differential input end V
in+, V
in-, two couples of difference output end V
oI+, V
oI-and V
oQ+, V
oQ-, two inductance L 1, L2, two capacitor C 1, C2, two resistance R 1, R2; Differential input end V wherein
in+be connected with one end of L1 and C1, V
in-be connected with one end of L2, C2, V
oI+be connected V with one end of R1 and the other end of C1
oI-be connected V with one end of R2 and the other end of C2
oQ+be connected with the other end of L1 and the other end of R2, V
oQ-be connected with the other end of L2 and the other end of R1.
3. according to a kind of five active phase shifters of ultra broadband based on orthogonal vector modulation described in claim 1, it is characterized in that: described DAC (3) is by 7 modules (301), 19 modules (302), 28 modules (303), 37 modules (304), 91 modules (305) and four NMOS transistors M1, M2, M3, M4 forms, wherein 7 modules (301) have two input port S0, S0N and two output port I1 and Q1, input port S0, S0N connects the digital signal of logic encoder (4), S0N is the non-of S0, output port I1 is connected with I road input current node, Q1 is connected with Q road input current node,
19 modules (302) have two input port S1, S1N and two output port I2 and Q2, S1, S1N are the digital signals fetching from described logic encoder (4), S1N is the non-of S1, and I2 is connected with I road input current node, and Q2 is connected with Q road input current node;
28 modules (303) have two input port S2, S2N and two output port I3 and Q3, S2, S2N are the digital signals fetching from described logic encoder (4), S2N is the non-of S2, and I3 is connected with I road input current node, and Q3 is connected with Q road input current node;
37 modules (304) have two input port S3, S3N and two output port I4 and Q4, S3, S3N are the digital signals fetching from described logic encoder (4), S3N is the non-of S3, and I3 is connected with I road input current node, and Q3 is connected with Q road input current node;
91 modules (305) have two input port S4, S4N and two output port I4 and Q4, S4, S4N are the digital signals fetching from described logic encoder (4), S4N is the non-of S4, and I4 is connected with I road input current node, and Q4 is connected with Q road input current node;
The drain electrode of M1 pipe is connected with the grid level of the source class of M3, M1, and the source class of M1 pipe is connected to the ground, and the grid level of M1 pipe is connected with the grid level of the drain electrode of M1, M5; The drain electrode of M3 pipe is connected with the grid level of I1, I2, I3, I4, I5, M3 pipe, and the source class of M3 pipe is connected with the drain electrode of M1 pipe; The grid level of M3 pipe is connected with the drain electrode of M3 pipe, and Ibias is connected with the biasing of I road voltage control Amplifier; The drain electrode of M2 pipe is connected with the grid level of the source class of M4, M2, and the source class of M2 pipe is connected to the ground, and the grid level of M2 pipe is connected with the grid level of 41 drain electrode, M6; The drain electrode of M4 pipe is connected with the grid level of Q1, Q2, Q3, Q4, Q5, M4 pipe, and the source class of M4 pipe is connected with the drain electrode of M2 pipe; The grid level of M4 pipe is connected with the drain electrode of M4 pipe, and Qbias is connected with the biasing of Q road voltage control Amplifier.
4. according to a kind of five active phase shifters of ultra broadband based on orthogonal vector modulation described in claim 1, it is characterized in that: described analog adder (2) is comprised of I road phase quadrant controller (201), I road voltage control Amplifier (202), Q road phase quadrant controller (203), Q road voltage control Amplifier (204) and adder (205), and adder (205) is comprised of two nmos pass transistor M5 and M6;
M5 and M6 are respectively the tail current of I road voltage control Amplifier (202), Q road voltage control Amplifier (204), be used for controlling the gain of I road voltage control Amplifier (202) and Q road voltage control Amplifier (204), adder (205) is added the output current of I road voltage control Amplifier (202) and Q road voltage control Amplifier (204), and adder (205) is output as the differential signal after phase shift.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410200749.0A CN103986439A (en) | 2014-05-13 | 2014-05-13 | Ultra-wide-band five-digit active phase shifter based on orthogonal vector modulation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410200749.0A CN103986439A (en) | 2014-05-13 | 2014-05-13 | Ultra-wide-band five-digit active phase shifter based on orthogonal vector modulation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103986439A true CN103986439A (en) | 2014-08-13 |
Family
ID=51278284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410200749.0A Pending CN103986439A (en) | 2014-05-13 | 2014-05-13 | Ultra-wide-band five-digit active phase shifter based on orthogonal vector modulation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103986439A (en) |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104483660A (en) * | 2014-12-25 | 2015-04-01 | 中国电子科技集团公司第四十一研究所 | Calibration method for microwave vector modulation in doppler signal simulation |
| CN104767501A (en) * | 2015-05-06 | 2015-07-08 | 中国科学技术大学 | Six-bit 360-degree active phase shifter based on ultrahigh frequency RFID application |
| CN105207644A (en) * | 2015-09-16 | 2015-12-30 | 电子科技大学 | On-chip active phase shifter based on vector synthesis |
| CN105610417A (en) * | 2015-12-28 | 2016-05-25 | 中国工程物理研究院电子工程研究所 | Phase tunable orthogonal signal generator based on coplanar waveguide slow wave structure |
| CN105915196A (en) * | 2016-05-17 | 2016-08-31 | 中国电子科技集团公司第三十八研究所 | CMOS width active phase shifter circuit |
| CN107124154A (en) * | 2017-03-30 | 2017-09-01 | 复旦大学 | A kind of high-precision active phase shifter in broadband |
| CN108767378A (en) * | 2018-04-27 | 2018-11-06 | 东南大学 | A kind of wideband orthogonal all-pass filter based on L-C resonance |
| CN109546987A (en) * | 2018-11-16 | 2019-03-29 | 西安电子科技大学 | Broadband active phase shifter |
| CN109586682A (en) * | 2018-09-30 | 2019-04-05 | 天津大学 | A kind of millimeter wave active orthogonal signal generator |
| CN109687839A (en) * | 2018-12-17 | 2019-04-26 | 中国电子科技集团公司第五十五研究所 | Active passive mixed type microwave phase shifter |
| CN110048692A (en) * | 2018-03-14 | 2019-07-23 | 平湖市奥特模星电子有限公司 | A kind of across the quadrant phase-moving method of vector addition phase shifter and circuit |
| CN110798171A (en) * | 2019-10-15 | 2020-02-14 | 浙江大学 | Hybrid broadband high-precision phase shifter integrated circuit |
| CN113572453A (en) * | 2021-09-23 | 2021-10-29 | 广州慧智微电子有限公司 | Multiphase phase shifter and multiphase phase shifting method |
| CN113572454A (en) * | 2021-09-27 | 2021-10-29 | 广州慧智微电子有限公司 | Multiphase phase shifter and multiphase phase shifting method |
| US11183973B1 (en) | 2020-06-02 | 2021-11-23 | Samsung Electronics Co., Ltd | Method and circuit for power consumption reduction in active phase shifters |
| US11349503B2 (en) * | 2020-08-24 | 2022-05-31 | Qualcomm Incorporated | Phase shifter with compensation circuit |
| US20220200781A1 (en) * | 2020-12-18 | 2022-06-23 | Intel Corporation | Wide-range inductor-based delay-cell and area efficient termination switch control |
| US11569555B2 (en) | 2019-12-06 | 2023-01-31 | Qualcomm Incorporated | Phase shifter with active signal phase generation |
-
2014
- 2014-05-13 CN CN201410200749.0A patent/CN103986439A/en active Pending
Cited By (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104483660A (en) * | 2014-12-25 | 2015-04-01 | 中国电子科技集团公司第四十一研究所 | Calibration method for microwave vector modulation in doppler signal simulation |
| CN104483660B (en) * | 2014-12-25 | 2017-02-22 | 中国电子科技集团公司第四十一研究所 | Calibration method for microwave vector modulation in doppler signal simulation |
| CN104767501B (en) * | 2015-05-06 | 2017-09-29 | 中国科学技术大学 | A kind of 6 360 ° of active phase shifters applied based on ultrahigh frequency RFID |
| CN104767501A (en) * | 2015-05-06 | 2015-07-08 | 中国科学技术大学 | Six-bit 360-degree active phase shifter based on ultrahigh frequency RFID application |
| CN105207644A (en) * | 2015-09-16 | 2015-12-30 | 电子科技大学 | On-chip active phase shifter based on vector synthesis |
| CN105207644B (en) * | 2015-09-16 | 2018-08-21 | 电子科技大学 | A kind of on-chip active phase shifter based on Vector modulation |
| CN105610417A (en) * | 2015-12-28 | 2016-05-25 | 中国工程物理研究院电子工程研究所 | Phase tunable orthogonal signal generator based on coplanar waveguide slow wave structure |
| CN105915196B (en) * | 2016-05-17 | 2018-09-04 | 中国电子科技集团公司第三十八研究所 | A kind of CMOS broadband actives phase shifter circuit |
| CN105915196A (en) * | 2016-05-17 | 2016-08-31 | 中国电子科技集团公司第三十八研究所 | CMOS width active phase shifter circuit |
| CN107124154A (en) * | 2017-03-30 | 2017-09-01 | 复旦大学 | A kind of high-precision active phase shifter in broadband |
| CN107124154B (en) * | 2017-03-30 | 2021-09-17 | 复旦大学 | Broadband high-precision active phase shifter |
| CN110048692A (en) * | 2018-03-14 | 2019-07-23 | 平湖市奥特模星电子有限公司 | A kind of across the quadrant phase-moving method of vector addition phase shifter and circuit |
| CN108767378A (en) * | 2018-04-27 | 2018-11-06 | 东南大学 | A kind of wideband orthogonal all-pass filter based on L-C resonance |
| CN109586682A (en) * | 2018-09-30 | 2019-04-05 | 天津大学 | A kind of millimeter wave active orthogonal signal generator |
| CN109546987A (en) * | 2018-11-16 | 2019-03-29 | 西安电子科技大学 | Broadband active phase shifter |
| CN109687839A (en) * | 2018-12-17 | 2019-04-26 | 中国电子科技集团公司第五十五研究所 | Active passive mixed type microwave phase shifter |
| CN109687839B (en) * | 2018-12-17 | 2022-08-19 | 中国电子科技集团公司第五十五研究所 | Active and passive mixed microwave phase shifter |
| CN110798171A (en) * | 2019-10-15 | 2020-02-14 | 浙江大学 | Hybrid broadband high-precision phase shifter integrated circuit |
| CN110798171B (en) * | 2019-10-15 | 2021-08-24 | 浙江大学 | Hybrid broadband high-precision phase shifter integrated circuit |
| US11569555B2 (en) | 2019-12-06 | 2023-01-31 | Qualcomm Incorporated | Phase shifter with active signal phase generation |
| US11183973B1 (en) | 2020-06-02 | 2021-11-23 | Samsung Electronics Co., Ltd | Method and circuit for power consumption reduction in active phase shifters |
| US11349503B2 (en) * | 2020-08-24 | 2022-05-31 | Qualcomm Incorporated | Phase shifter with compensation circuit |
| US20220200781A1 (en) * | 2020-12-18 | 2022-06-23 | Intel Corporation | Wide-range inductor-based delay-cell and area efficient termination switch control |
| CN113572453A (en) * | 2021-09-23 | 2021-10-29 | 广州慧智微电子有限公司 | Multiphase phase shifter and multiphase phase shifting method |
| CN113572454A (en) * | 2021-09-27 | 2021-10-29 | 广州慧智微电子有限公司 | Multiphase phase shifter and multiphase phase shifting method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103986439A (en) | Ultra-wide-band five-digit active phase shifter based on orthogonal vector modulation | |
| US9577600B2 (en) | Variable load for reflection-type phase shifters | |
| CN110212887B (en) | Radio frequency active phase shifter structure | |
| CN109687839B (en) | Active and passive mixed microwave phase shifter | |
| US9509363B2 (en) | Circuits having switches providing increased voltage swing uniformity | |
| US20100026411A1 (en) | Balun signal transformer and method of forming | |
| US20140155003A1 (en) | Quadrature hybrid coupler, amplifier, and wireless communication device | |
| EP2403140A2 (en) | Phase shifter | |
| CN103454654B (en) | Configurable matching network used at satellite navigation radio frequency front end | |
| CN109616723A (en) | A kind of high-precision phase shifter applied to 5G millimeter wave base station | |
| CN107707217A (en) | The broadband of high dB gains becomes six active phase shifters of mutual conductance | |
| CN107863949B (en) | X-band 5-phase shifter based on combination of active phase shifter and passive phase shifter | |
| CN111082765B (en) | Ultra-wideband two-position phase shifter | |
| CN113162581B (en) | Broadband digital phase shifter based on GaN HEMT device | |
| CN103618519B (en) | Ultra wide band high-linearity active phase shifter | |
| CN103066947A (en) | Ultra wide band large dynamic figure / analog compatible adjustable attenuator | |
| CN115865040A (en) | Variable gain active phase shifter capable of working bidirectionally | |
| CN203596804U (en) | Ultra-wideband high-linearity phase shifter | |
| CN104617948B (en) | Active width phase control circuit | |
| CN105006606B (en) | Radiofrequency signal phase-shift network | |
| CN115986344B (en) | Electrically-controlled differential phase shifter | |
| CN105915196B (en) | A kind of CMOS broadband actives phase shifter circuit | |
| CN113193851B (en) | Numerical control phase shifter for X wave band | |
| CN116598733A (en) | Millimeter wave phase shifter | |
| CN113452345B (en) | Broadband active phase shifter based on III-V group compound semiconductor process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140813 |
|
| RJ01 | Rejection of invention patent application after publication |