CN103944514A - Amplitude detection control circuit and numerical control crystal oscillator system - Google Patents
Amplitude detection control circuit and numerical control crystal oscillator system Download PDFInfo
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- CN103944514A CN103944514A CN201410176244.5A CN201410176244A CN103944514A CN 103944514 A CN103944514 A CN 103944514A CN 201410176244 A CN201410176244 A CN 201410176244A CN 103944514 A CN103944514 A CN 103944514A
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Abstract
The invention relates to an amplitude detection control circuit of a numerical control crystal oscillator and a numerical control crystal oscillator system. The amplitude detection control circuit comprises a peak detection circuit, a control circuit and a compensation output circuit. The peak detection circuit comprises a forward peak detection unit, a reverse peak detection circuit and a compensation unit, wherein the forward peak detection unit is used for detecting forward peak voltages of the oscillator to obtain first detection voltages, the reverse peak detection unit is used for detecting reverse peak voltages of the oscillator to obtain second detection voltages, and the compensation unit is used for compensating the first detection voltages to obtain third detection voltages. The control circuit processes the third detection voltages and the second detection voltages to generate control voltages. The compensation output circuit generates control currents according to the control voltages for controlling and compensating the amplitude of the oscillator.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of amplitude detecting control circuit and digitally controlled crystal oscillator system.
Background technology
Digital control crystal oscillator (DCXO) circuit is used widely in Modern wireless communication chip system.Conventionally consist of the following components: the monofier of the required negative resistance of vibration is provided, guarantees amplitude detecting and the control circuit of starting of oscillation, some designs also can add that temperature-compensation circuit revises the drift of the frequency of oscillation that variations in temperature brings.Wherein, oscillation amplitude detection and control circuit are used for guaranteeing starting of oscillation and/or start fast.
Oscillation amplitude detects and control circuit has two kinds of common approach that realize of Digital and analog.In Digital Implementation mode, conventionally can require extra clock input, and because the delay on clock zone cannot be accomplished real-time control, therefore can affect the reliability of circuit.In simulation implementation, can provide the real-time control of amplitude also without the need for the input of extra clock, but the detection threshold of its use can change with the variation of technique, supply voltage and temperature (PVT), thereby affect the reliability of circuit.Other amplitude detecting also can be introduced extra making an uproar mutually and loading problem with control circuit.
Summary of the invention
The object of this invention is to provide a kind of amplitude detecting control circuit and digitally controlled crystal oscillator system, wherein amplitude detecting control circuit can carry out stable detection to the shock range of monofier, and according to the shock range of testing result compensating digits control crystal oscillator, make it constant, effectively raise the reliability of digital control crystal-oscillator circuit.
First aspect, the embodiment of the present invention provides a kind of amplitude detecting control circuit of digitally controlled crystal oscillator, it is characterized in that, and described amplitude detecting control circuit comprises: peak detection circuit, control circuit and compensation output circuit;
Described peak detection circuit comprises:
Forward peak detection unit, detects for the peak forward voltage to oscillator, obtains the first detection voltage;
Reversed peak detecting unit, detects for the peak-inverse voltage to oscillator, obtains the second detection voltage;
Compensating unit, be connected with described forward peak detection unit, for detecting voltage to described first, compensate, obtain the 3rd and detect voltage, second voltage difference that detect voltage and peak-inverse voltage between of described compensation in order to introduce offset reversed peak detecting unit in the first detection voltage in;
Described control circuit is processed for described the 3rd detection voltage and second is detected to voltage, produces and controls voltage;
Described compensation output circuit generates and controls electric current according to described control voltage, for compensating the shock range of described digitally controlled crystal oscillator.
Preferably, stating forward peak detection unit specifically comprises: the first N-type Metal-oxide-semicondutor nmos pass transistor M1, DC bias circuit and the first capacitor C 1;
Wherein, described DC bias circuit specifically comprises: the first current source, biasing feedback circuit and current mirror;
Described the first current source is for providing the first constant electric current I 1 to described current mirror;
Described biasing feedback circuit is for providing operating voltage to described current mirror;
The grid access monofier output signal of described the first nmos pass transistor;
The two ends of described the first capacitor C 1 connect respectively source electrode and the ground of described the first nmos pass transistor M1;
Described current mirror specifically comprises the second nmos pass transistor M6 and the 3rd nmos pass transistor M5, described the second nmos pass transistor M6 is total to grid common source with the 3rd nmos pass transistor M5 and is connected, the input that described the second nmos pass transistor M6 is described current mirror, be connected in series with described the first current source, described the first nmos pass transistor M1 and described the 3rd nmos pass transistor M5 are connected in series, and are the output of described current mirror; Wherein, described biasing feedback circuit for the second nmos pass transistor M6 and the 3rd nmos pass transistor M5 altogether grid end conducting voltage is provided, described biasing feedback circuit is that the second nmos pass transistor M6 and the 3rd nmos pass transistor M5 mate in the first ratio so that described in flow through the 3rd nmos pass transistor M6 and the first nmos pass transistor M5 the second electric current and described the first electric current there is the first proportionate relationship;
The source electrode of described the first nmos pass transistor M1 is the output of forward peak detection unit, and output first detects voltage.
Further preferred, described biasing feedback circuit specifically comprises: the first operational amplifier and the 4th nmos pass transistor M7;
The positive input access reference circuit voltage of described the first operational amplifier, the output voltage of the source electrode of reverse input end access the 4th nmos pass transistor M7, output connects the grid of the 4th nmos pass transistor M7, by the gain of described the first operational amplifier, control described the 4th nmos pass transistor and continue conducting, so that the electric current I 1 of described the first current source is inputted the drain electrode of described the second nmos pass transistor M6 after described the 4th nmos pass transistor M7.
Preferably, described compensating unit specifically comprises: a PMOS transistor M2 and the second current source I
0a; Described inverted peaks detecting unit specifically comprises: the 2nd PMOS transistor M3, the 3rd current source I
0bwith the second capacitor C 2;
The second current source I
0abe serially connected in the source electrode of a PMOS transistor M2, to a PMOS transistor M2, provide constant On current I
0a; The 3rd current source I
0bbe serially connected in the source electrode of the 2nd PMOS transistor M3, to the 2nd PMOS transistor M3, provide constant On current I
0b; Wherein, control the second current source I
0a, the 3rd current source I
0b, the electric current that flows through a described PMOS transistor M2 is equated, so that the conduction voltage drop V of a PMOS transistor M2 with the electric current that flows through described the 2nd PMOS transistor M3
gS2conduction voltage drop V with the 2nd PMOS transistor M3
gS3identical;
The grid of the one PMOS transistor M2 accesses first of described forward peak detection unit output and detects voltage, and source electrode is connected with an input of control circuit; The grid access input monofier output signal of the 2nd PMOS transistor M3, source electrode is connected with another input of control circuit; A described PMOS transistor M2 and the 2nd PMOS transistor M3 common drain ground connection.
Preferably, described control circuit specifically comprises the second operational amplifier, and described control circuit specifically comprises controllable current source;
The positive input access the 3rd of described the second operational amplifier detects voltage, and reverse input end access second detects voltage, generates output voltage; Described output voltage is for controlling the size of the control electric current of described controllable current source generation.
Further preferred, described the second operational amplifier is specially limiting amplifier.
Preferably, described amplitude detecting control circuit also comprises switching circuit, and described switching circuit, for obtaining calculating crest voltage according to described control electric current, is compared with reference voltage, and according to comparative result, determined unlatching or the shutoff of described compensation output circuit.
Further preferred, described switching circuit specifically comprises: the first resistance R 1, the first comparator and delay unit;
Described the first resistance is connected between the positive input and ground end of the first comparator, and described control electric current is through the first resistance inflow place end;
Described the first comparator compares described calculating crest voltage and comparison reference voltage, output comparative result;
Described delay unit is for carrying out time delay to the comparative result of described the first comparator, and generative circuit switch controlling signal, for controlling unlatching or the shutoff of described control circuit.
Further preferred, described delay unit specifically comprises counter, clock divider and clock switch unit;
The clock signal of described digitally controlled crystal oscillator output is accepted in described clock switch unit, after clock divider is processed for described the first comparator provides clock signal input;
Described counter carries out time delay in order to realize to the comparative result of described the first comparator, and by clock switch unit described in described comparative result FEEDBACK CONTROL.
Preferably, described the first resistance R 1=V
th/ I
ctrl_th; V wherein
thfor threshold voltage, I
ctrl_thfor allowing to turn-off the minimum current value of described amplitude detecting control circuit in oscillating circuit.
Second aspect, the embodiment of the present invention provides a kind of digitally controlled crystal oscillator system, comprising: monofier, with reference to generative circuit and the amplitude detecting control circuit as described in above-mentioned first aspect.
Amplitude detecting control circuit provided by the invention and digitally controlled crystal oscillator system, can carry out stable detection to the shock range of monofier, and according to the shock range of testing result compensating digits control crystal oscillator, make it constant, effectively raise the reliability of digital control crystal oscillator system.
Accompanying drawing explanation
The circuit diagram of a kind of amplitude detecting control circuit that Fig. 1 provides for the embodiment of the present invention;
The circuit diagram of a kind of forward peak detection unit that Fig. 2 provides for the embodiment of the present invention;
The circuit diagram of a kind of switching circuit that Fig. 3 provides for the embodiment of the present invention;
The schematic diagram of the digitally controlled crystal oscillator system that Fig. 4 provides for the embodiment of the present invention.
Below in conjunction with drawings and Examples, the present invention is described in detail.
Embodiment
The embodiment of the present invention provides a kind of amplitude detecting control circuit of digitally controlled crystal oscillator, can carry out stable detection to the shock range of monofier, and according to the shock range of testing result compensating digits control crystal oscillator, make it constant, effectively raise the reliability of digital control crystal-oscillator circuit.
The circuit diagram of the low-power consumption oscillator that Fig. 1 provides for the embodiment of the present invention.As shown in Figure 1, described amplitude detecting control circuit comprises: peak detection circuit 1, control circuit 2 and compensation output circuit 4;
Described peak detection circuit 1 comprises:
Forward peak detection unit 11, for the peak forward voltage V to oscillator
pk, posdetect, obtain the first detection voltage V
pPK0;
Reversed peak detecting unit 12, for the peak-inverse voltage V to oscillator
pk, negdetect, obtain the second detection voltage V
nPK;
Compensating unit 13, is connected with described forward peak detection unit 11, for detecting voltage V to described first
pPK0compensate, obtain the 3rd and detect voltage V
pPK, described compensation is in order at the first detection voltage V
pPK0the the second detection voltage V introducing in middle counteracting reversed peak detecting unit 12
nPKwith peak-inverse voltage V
pk, negbetween voltage difference;
Control circuit 2 is for detecting voltage V to the 3rd
pPKwith the second detection voltage V
nPKprocess, produce and control voltage V
ctrl;
Compensation output circuit 4 is according to controlling voltage V
ctrlgenerate and control electric current I
ctrl, control electric current I
ctrlfor the shock range of digitally controlled crystal oscillator is compensated.
Concrete, forward peak detection unit 11 specifically comprises: the first N-type Metal-oxide-semicondutor nmos pass transistor M1, DC bias circuit 14 and the first capacitor C 1; The grid input monofier output signal XTAL_IN of the first nmos pass transistor M1, detects voltage V by source electrode output first
pPK0;
Wherein, the first detection voltage is:
V
pPK0=V
pk, pos-V
gS1(formula 1)
V wherein
pk, posfor the peak forward voltage of monofier output signal, V
gS1it is the grid source conduction voltage drop of the first nmos pass transistor M1.
Compensating unit 13 specifically comprises: a PMOS transistor M2 and the second current source I
0a; The 3rd detect voltage V
pPKfor:
V
pPK=V
pPK0+ V
gS2=V
pk, pos-V
gS1+ V
gS2(formula 2)
Wherein, V
gS1it is the grid source conduction voltage drop of a PMOS transistor M2.
Inverted peaks detecting unit 12 specifically comprises: the 2nd PMOS transistor M3, the 3rd current source I
0bwith the second capacitor C 2; Second detect voltage V
nPKfor:
V
nPK=V
pk, neg+ V
gS3(formula 3)
Wherein, V
gS3it is the grid source conduction voltage drop of the 2nd PMOS transistor M3; V
pk, negpeak-inverse voltage for monofier output signal.
Hence one can see that, to the detection threshold of the amplitude of digitally controlled crystal oscillator output, is to meet:
V
pk, pos-V
gS1+ V
gS2>V
pk, neg+ V
gS3(formula 4)
If the electric current I on a PMOS transistor M2
0awith the electric current I on the 2nd PMOS transistor M3
0bequate or proportional, V
gS2=V
gS3.
Thus, the amplitude detecting thresholding of this circuit is for meeting:
V
pp=V
pk, pos-V
pk,
neg>V
gS1(formula 5)
Wherein, V
pppeak-peak voltage for monofier output signal.
Can, by controlling the second current source, the 3rd current source, the electric current that flows through a PMOS transistor M2 be equated, so that the conduction voltage drop V of a PMOS transistor M2 with the electric current that flows through described the 2nd PMOS transistor M3 thus
gS2conduction voltage drop V with the 2nd PMOS transistor M3
gS3identical.
Control circuit 2 specifically comprises the second operational amplifier OPAMP2; Wherein OPAMP2 can be specially limiting amplifier.
Compensation output circuit 4 comprises controllable current source 21.
The positive input access the 3rd of the second operational amplifier OPAMP2 detects voltage V
pPK, reverse input end access second detects voltage V
nPK, output voltage V
ctrlthe control electric current I producing for controlling described controllable current source 21
ctrlsize.
Further, in forward peak detection unit 11, V
gS1meeting change because being subject to the impact of PVT process corner (PVTcorner), thereby causes the amplitude off-design requirement of DCXO.In this present invention, mainly the design by the DC bias circuit 14 in forward peak detection unit 11 makes V
gS1the impact that not changed by PVT.As shown in Figure 2, DC bias circuit 14 specifically comprises: the first current source 111, biasing feedback circuit 112 and current mirror 113;
The first current source 111, for DC bias circuit 14 provides reference current;
Biasing feedback circuit 112 specifically comprises: the first operational amplifier OPAMP1 and the 4th nmos pass transistor M7; The positive input access reference circuit voltage V of the first operational amplifier OPAMP1
rEFthe output voltage of the source electrode of reverse input end access the 4th nmos pass transistor M7, output connects the grid of the 4th nmos pass transistor M7, by the gain of the first operational amplifier OPAMP1, amplify and control the gate voltage of exporting to the 4th nmos pass transistor M7, make the 4th nmos pass transistor M7 continue conducting, so that the electric current of the first current source 111 after the 4th nmos pass transistor M7 as the input current of current mirror 113, input current mirror 113.
The two ends of described the first capacitor C 1 connect respectively source electrode and the ground of the first nmos pass transistor M1; The maximum potential of the first capacitor C 1 for keeping occurring on M1 source class.
Current mirror 113 specifically comprises the second nmos pass transistor M6 and the 3rd nmos pass transistor M5, and the second nmos pass transistor M6 is total to grid common source with the 3rd nmos pass transistor M5 and is connected, and the second nmos pass transistor M6 is the input of current mirror 113, connects with the first current source 111; The first nmos pass transistor M1 and the 3rd nmos pass transistor M5 are connected in series, and are the output of current mirror 113; Wherein, the second nmos pass transistor M6 is total to the 3rd nmos pass transistor M5 the reverse input end that grid are connected the first operational amplifier of the feedback circuit 112 of setovering, for the second nmos pass transistor M6 and the 3rd nmos pass transistor M5 of current mirror 113 provides gate voltage, make current mirror 113 in running order, so that flow through the second electric current I 2 of the 3rd nmos pass transistor M5 and the first nmos pass transistor M1, there is fixing proportionate relationship with described the first electric current I 1.
Set M1, the ratio of the breadth length ratio W/L of the conducting channel between M5 and M6 is N:N:1, and N is positive integer.The current relationship by M1 and M6 can be as shown in the formula expression:
I
2=NI
1(formula 6)
?
Wherein, μ
0for electron mobility, C
oxfor unit-area capacitance, V
tHNconduction voltage drop for M5, M6.
Hence one can see that, V
gS1=V
rEF(formula 8)
V like this
gS1be no longer dependent on PVT corners.Supporting that in the technique of dark N trap or P trap, the bulk effect of M1 threshold voltage can be by being connected bulk to eliminate with source.So in this circuit, the amplitude of the DCXO after compensation is constant.
V
pp=V
gS1=V
rEF(formula 9)
The embodiment of the present invention provides a kind of amplitude detecting control circuit of digitally controlled crystal oscillator, can carry out stable detection to the shock range of monofier, and according to the shock range of testing result compensating digits control crystal oscillator, make it constant, effectively raise the reliability of digital control crystal-oscillator circuit.
In addition, the embodiment of the present invention also provides a kind of switching circuit, for guaranteeing at digitally controlled crystal oscillator, under the prerequisite of starting of oscillation and amplitude, controls the compensation output circuit turn-offing in amplitude detecting control circuit.
Specifically as shown in Figure 3, switching circuit 3 specifically comprises: the first resistance R 1, the first comparator 31 and delay unit 32;
The first resistance R 1 is connected between the positive input and ground end of the first comparator 31, by aforementioned amplitude detecting control circuit I
ctrlthe control electric current producing is replicated and through the first resistance R 1 inflow place end;
The first 31 pairs of comparators calculate crest voltage V
pPK1with comparison reference voltage V
tHcompare output comparative result; Wherein, calculate crest voltage V
pPK1be the first resistance R 1 and control electric current I
ctrlproduct;
Concrete, the first resistance R 1=V
th/ I
ctrl_th(formula 10)
V wherein
thfor threshold voltage, I
ctrl_thfor allowing to turn-off the lowest high-current value of described amplitude detecting control circuit in oscillating circuit.
Delay unit 32 is for carrying out time delay to the comparative result of the first comparator 31 outputs, and generative circuit switch controlling signal PWRDOWN, for controlling unlatching or the shutoff of described control circuit.
Concrete, delay unit 32 has comprised 321, one clock dividers 322 of a counter and clock switch unit 323 thereof.Control electric current I when control circuit
ctrl< (V
th/ R1), time, the first comparator 31 is output as " 1 ".The clock of the first comparator 31 is from the output of DCXO, and therefore, only in the situation that the monofier starting of oscillation of DCXO, switching circuit just can be worked.By counter, realize the time delay to the first comparator 31 output signals, take and guarantee that the first comparator 31 continuous wave outputs are in the situation of " 1 ", cut-off signals PWRDOWN is " 1 ", and control circuit is turn-offed.Can avoid thus the shutoff false triggering causing because of voltage, electric current shakiness.Therefore by delay unit 32, can prevent the generation of false triggering.
Switching circuit 3 can guarantee in the situation that DCXO starting of oscillation and amplitude are enough large, closes compensation output circuit to eliminate unnecessary making an uproar mutually and load.
Accordingly, the embodiment of the present invention also provides a kind of digitally controlled crystal oscillator system, as shown in Figure 4, comprising: monofier 6, with reference to generative circuit (not shown) and the amplitude detecting control circuit 5 as described in above-described embodiment.
Although in the present invention, having used the common source configuration based on NMOS pipe is the design that example has realized amplitude detecting control circuit 5, in other specific implementation, can also adopt the mode of common leakage or common grid to realize.
Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only the specific embodiment of the present invention; the protection range being not intended to limit the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (11)
1. an amplitude detecting control circuit for digitally controlled crystal oscillator, is characterized in that, described amplitude detecting control circuit comprises: peak detection circuit, control circuit and compensation output circuit;
Described peak detection circuit comprises:
Forward peak detection unit, detects for the peak forward voltage to oscillator, obtains the first detection voltage;
Reversed peak detecting unit, detects for the peak-inverse voltage to oscillator, obtains the second detection voltage;
Compensating unit, be connected with described forward peak detection unit, for detecting voltage to described first, compensate, obtain the 3rd and detect voltage, second voltage difference that detect voltage and peak-inverse voltage between of described compensation in order to introduce offset reversed peak detecting unit in the first detection voltage in;
Described control circuit is processed for described the 3rd detection voltage and second is detected to voltage, produces and controls voltage;
Described compensation output circuit generates and controls electric current according to described control voltage, for compensating the shock range of described digitally controlled crystal oscillator.
2. amplitude detecting control circuit according to claim 1, is characterized in that, described forward peak detection unit specifically comprises: the first N-type Metal-oxide-semicondutor nmos pass transistor M1, DC bias circuit and the first capacitor C 1;
Wherein, described DC bias circuit specifically comprises: the first current source, biasing feedback circuit and current mirror;
Described the first current source is for providing the first constant electric current I 1 to described current mirror;
Described biasing feedback circuit is for providing operating voltage to described current mirror;
The grid access monofier output signal of described the first nmos pass transistor;
The two ends of described the first capacitor C 1 connect respectively source electrode and the ground of described the first nmos pass transistor M1;
Described current mirror specifically comprises the second nmos pass transistor M6 and the 3rd nmos pass transistor M5, described the second nmos pass transistor M6 is total to grid common source with the 3rd nmos pass transistor M5 and is connected, the input that described the second nmos pass transistor M6 is described current mirror, be connected in series with described the first current source, described the first nmos pass transistor M1 and described the 3rd nmos pass transistor M5 are connected in series, and are the output of described current mirror; Wherein, described biasing feedback circuit for the second nmos pass transistor M6 and the 3rd nmos pass transistor M5 altogether grid end conducting voltage is provided, described biasing feedback circuit is that the second nmos pass transistor M6 and the 3rd nmos pass transistor M5 mate in the first ratio so that described in flow through the 3rd nmos pass transistor M6 and the first nmos pass transistor M5 the second electric current and described the first electric current there is the first proportionate relationship;
The source electrode of described the first nmos pass transistor M1 is the output of forward peak detection unit, and output first detects voltage.
3. amplitude detecting control circuit according to claim 2, is characterized in that, described biasing feedback circuit specifically comprises: the first operational amplifier and the 4th nmos pass transistor M7;
The positive input access reference circuit voltage of described the first operational amplifier, the output voltage of the source electrode of reverse input end access the 4th nmos pass transistor M7, output connects the grid of the 4th nmos pass transistor M7, by the gain of described the first operational amplifier, control described the 4th nmos pass transistor and continue conducting, so that the electric current I 1 of described the first current source is inputted the drain electrode of described the second nmos pass transistor M6 after described the 4th nmos pass transistor M7.
4. amplitude detecting control circuit according to claim 1, is characterized in that, described compensating unit specifically comprises: a PMOS transistor M2 and the second current source I
0a; Described inverted peaks detecting unit specifically comprises: the 2nd PMOS transistor M3, the 3rd current source I
0bwith the second capacitor C 2;
The second current source I
0abe serially connected in the source electrode of a PMOS transistor M2, to a PMOS transistor M2, provide constant On current I
0a; The 3rd current source I
0bbe serially connected in the source electrode of the 2nd PMOS transistor M3, to the 2nd PMOS transistor M3, provide constant On current I
0b; Wherein, control the second current source I
0a, the 3rd current source I
0b, the electric current that flows through a described PMOS transistor M2 is equated, so that the conduction voltage drop V of a PMOS transistor M2 with the electric current that flows through described the 2nd PMOS transistor M3
gS2conduction voltage drop V with the 2nd PMOS transistor M3
gS3identical;
The grid of the one PMOS transistor M2 accesses first of described forward peak detection unit output and detects voltage, and source electrode is connected with an input of control circuit; The grid access monofier output signal of the 2nd PMOS transistor M3, source electrode is connected with another input of control circuit; A described PMOS transistor M2 and the 2nd PMOS transistor M3 common drain ground connection.
5. amplitude detecting control circuit according to claim 1, is characterized in that, described control circuit specifically comprises the second operational amplifier, and described compensation output circuit specifically comprises controllable current source;
The positive input access the 3rd of described the second operational amplifier detects voltage, and reverse input end access second detects voltage, generates output voltage; Described output voltage is for controlling the size of the control electric current of described controllable current source generation.
6. amplitude detecting control circuit according to claim 5, is characterized in that, described the second operational amplifier is specially limiting amplifier.
7. amplitude detecting control circuit according to claim 1, it is characterized in that, described amplitude detecting control circuit also comprises switching circuit, described switching circuit is for obtaining calculating crest voltage according to described control electric current, compare with reference voltage, and according to comparative result, determine unlatching or the shutoff of described compensation output circuit.
8. amplitude detecting control circuit according to claim 7, is characterized in that, described switching circuit specifically comprises: the first resistance R 1, the first comparator and delay unit;
Described the first resistance is connected between the positive input and ground end of the first comparator, and described control electric current is through the first resistance inflow place end;
Described the first comparator compares described calculating crest voltage and comparison reference voltage, output comparative result;
Described delay unit is for carrying out time delay to the comparative result of described the first comparator, and generative circuit switch controlling signal, for controlling unlatching or the shutoff of described compensation output circuit.
9. amplitude detecting control circuit according to claim 8, is characterized in that, described delay unit specifically comprises counter, clock divider and clock switch unit;
The clock signal of described digitally controlled crystal oscillator output is accepted in described clock switch unit, after clock divider is processed for described the first comparator provides clock signal input;
Described counter carries out time delay in order to realize to the comparative result of described the first comparator, and by clock switch unit described in described comparative result FEEDBACK CONTROL.
10. amplitude detecting control circuit according to claim 8, is characterized in that, described the first resistance R 1=V
th/ I
ctrl_th; V wherein
thfor threshold voltage, I
ctrl_thfor allowing to turn-off the minimum current value of described amplitude detecting control circuit in oscillating circuit.
11. 1 kinds of digitally controlled crystal oscillator systems, is characterized in that, described system comprises: monofier, with reference to the amplitude detecting control circuit as described in generative circuit and claim as arbitrary in the claims 1-10.
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| CN108781056A (en) * | 2017-02-24 | 2018-11-09 | 深圳市汇顶科技股份有限公司 | Crystal oscillator and its control circuit |
| CN111786634A (en) * | 2020-07-11 | 2020-10-16 | 重庆百瑞互联电子技术有限公司 | Crystal oscillator, oscillation signal generation method, storage medium and equipment |
| CN112882529A (en) * | 2020-12-31 | 2021-06-01 | 广州润芯信息技术有限公司 | Swing amplitude detection circuit with DC offset elimination |
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|---|---|---|---|---|
| CN106330145A (en) * | 2015-06-26 | 2017-01-11 | 深圳市中兴微电子技术有限公司 | Crystal oscillator circuit and control method of output signal amplitude |
| WO2017000571A1 (en) * | 2015-06-29 | 2017-01-05 | 深圳市中兴微电子技术有限公司 | Crystal oscillator circuit and method for controlling output signal amplitude thereof |
| WO2018094893A1 (en) * | 2016-11-22 | 2018-05-31 | 深圳市中兴微电子技术有限公司 | Method and device for calibrating signal amplitude, and computer storage medium |
| CN108781056A (en) * | 2017-02-24 | 2018-11-09 | 深圳市汇顶科技股份有限公司 | Crystal oscillator and its control circuit |
| CN108781056B (en) * | 2017-02-24 | 2022-03-25 | 深圳市汇顶科技股份有限公司 | Crystal oscillator and control circuit thereof |
| CN111786634A (en) * | 2020-07-11 | 2020-10-16 | 重庆百瑞互联电子技术有限公司 | Crystal oscillator, oscillation signal generation method, storage medium and equipment |
| CN112882529A (en) * | 2020-12-31 | 2021-06-01 | 广州润芯信息技术有限公司 | Swing amplitude detection circuit with DC offset elimination |
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|---|---|
| CN103944514B (en) | 2017-06-16 |
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