CN103855149A - Inverted high-voltage light-emitting diode and manufacturing method thereof - Google Patents
Inverted high-voltage light-emitting diode and manufacturing method thereof Download PDFInfo
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Abstract
An inverted high-voltage light-emitting diode comprises an LED chip and a supporting substrate. The LED chip comprises a plurality of LED chip units, and each LED chip unit is welded to the supporting substrate in an inverted mode. Each LED chip unit comprises an n-type semiconductor layer, a p-type semiconductor layer, an active layer, a p electrode bonding pad and an n electrode bonding pad. The n electrode bonding pad comprises three electrified connected parts which are an n contact electrode part located on the surface of the n-type semiconductor layer, a connecting part located on the side wall of a table board and a welding part extending to the position above the p-type semiconductor layer, wherein only part of the side wall of the table board is covered with the connecting part, and the connecting part is electrically isolated from the side wall of the table board through an insulating layer; the welding part is electrically isolated from the p-type semiconductor layer and the p electrode bonding pad, and the welding part is used for being welded to the connected bonding pads on the supporting substrate. The inverted high-voltage light-emitting diode is used for solving the problem that in the inverted mounting process, because the contact area is small, the reliability is poor, and the utilization rate of an active area of the chip can be increased.
Description
Technical field
The present invention relates to a kind of high pressure light-emitting diode chip structure and preparation method thereof.More specifically, the present invention relates to a kind of high pressure light-emitting diode chip that is more suitable for face-down bonding and preparation method thereof.
Background technology
Light-emitting diode (LED) has life-span length, energy-saving and environmental protection, coloury advantage, therefore, along with the development of the technology such as extension, chip, encapsulation, the further raising of luminous efficiency, LED by progressively for illumination, show, medical treatment etc. every field.Traditional gallium nitride based light emitting diode is operated under direct voltage, and voltage range is at 2.9-3.5V, and operating current is generally 20mA.In order to allow light-emitting diode reach the required brightness of general lighting, more than generally the operating current of LED chip will being brought up to 100mA, at present conventional have 100mA, 350mA and a 700mA.In the time that LED is used for to general lighting, need the electric main of 220V-380V left and right to drive, if adopt the high-capacity LED chip of large electric current, in drive unit, need a larger transformer, need, by filter rectifier, alternating current is transformed into direct current simultaneously, thereby cause whole LED light fixture volume larger, the life-span also reduces greatly due to the introducing of electrochemical capacitor (life-span is only 2000-5000 hour).In addition, the line loss that large driven current density causes is also higher, thereby causes the energy consumption of waste to increase, and the burden of light fixture heat radiation also increases.
In US Patent No. 6787999, adopt the mode of series connection to be arranged on PCB substrate single light-emitting diode good many individual packages and form high-voltage LED array, for high pressure occasion.This scheme can be saved the transformer that volume is larger, also can reduce operating current.But this scheme increases the volume of illuminating module greatly, and because each tube core is again by pin interconnection, processing procedure complexity, and a large amount of interconnection lines brings and is in the light and the problem such as reliability decrease.In addition,, because light source area is larger, be unfavorable for secondary optical design and luminous intensity distribution.
In the open CN102867837A of Chinese invention patent application, disclose a kind of in Sapphire Substrate by the LED array of deep trench isolation, the LED that has realized chip-scale is integrated, reduce the encapsulation volume of illuminating module, adopt chip-scale layer metal interconnection to replace pin interconnection, improved the reliability of LED array.
But, in the technical scheme of CN102867837A, as Fig. 1, owing to epitaxial loayer will being etched into Sapphire Substrate 10 from p-type layer 13, needing etching depth is the isolation deep trouth 101 of 4-7um, make interconnection line 20 between each LED unit 100 owing to getting over so dark isolation deep trouth 101 reliability variation, thereby cause the rate of finished products of high-voltage LED chip and working life greatly to reduce.
In addition, for the high-voltage LED of positive assembling structure, LED array is positioned in the poor Sapphire Substrate of thermal conductivity, spacing between each LED unit is also smaller, the heat that multiple LED unit produces affects each other, relatively concentrates and be difficult to again distribute, therefore, heat radiation is that formal dress high-voltage LED is applied the difficult problem facing.
Adopt inverted structure being interconnected on flip-chip substrate between luminescence unit can be completed, can solve because interconnection line gets over the integrity problem that deep trench causes, heat can be conducted from the upside-down mounting support substrates of high heat conductance simultaneously.But, when LED chip is arranged on flip-chip substrate, need p and n electrode zone enough large, to meet the requirement of aligning and installation reliability.But the area that increases n mesa region will inevitably be sacrificed active region area, reduce the light output variable of chip.
In prior art, there is the plug type n of employing electrode, then avoid large-area mesa etch by two-layer wiring, but less owing to leading to the jack diameter of N-GaN, often can in jack, form leak channel, cause the poor reliability of LED.
Therefore, need a kind of p and n electrode zone enough to meet the upside-down mounting high pressure chip structure of installation reliability requirement, the while can solve heat dissipation problem and interconnection line gets over the integrity problem that deep trouth brings.
Summary of the invention
The object of the invention is to, a kind of high pressure light-emitting diode chip structure and manufacture method are provided, for solving the problem of the poor reliability that upside-down mounting installation process causes because contact area is little, and can improve the utilance of chip active area.
The invention provides a kind of upside-down mounting high-voltage LED, comprise LED chip and supporting substrate; Described LED chip comprises multiple LED chips unit, and described each LED chip face-down bonding is on supporting substrate; Described each LED chip unit comprises N-shaped semiconductor layer, p-type semiconductor layer, active layer, p electrode pad and n electrode pad;
Three parts that wherein said n electrode pad comprises electrical interconnection:
Be positioned at the n contact electrode part of N-shaped semiconductor layer surface;
Be positioned at the coupling part on table top sidewall, described coupling part is cover part table top sidewall only, and by insulating barrier and the isolation of table top sidewall electricity;
With the welding portion that extends to p-type semiconductor layer top, described welding portion and p-type semiconductor layer and the isolation of p electrode pad electricity, described welding portion for supporting substrate on interconnect pad weld.
The present invention also provides a kind of manufacture method of upside-down mounting high-voltage LED, comprises following steps:
On the epitaxial wafer that comprises N-shaped semiconductor layer, p-type semiconductor layer and active layer, form table top, expose N-shaped semiconductor layer;
On p-type semiconductor layer, form high reflectance p electrode;
Form insulating barrier at high reflectance p electrode surface and table top sidewall;
Patterned insulator layer is also made p electrode pad, and described p electrode pad is electrically connected with high reflectance p electrode;
Form n electrode pad, three parts that described n electrode pad comprises electrical interconnection:
Be positioned at the n contact electrode part of N-shaped semiconductor layer surface;
Be positioned at the coupling part on table top sidewall, described coupling part is cover part table top sidewall only;
With the welding portion that extends to p-type semiconductor layer top, described welding portion and high reflectance p electrode and the isolation of p electrode pad electricity;
By described welding portion 171, LED chip and supporting substrate are welded.
Brief description of the drawings
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail, wherein:
Fig. 1 is according to the sectional view of the LED chip unit of first embodiment of the invention;
Fig. 2 is according to the three-dimensional view of the LED chip unit of first embodiment of the invention;
Fig. 3 is according to the three-dimensional view of the LED chip unit of second embodiment of the invention;
Fig. 4 is according to the vertical view of the LED chip unit of third embodiment of the invention;
Fig. 5 is according to high pressure chip LED cell array schematic cross-section of the present invention;
Fig. 6 is the schematic cross-section on substrate according to high pressure chip LED cell array of the present invention upside-down mounting;
Fig. 7 to Figure 13 is according to the making schematic flow sheet of array upside-down mounting high pressure chip of the present invention;
Embodiment
Refer to shown in Fig. 1, a kind of upside-down mounting high-voltage LED of the present invention, comprising:
One substrate 10;
One N-shaped GaN layer 11, it is produced on substrate 10, and this N-shaped GaN layer 11 side above has table top 111;
One quantum well active area 12, its be produced on N-shaped GaN layer 11 do not have table top 111 above;
One p-type GaN layer 13, its be produced on quantum well active area 12 above;
One p electrode 14, its be produced on p-type GaN layer 13 above;
One p electrode pad 15, it is produced on the side away from table top 111 above p electrode 14;
One insulating barrier 16, its be produced on p electrode 14 above and a side of p electrode 14, p-type GaN layer 13, quantum well active area 12, and extend to the part surface of the table top 111 of N-shaped GaN layer 11, between one end of this insulating barrier 16 and p electrode pad 15, have a gap;
One n electrode pad 17, it is produced on the part upper surface of insulating barrier 16, and extends to another part surface of the table top 111 of N-shaped GaN layer 11.
Shown in Fig. 1, the invention provides a kind of manufacture method of upside-down mounting high-voltage LED, comprise following steps:
Step 1: prepare successively a N-shaped GaN layer 11, a quantum well active area 12, a p-type GaN layer 13 and a p electrode 14 on a substrate 10;
Step 2: etching under the side direction on p electrode 14, etching depth arrives in N-shaped GaN layer 11, makes a side of N-shaped GaN layer 11 form a table top 111;
Step 3: the side on p electrode 14 is prepared a p electrode pad 15;
Step 4: the opposite side on p electrode 14 is prepared an insulating barrier 16, and extend to the part surface of the table top 111 of N-shaped GaN layer 11;
Step 5: prepare a n electrode pad 17 on the part upper surface of insulating barrier 16, and extend to another part surface of the table top 111 of N-shaped GaN layer 11.
According to the LED chip unit first embodiment of the present invention (as shown in Figure 1) Suo Shu, in Sapphire Substrate 10, be followed successively by N-shaped GaN layer 11, quantum well active area 12 and p-type GaN layer 13, form the epitaxial structure of LED.Expose N-shaped GaN layer 11 by means parts such as etchings, form n type GaN exposed region 111.On p-type GaN layer 13, form high reflectance p electrode 14, this high reflectance p electrode 14 can be made up of the metal system that comprises high-reflectivity metal Ag or Al, for example Ni/Ag metal system, or the metal systems such as AlTiAu, it covers whole high reflectance p electrode 14 surfaces substantially, reflects and sends from Sapphire Substrate 10 1 sides with the light that active area 12 is sent.On high reflectance p electrode 14, expose the local insulating barrier 16 that forms near N-shaped GaN layer 11, this insulating barrier 16 extends to N-shaped GaN exposed region 111 surfaces from table top sidewall 120, for the high reflectance p electrode of below 14 and n electrode pad 17 electricity on it are isolated, and passivated mesa sidewall, avoid forming leak channel, and insulating barrier 16 is slightly larger than the part of n electrode pad above p-type GaN layer 13 at p-type GaN layer 13 upper section periphery, as depicted in figs. 1 and 2.P electrode pad 15 is positioned on high reflectance p electrode 14, n electrode pad 17 is formed on insulating barrier 16, described n electrode pad 17 is oppositely arranged above high reflectance p electrode 14 with p electrode pad 15, size in length L and width W direction is more than 30um, preferably more than 50um, the spacing d of the two is more than 10um, to guarantee that p/n electrode pad is in the time that upside-down mounting substrate is combined, existing enough reliable connection areas, again can the short circuit due to the technique such as Reflow Soldering and aligning; N electrode pad extends to N-shaped GaN layer 11 surface of exposure through table top sidewall 120 from p-type GaN layer 13 top, and form ohmic contact with N-shaped GaN11 in interface.
The etching process that forms table top can cause damage to table top sidewall 120, forms some defect levels, exposes p-type GaN layer 13 and N-shaped GaN layer 11 at table top sidewall 120 places simultaneously, isolates bad meeting and forms some leak channels.Therefore, when adopt shown in Fig. 2 the electrode structure of n electrode pad 17 being guided to p-type GaN layer 13 surface time, due to the whole table top sidewall 120 of n electrode pad 17 nearly cover, any one there is defect and pin hole in insulating barrier 16, capital causes the electric leakage of LED unit, makes the reliability variation of whole device.
The second embodiment of the present invention proposes for addressing the above problem.The structure of high-voltage LED unit is identical with embodiment 1, and difference is that the part of n electrode pad 17 on table top sidewall 120 only partly covers table top sidewall 120, as shown in Figure 3.N electrode pad 17 is divided into three parts: be positioned at the welding portion 171 of p-type GaN layer 13 top and be positioned at the coupling part 173 on table top sidewall 120, and N-shaped contact electrode 172, three parts that are positioned on N-shaped GaN layer 11 exposed region 111 (Fig. 1 illustrates) are electrically connected.Wherein coupling part 173 does not cover whole table top sidewall 120, for example, only cover below 4/5 of table top sidewall, or below 1/2, preferably below 1/8.The shape of coupling part 173 is preferably the bar shaped shown in Fig. 3, can be also 2 above bar shapeds that are scattered on table top sidewall; Can also be trapezoid, be less than the width near N-shaped GaN layer 11 near p-type GaN layer 13 surface width, trapezoid structure can reduce in electrode deposition process due to the coated occurrence probability opening circuit that causes in uneven thickness of step.The coupling part 173 of n electrode pad adopts the probability that does not cover whole table top sidewall 120 and can greatly reduce to occur electric leakage, improves the reliability of high pressure chip.
The third embodiment of the present invention as shown in Figure 4, the welding portion 271 that n electrode pad is positioned at p-type GaN layer 28 top can cover larger p-type GaN layer 28 upper surface, to meet the reliability requirement of eutectic welding or bonding, welding portion 271 can select to have with p electrode pad 25 the various figures of certain distance.N electrode pad also comprises the N-shaped contact electrode 272 on the N-shaped GaN layer 29 that is positioned at exposure, and connects the coupling part 273 of N-shaped contact electrode part 272 and welding portion 271.
In above-mentioned three embodiment, the coupling part 273,173 of n electrode pad can be made up of the metal level identical with N-shaped contact electrode 272,172 with welding portion 271,171, for example Cr/Pt/Au, the n such as Ni/Ag/Pt/Au or Ti/Al/TiAu electrode metal system forms, and also can be made up of Graphene, graphite film or the ITO material with good lateral thermal conductivity.
Preferably, below n electrode pad, form multilayer insulating film, for example, by SiO
2and SiN
xthe multilayer film of stacked composition, or formed by the relatively good oxide of thermal conductivity or nitride ceramics, for example, by Al
2o
3, the single or multiple lift film of AlN composition with electricity isolation p electrode pad and n electrode pad effectively, reduces the thermal resistance of active area to upside-down mounting supporting substrate 100 (as shown in Figure 6) simultaneously.
Fig. 5 arranges by multiple LED chip unit according to embodiment mono-, two and three the high-voltage LED chip forming, high-voltage LED chip comprises multiple LED chips unit 1,2,3, the quantity of LED chip unit according to when application required voltage specification determine, can be for example 6V (2 unit), 12V (4 unit), 24V (8 unit), 48V (16 unit) etc., or can be 15V (5 unit), 30V (10 unit), 60V (20 unit) etc.Between each LED chip unit, by isolated groove 50 (Fig. 6 illustrates) isolation, also can form high resistance area isolation by Implantation, preferably, this isolated groove by dry method or wet etching LED epitaxial loayer until Sapphire Substrate 10 form.
High-voltage LED chip is by eutectic weldering, bonding or conductive agent and 100 combinations of upside-down mounting supporting substrate, on upside-down mounting supporting substrate 100, form interconnection line, realize the serial or parallel connection between multiple LED chips unit 13, and be connected with the electrode on package support with 102 by the extraction electrode 101 being arranged on upside-down mounting supporting substrate 100.
The invention still further relates to a kind of manufacture method of high-voltage LED chip, as shown in Fig. 7 to 13, the method comprises the steps:
First, as shown in Figure 7, in Sapphire Substrate 10, form successively the epitaxial wafer that comprises N-shaped GaN layer 11, quantum well active area 12 and p-type GaN layer 13.Wherein the material of substrate is not limited to Sapphire Substrate, can also be GaN, AlN, Si, SiC, InP, GaAs and Ga
2o
3deng the substrate of material composition, can be also to comprise luminescent conversion material, as the transparent ceramic substrate of fluorescent material; The material of N-shaped layer, active area and p-type layer is not limited to GaN, can be binary, ternary and quaternary alloy that AlInGaN material system forms, as monocrystal materials such as AlN, AlGaN, InGaN, AlInGaN.
Voltage specification requirement according to actual needs, design is about to the quantity of the LED chip unit of interconnection.Fig. 8 only shows 3 unit, but the invention is not restricted to 3 unit.On epitaxial wafer, make mask, as the photoresist of post bake, silica or silicon nitride, or the combination mask of photoresist and silica and silicon nitride; , form isolated groove 50 epitaxial loayer is separated into multiple unit 1,2,3 to Sapphire Substrate 10 surfaces by epitaxial wafer described in dry method or wet etching.
Then, as shown in Figure 9, again form mask, each chip unit is carried out to etching and expose N-shaped GaN layer 11, form table top 110.The area of table top 110 can be less, and for example, isolation deep trouth 50 edges are that 10-50um is preferably 10-30um to the width of sidewall 120, can meet the ohmic contact requirement of N-shaped GaN layer 11.Like this, can greatly reduce the sacrifice of active area, improve the utilization ratio of epitaxial wafer.This step can with the etch step reversed order of above-mentioned isolation deep trouth 50, be that first etching forms mesa region 110, and the region of isolation deep trouth 50 is also etched into N-shaped GaN layer 11 in same step, and then further deep area of isolation and form isolation deep trouth 50, after putting upside down sequence of steps, can reduce total etch period, improve chip manufacturing efficiency.
As shown in figure 10, on p-type GaN layer, form high reflectance p electrode 14, this electrode can be transparent current extending in conjunction with distributed bragg reflector mirror (DBR), the DBR that for example ITO or Graphene form in conjunction with multilevel oxide or nitride film; Or the stacked high-reflectivity metal layer of transparent current extending, for example Al or Ag; Also can be directly the metal electrode system that contains Al or Ag, as NiAg or AlTiAu metal system.Then described high reflectance p electrode 14 can peel off graphical formation by evaporation metal film.
As shown in Figure 11 A, on whole chip, cover insulating barrier 16, this insulating barrier 16 can form by sputter or CVD mode, formed by insulating material such as silica, silicon nitride, aluminium nitride, aluminium oxide, zirconia, titanium nitrides, also can be these combinations of materials, can be also some organic insulating medium layer.The sidewall that described insulating barrier 16 can form etching on the one hand carry out passivation, the n electrode pad 17 (shown in Fig. 5) that can be used as on the one hand follow-up making in the time extending to p-type GaN layer 13 upper surface and high reflectance p electrode 14 insulate.Therefore, the compactness of this insulating barrier 16 should be enough high, to avoid forming some pin holes or leak channel, causes from n electrode pad 17 by leak channel and high reflectance p electrode 14 or 13 short circuit of p-type GaN layer.
For guaranteeing to insulate reliably, can form multilayer insulating film, as shown in Figure 11 B.First below the region that n electrode pad 17 covers on sidewall 120 and high reflectance p electrode 14, form the first insulating barrier 161, then forming as mentioned above large-area insulating barrier 16.In Figure 11 B, only showing dielectric layers, can be in fact multilayer as required.
Then, only to have insulating barrier 16 as example, insulating barrier 16 is carried out to photoetching, etch pattern, above p-type GaN layer 13, expose the subregion of high reflectance p electrode 14, and expose the subregion of table top 110.Again graphical with photoresist, then form p electrode pad 15 and n electrode pad 17 by one or many electrode deposition, described n electrode pad comprises three parts: be positioned at the welding portion 171 of high reflectance p electrode 14 tops, N-shaped ohmic contact part 172 and coupling part 173.Because n electrode pad extends to p-type GaN layer 13 top from N-shaped GaN layer 11 surface, above p-type GaN layer 13, form the welding portion 171 being connected with supporting substrate, therefore, compared with being only arranged on N-shaped GaN layer with traditional n electrode pad, do not need to sacrifice too much active region area and just can make face-down bonding part make to such an extent that area is larger, can improve soldering reliability; In addition, coupling part 173 can be smaller for the area coverage of sidewall, for example, be made into fillet shape or trapezoid, needn't cover whole sidewall 120 surfaces adjacent with table top 110.In the manufacturing process of insulating barrier 16, generally, the thickness of insulating layer on sidewall 120 surfaces is compared thinner with the table top 110 of level with p-type GaN layer 13 upper surface, therefore, the probability that electric leakage occurs sidewall is larger, and the area coverage that reduces coupling part 173 can effectively reduce the probability that electric leakage occurs at sidewall.Three parts of n electrode pad 17 can adopt identical metal electrode material system, and such as CrPtAu or AlTiAu etc. can save processing step; Also can adopt different materials, such as welding portion 171 adopts the weld metal systems such as AuSn, AgSn, Sn, CuSn, NiAu, PtAu, TiAu, and the mode of welding can be eutectic weldering, bonding etc.; N-shaped ohmic contact part 172 can adopt CrPtAu, TiAlTiAu, AlTiAu etc. can form with N-shaped GaN layer 11 metal system of ohmic contact; If coupling part 173 adopts the material identical with welding portion 171 or N-shaped ohmic contact part 172, also can adopt the graphite film material that heatsink transverse and electric conductivity are good, or Graphene, also can adopt the relatively low metal material of the cost such as Cu, Al, thereby reduce the material cost of whole chip.The upper surface of described welding portion 171 keeps flushing with the upper surface of p electrode pad 15 as far as possible substantially, or highly differ at weld metal within the scope of the linear deformation in welding process, to guarantee that welding portion 171 and p electrode pad 15 and the pad of supporting substrate 100 (Fig. 5 illustrates) weld together simultaneously reliably.
As shown in figure 13, on supporting substrate 100, form multiple interconnect pads 103.Supporting substrate can adopt insulated substrate, as ceramic insulation substrates such as AlN, also can adopt the electrically-conductive backing plate such as Cu, Al, or adopts the substrate of the semi-conducting material compositions such as Si, Ge, GaAs.In the time adopting electrically-conductive backing plate and semiconductor substrate, between interconnect pad 103 and supporting substrate 100, form insulating barrier, to prevent short circuit between interconnect pad 103.Described supporting substrate can also be pcb board or have the shell that wiring is connected with circuit.LED chip and supporting substrate 100 face-down bondings, the mode of welding can be eutectic weldering, bonding or other conductive adhesive modes.LED chip welds together with the interconnect pad 103 on supporting substrate 100 by the welding portion 171 of p electrode pad 15 and n electrode pad 17, forms the circuit structure of serial or parallel connection.Finally, by being electrically connected with interconnect pad 103 on supporting substrate 100 draw pad 101 and 102, and be connected external circuit from drawing the lead-in wire 106 that pad 101 draws with 102.
In addition, the space forming between LED chip and supporting substrate can be filled with insulating heat-conduction materials such as aluminium nitride, to improve the heat dispersion of whole upside-down mounting high-voltage LED.
The above; be only the embodiment in the present invention, but protection scope of the present invention is not limited to this, any people who is familiar with this technology is in the disclosed technical scope of the present invention; the conversion that can expect easily or replacement, all should be encompassed in of the present invention comprise scope within.Therefore, protection scope of the present invention should be as the criterion with the protection range of claims.
Claims (10)
1. a upside-down mounting high-voltage LED, comprises LED chip and supporting substrate; Described LED chip comprises multiple LED chips unit, and described each LED chip face-down bonding is on supporting substrate; Described each LED chip unit comprises N-shaped semiconductor layer, p-type semiconductor layer, active layer, p electrode pad and n electrode pad;
Three parts that wherein said n electrode pad comprises electrical interconnection:
Be positioned at the n contact electrode part of N-shaped semiconductor layer surface;
Be positioned at the coupling part on table top sidewall, described coupling part is cover part table top sidewall only, and by insulating barrier and the isolation of table top sidewall electricity;
With the welding portion that extends to p-type semiconductor layer top, described welding portion and p-type semiconductor layer and the isolation of p electrode pad electricity, described welding portion for supporting substrate on interconnect pad weld.
2. upside-down mounting high-voltage LED as claimed in claim 1, wherein LED chip unit also comprises the high reflectance p electrode being formed on p-type semiconductor layer, and described high reflectance p electrode covers p-type semiconductor layer upper surface, and isolates with n electrode pad electricity.
3. upside-down mounting high-voltage LED as claimed in claim 1, wherein coupling part is one or more bar shapeds or trapezoid conductive layer.
4. upside-down mounting high-voltage LED as claimed in claim 2, wherein the material of coupling part is metal, ito thin film, graphite film or grapheme material.
5. upside-down mounting high-voltage LED as claimed in claim 1, wherein there is multilayer dielectric layer coupling part and welding portion below, for isolating with table top sidewall and p-type semiconductor layer electricity.
6. upside-down mounting high-voltage LED as claimed in claim 4, wherein in multilayer dielectric layer, at least one deck is corresponding with coupling part and welding portion shape, but surrounding edge is greater than described coupling part and welding portion.
7. upside-down mounting high-voltage LED as claimed in claim 1, the wherein basic upper surface flush with described p electrode pad of welding portion upper surface.
8. upside-down mounting high-voltage LED as claimed in claim 1, wherein the mode of face-down bonding comprises eutectic weldering, bonding or conductive adhesive.
9. a manufacture method for upside-down mounting high-voltage LED, comprises following steps:
On the epitaxial wafer that comprises N-shaped semiconductor layer, p-type semiconductor layer and active layer, form table top, expose N-shaped semiconductor layer;
On p-type semiconductor layer, form high reflectance p electrode;
Form insulating barrier at high reflectance p electrode surface and table top sidewall;
Patterned insulator layer is also made p electrode pad, and described p electrode pad is electrically connected with high reflectance p electrode;
Form n electrode pad, three parts that described n electrode pad comprises electrical interconnection:
Be positioned at the n contact electrode part of N-shaped semiconductor layer surface;
Be positioned at the coupling part on table top sidewall, described coupling part is cover part table top sidewall only;
With the welding portion that extends to p-type semiconductor layer top, described welding portion and high reflectance p electrode and the isolation of p electrode pad electricity;
By described welding portion 171, LED chip and supporting substrate are welded.
10. the manufacture method of upside-down mounting high-voltage LED as claimed in claim 9, wherein coupling part is formed as one or more bar shapeds or trapezoid.
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