CN106941353A - A kind of time-domain signal optimization Simulation system - Google Patents
A kind of time-domain signal optimization Simulation system Download PDFInfo
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- H—ELECTRICITY
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
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Abstract
The invention discloses a kind of time-domain signal optimization Simulation system, the time-domain signal optimization Simulation system includes central controller, time constant generator, frequency division module, detector amplefier, integrator, simulation excitation source generator, frequency stabilization tester, strategy controller and frequency multiplier；The frequency division module, detector amplefier, integrator are sequentially connected in series；The integrator is connected with the central controller；The central controller is connected with the frequency multiplier, simulation excitation source generator, strategy controller and frequency stabilization tester respectively；The strategy controller is connected with the detector amplefier, and is sequentially connected in series with the time constant generator, detector amplefier；The time constant generator is connected with the integrator；The frequency multiplier is connected with the frequency division module, simulation excitation source generator respectively；The simulation excitation source generator is connected with the frequency stabilization tester.
Description
Technical field
The present invention relates to field of circuit technology, more particularly to a kind of time-domain signal optimization Simulation system.
Background technology
With science and technology continuous improvement, people are to analogue system more and more higher.Analogue system calculates essence in the prior art
Degree is relatively low, when being emulated to complication system, realize that difficulty is big on circuit, precision is difficult guarantee.
The content of the invention
The present invention provides a kind of time-domain signal optimization Simulation system, solves above-mentioned technical problem, has reached analogue system
Computational accuracy is higher, when being emulated to complication system, realizes that difficulty is imitated on circuit, the technique effect that precision is easily guaranteed that.
The present invention provides a kind of time-domain signal optimization Simulation system, and the time-domain signal optimization Simulation system includes center and controlled
Device processed, time constant generator, frequency division module, detector amplefier, integrator, simulation excitation source generator, frequency stabilization tester, plan
Omit controller and frequency multiplier；The frequency division module, detector amplefier, integrator are sequentially connected in series；The integrator with it is described
Central controller is connected；The central controller respectively with the frequency multiplier, simulation excitation source generator, strategy controller and frequency
Stabilization tester is connected；The strategy controller is connected with the detector amplefier, and is put with the time constant generator, detection
Big device is sequentially connected in series；The time constant generator is connected with the integrator；The frequency multiplier respectively with the frequency dividing
Module, the connection of simulation excitation source generator；The simulation excitation source generator is connected with the frequency stabilization tester.
It is preferred that, the frequency division module receives the original frequency F of the high steady reference source0；The steady reference source of height received
Original frequency F0High steady reference source crossover frequency F is obtained after the frequency division module scaling down processingREF。
It is preferred that, the time constant generator module is made up of the multistage connection in series-parallel loop of resistance and condenser type.
It is preferred that, when the multiplication factor A of the integrator is infinity, the transmission function of the integrator is 1/STi；
Wherein, S is complex Fourier frequency S=j ω=j2 π f, A and TiThe respectively multiplication factor and time constant of integrator.
It is preferred that, analogue system open-loop gain is：
Wherein, G0=KDETKOSCM；
S is complex Fourier frequency S=j ω=j2 π f；
TiFor time constant；
ThFor the RC time constants of equivalent RC wave filters；
M is the Clock Multiplier Factor of frequency multiplier；
KDETFrequency slope is examined for detector amplefier；
KOSCFor the voltage-controlled slope of simulation excitation generator.
It is preferred that,
It is preferred that, the initialization simulation excitation generator output 10MHz frequency signals that the central controller is set.
It is preferred that, the initialization simulation excitation generator output 10MHz frequency signals that the central controller is set.
It is preferred that, initialization frequency multiplier output signal frequency and F that central controller is setREFTheoretical value is identical, is
50.1234MHz。
It is preferred that, simulation excitation generator output signal frequency has linkage to correlate with frequency multiplier output signal frequency.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, embodiment will be described below
Needed for the accompanying drawing to be used be briefly described, it should be apparent that, drawings in the following description be only the present invention some
Embodiment.
Fig. 1 is a kind of schematic diagram of time-domain signal optimization Simulation system of the application better embodiment；
Fig. 2 is the schematic diagram of an implementation model in the application Fig. 1；
Fig. 3 is that judgement is the square wave that has fixed frequency and phase relation with signal, synchronous reference signal, keying FM signal
Digital signaling diagram；
Fig. 4 is the application analogue system strategy anticipation tendency chart.
Embodiment
In order to be better understood from above-mentioned technical proposal, below in conjunction with Figure of description and specific embodiment to upper
Technical scheme is stated to be described in detail.
Fig. 1 is a kind of schematic diagram of time-domain signal optimization Simulation system of the application better embodiment, referring to Fig. 1, this
Application provides a kind of time-domain signal optimization Simulation system, and the time-domain signal optimization Simulation system includes central controller, time
Constant generator, frequency division module, detector amplefier, integrator, simulation excitation source generator, frequency stabilization tester, strategy controller
And frequency multiplier；
The frequency division module, detector amplefier, integrator are sequentially connected in series；The integrator and the central controller
Connection；The central controller connects with the frequency multiplier, simulation excitation source generator, strategy controller and frequency stabilization tester respectively
Connect；The strategy controller is connected with the detector amplefier, and is gone here and there successively with the time constant generator, detector amplefier
Connection connection；The time constant generator is connected with the integrator；The frequency multiplier swashs with the frequency division module, emulation respectively
Encourage source generator connection；The simulation excitation source generator is connected with the frequency stabilization tester.
The frequency division module receives the original frequency F of the high steady reference source0；The original frequency of the steady reference source of height received
Rate F0High steady reference source crossover frequency F is obtained after the frequency division module scaling down processingREF。
F0 is the high surely original frequency of reference source, F in Fig. 1REF, FOUTRespectively high steady reference source crossover frequency swashs with emulation
Encourage generator output frequency.εREF, εDET, εINT, εOSC, εMULRespectively high steady reference source, detector amplefier, integrator, emulation swash
Encourage the error of generator and frequency multiplier output end.M is Clock Multiplier Factor, KDETFor detector amplefier discrimination gradient, KOSCSwash for emulation
Encourage the voltage-controlled slope of generator.1/(1+STh) be equivalent RC wave filters loop transfer function, wherein S be complex Fourier frequently
Rate S=j ω=j2 π f, Th is RC time constants.A and Ti are respectively the multiplication factor and time constant of integrator, herein, are
Fig. 1 emulation is realized, we add time constant generator module, it is by resistance and the multistage connection in series-parallel loop structure of condenser type
Into, the RC time constant different to produce, and applied to the T of detector amplefier in Fig. 1hAnd the T of integratori。
In Fig. 1 integrator, to simplify simulation scenarios, it is infinity to set the multiplication factor A of integrator, when A is very big
When can approximately recognize integrator transmission function be 1/STi.Definition：
G0=KDETKOSCM (1)
Then Fig. 1 analogue system open-loop gain is：
The stable state output frequency of simulation excitation source generator is represented by：
System generally has G (s) after loop work reaches stable state》1, thus (3) formula can be written for：
From (4) formula, the stable state output frequency of simulation excitation source generator should be equal to high stable ginseng in the ideal situation
Examining frequency values after the frequency dividing of source has a multiple proportion：
When the multiplication factor A of the integrator is infinity, the transmission function of the integrator is 1/STi；Wherein, S
For complex Fourier frequency S=j ω=j2 π f, A and TiThe respectively multiplication factor and time constant of integrator.
Analogue system open-loop gain is：
Wherein, G0=KDETKOSCM；
S is complex Fourier frequency S=j ω=j2 π f；
TiFor time constant；
ThFor the RC time constants of equivalent RC wave filters；
M is the Clock Multiplier Factor of frequency multiplier；
KDETFrequency slope is examined for detector amplefier；
KOSCFor the voltage-controlled slope of simulation excitation generator.
The time constant generator module is made up of the multistage connection in series-parallel loop of resistance and condenser type.
The initialization simulation excitation generator output 10MHz frequency signals that the central controller is set.
The initialization simulation excitation generator output 10MHz frequency signals that the central controller is set.
Initialization frequency multiplier output signal frequency and F that central controller is setREFTheoretical value is identical, is 50.1234MHz.
Simulation excitation generator output signal frequency has linkage to correlate with frequency multiplier output signal frequency.
The stable state output frequency of the simulation excitation source generator of theoretical expression should refer to source frequency with high stable in formula (5)
Multiple proportion between value, and above-mentioned relation is a dynamic equilibrium.
The setting of formula (5) and above-mentioned X parameter is theoretical, because in the PLL phase-locked loops that actual Fig. 1 is constituted,
Because the error of each several part in the frequency difference and PLL loops of high steady reference source itself is present, Fig. 1 output frequency and its nominal value are total
There is certain deviation.The deviation and aging at simulation excitation generator end, integrator null offset, frequency multiplier phase place change etc. all may
Produce this deviation.All ε long term drifts are all likely to result in the aging phenomenon of output frequency, as additional noise.
Should try one's best to reduce the error of above-mentioned electronic circuitry part and improve open-loop gain G (s).For the sake of convenient simulation, I
The unified ε by Fig. 1 in the patentREF, εDET, εINT, εOSC, εMULEvery error is set to fixed value.To improve Fig. 1 emulation
The performance of system, should make open-loop gain G (s) become big as far as possible, make the molecule G in formula (2) theoretically0=KDETKOSCM becomes
Greatly, but actually G0 should have the limit.It is generally acknowledged that the damped coefficient of system is no less than 0.5, then
For the sake of so facilitating, we set G0=1, while making Th=Ti.The method of realization is：
(1) detector amplefier, simulation excitation generator, frequency multiplier, are set by the central controller in Fig. 1 respectively
KDET、KOSC, M, make G0=KDETKOSCM is equal to 1；
(2) the corresponding time constant Th=of detector amplefier, integrator, is set by the central controller in Fig. 1 respectively
Ti。
After above-mentioned setting, the open-loop gain of Fig. 1 analogue systems of formula (2) statement is：
Reduce time constant Th, increase the open-loop gain of analogue system really according to formula (7), this is advantageous for systematicness
Can, this also increases loop filter bandwidth fh simultaneously.Fig. 1 equivalent to one frequency discriminator of high steady reference source, when its long term drift
When can ignore, it is assumed that its power-law noise formula is：
Sy(f)REF=h0+h-1f-1 (8)
Fig. 1 loop works under theoretical case are in linear condition, if it is considered that simulation excitation generator and high steady reference
Source power spectrum density (Sy (f) OSC and Sy (f) REF) is completely uncorrelated, then Fig. 1 system output powers spectrum density can be expressed as：
According to definition, we have STh=jf/fh, therefore, (8) formula substitute into (9) formula it is seen thatWhen emulation average period very in short-term, (f/fh) ＞ ＞ 1, have
(the f/f when the average period of emulation is extremely longh) ＜ ＜ 1, have
Obviously, whole loop is a high-pass filter for simulation excitation generator；To with for high steady reference source
It is a low pass filter；Its filtering characteristic by loop filter high end cut-off frequencies fhDetermine.Formula (10) formula it is extreme
Situation is Sy(f)0=Sy(f)OSC, the extreme case of (11) formula is Sy(f)0=Sy(f)REF.As can be seen that fh, which crosses senior general, makes Fig. 1
Analogue system output signal short-term stability be deteriorated；Fh is too small will to become Fig. 1 analogue system output signal long-term stability
Difference.After Fig. 1 system closed loops, we are can not to learn the loop bandwidth i.e. high end cut-off frequencies fh of system, we with Q values come
The stabilization signal of the analogue system output signal of phenogram 1, and measured by the frequency stabilization tester in Fig. 1 and draw sign system
The simulation results of Q values, so that indirect reaction loop bandwidth is high end cut-off frequencies fh value selection quality.
On multiple proportion strategy
According to Fig. 1 systems, the frequency range that our Simulation Model is pre-seted is as follows, the circuit of implementation model
Figure, refers to Fig. 2：
(1) it is to realize the simulated response of high band, the steady reference source of the height that we select frequency higher, at the frequency dividing through Fig. 1
The signal frequency obtained after reason is 50.****MHz.The * * * * (remaining into four) of wherein decimal place are random, are said for convenience
For the sake of bright, the F in Fig. 1REFFor 50.1234MHz；
(2) the initialization simulation excitation generator output 10MHz frequency signals that central controller is set；
(3) the initialization frequency multiplier output signal frequency and F that central controller is setREFTheoretical value is identical, i.e., be also
50.1234MHz；
(4) simulation excitation generator output signal frequency has linkage to correlate with frequency multiplier output signal frequency.
Wherein, wherein processor is located in the central controller module in Fig. 1 in Fig. 2, and processor XTAL ends and Fig. 2
In DDS1, DDS2 RefClk terminate frequency signal into same clock source, from synchronization during ensureing.
On the basis of clock reference of the processor when outside input end of clock (XTAL) is as work, three tunnel phases are produced respectively
The position adjustable square-wave signal of relation, wherein keying FM signal delivers to DDS1 FSK keying frequency modulation input port realization all the way
Frequency modulation, all the way synchronous reference signal are used as synchronous phase demodulation, all the way judgement lock-in detection of the signal as Fig. 1 phaselocked loops.
On the basis of reference clocks of the DDS1 when outside clock reference input (RefClk) is as work, pass through processor
Serial sequential communication between DDS1, the high and low electricity for the square wave keying frequency modulation square-wave signal that DDS1 is sent according to FSK ends processor
Level state chooses the multiple-frequency modulation data presetting frequency conduct that processor is inputted in internal frequency control register (F1, F0) respectively
Output, so as to produce the frequency signal 50.1234MHz ± △ f outputs with modulation.Preset frequency-splitting △ f are by two frequencies
Numerical value in control register F1, F0 determines, it is 50.1234MHz (the 4th essence after decimal point specifically to consider radiofrequency signal
It is close), we take △ f=100Hz.
It is similar with the principle that above-mentioned processor controls DDS1 generation multiple-frequency modulation signals, when processor is by serial communication
Sequence, DDS2 is passed to by same frequency dividing numerical value, and the 50.1234MHz frequency signals produced without modulation are exported.DDS2 is obtained
50.1234MHz frequency signals send into DDS3 external clock benchmark input end (RefClk), reference when being worked as DDS3
Clock.Processor is communicated according to serial sequential, and output frequency (10MHz) numerical value will be initialized accordingly and passes to DDS3, so that
Obtain the output of simulation excitation source generator frequency signal.
Due to DDS3 external reference when base use the frequency-doubled signal that DDS2 is produced, therefore in this programme, when closing in Fig. 1
Central controller in cyclization road is obtained after corresponding phase discrimination signal information, can change corresponding DDS2 multiple-frequency modulation signal
Frequency, so can also cause the frequency of DDS3 output signals to change, that is, instead of traditional side by D/A VCXOs
Formula changes the output frequency value of local oscillator, and then changes the method for system output frequency.It is worth noting that, for output frequency
Signal employs the mode of direct digital synthesizers so that a higher synthesizer of stability is act as in certain application
Role.User can be in practical application requirement, pass through user input port in Fig. 2, easily change DDS3 whole machine
The frequency values of output signal.
On time constant Provisioning Policy
From aforementioned schemes, we set G0=KDETKOSCM is equal to 1, while making Th=Ti.According to above-mentioned multiple proportion
Strategy, the signal frequency that we export simulation excitation source generator is that the frequency selection after 10MHz, high steady reference source frequency dividing is
50.1234MHz, according to formula (5)M=5 can be obtained.From above-mentioned multiple proportion strategy, Wo Men
System output frequency value side is not changed by the way of traditional VCXO by D/A in the analogue system of design drawing 1
Method, so the K in Fig. 1OSCThe voltage-controlled slope of simulation excitation generator can not know that we can only pass through G0=KDETKOSCM
K is obtained equal to 1 and by M=5DET*KOSC=1/5 conclusion.In specific implementation process, according to Fig. 1, we can only be in
Controller is entreated to carry out K to detector amplefierDETThe setting of value.Because the time constant in analogue system is only determined by Th, so pressing
According to Fig. 1 we by central controller to the control realization of time constant generator to detector amplefier, the detection of integrator when
Between constant Th and integration time constant Ti setting, and make Th=Ti。
On analogue system Q values strategy
Three road square-wave signals are produced by processor in fig. 2：Synchronous reference signal, keying FM signal, judgement letter
Number, synchronous reference signal frequency is equal to keying FM signal frequency, and have certain phase delay poor；Simultaneously believe judgement
Number N times of synchronous reference signal frequency of frequency or keying FM signal frequency, and have certain phase delay poor.Here it is specific
We to take synchronous reference signal frequency to be equal to keying FM signal frequency be 79Hz, and both phase differences are 100 degree；Take simultaneously
Judge with signal frequency N values for 4 times, and be 40 degree with synchronous reference signal phase difference.
Specific judgment basis is as shown in Figure 3；Judgement is to have with signal, synchronous reference signal, keying FM signal in Fig. 3
The square wave data signal of fixed frequency and phase relation；Enabling signal is either 1 or is 0, therefore be can be regarded as without fixed frequency
The square wave data signal of rate；Phase discrimination signal is produced by the integrator in Fig. 1, and it is the direct current signal of a change, therefore can see
Work is the analog signal of no fixed frequency.
According to Fig. 3 principle combination Fig. 1, a certain rising edge that we set judgement signal starts as triggering judgement,
10 judgements are completed before the arrival of next rising edge, when then next rising edge arrives, next group of 10 judgement is triggered again.By
Know the frequency of judgement signal in Fig. 3 in advance in us, i.e., it is understood that time T between two neighboring rising edge, therefore can
With the time interval of 10 judgements of mean allocation one group.
Central controller is judged the phase discrimination signal conveyed by integrator according to above-mentioned triggering Rule of judgment in Fig. 1,
When its analog DC signal magnitude is located in the non-enable banded regions shown in Fig. 3, central controller exports the enable letter in Fig. 3
Number be 0, Fig. 1 in the steady measuring instrument of frequency do not work；When its analog DC signal magnitude is located at outside the non-enable banded regions shown in Fig. 3
When, the enable signal that central controller exports in Fig. 3 is that the steady measuring instrument of frequency in 1, Fig. 1 is started working；Emulate Q values actually
It is the simulation results value exported when the steady measuring instrument of Fig. 1 intermediate frequencies works, it reflects the property of Fig. 1 analogue system output signals
Can,
During whole emulation, central controller initializes all desire arranges values, these parameters are just when starting
No longer change, there was only detector amplefier parameter K during dynamic simulationDETValue, detector amplefier time constant Th values must be by center controls
Device module processed enters Mobile state setting, and it is then emulation Q values to judge the whether rational criterion of the two parameters.We give KDET
Value takes scope a 1-10, same Th, and we also take a 1-10.When Fig. 1 systems are emulated at the beginning, except setting each road initialization
Outside arranges value, we can be in KDETValue and Th values gamut emulate one time and obtain corresponding Q values, and Q values are located between L and H, definition
For L=1 to H=10 (Q values are the bigger the better), the Q Value Datas that we are defined in this section of simulation time are " modeling area ", such as Fig. 4 institutes
Show, the modeling figure in Fig. 4, central controller sets KDETPhase demodulation letter in value and Th values, and synchronous recording Q values and Fig. 1 and Fig. 3
Number value J, and make setting KDETValue and Th values change in the opposite direction.After the completion of modeling, certain point S location starts emulation.When
It is triggering following strategy when emulation Q values are H1 (H1=0.8H) that Q values, which reach P points,：
Now central processing unit makes setting KDETValue is identical with the change direction of Th values, and sets K next timeDETValue (note
For K2) compared with this KDETValue (being designated as K1) is increased (i.e. K2>K1)；Th values (being designated as T2) are set next time then compared with this Th value
(being designated as T1) is increased (i.e. T2>T1)；Q values and phase discrimination signal value J are recorded simultaneously.Until according to " the tactful anticipation shown in Fig. 4
Line ", when Q values reach H, central processing unit judges the moment of this in Fig. 4 phase discrimination signal value J critical value and all phase demodulations before
Signal adds accumulated value J1 relation, and (J1 values here are from S points to all each emulation of critical value point previous moment in Fig. 4
The phase discrimination signal value sum that central processing unit is obtained), work as J>During 2*J1, it is believed that effectively, center is handled this simulation result
Device recalls the K that P points are set in Fig. 4DETValue and Th values are used as optimal value.
It should be noted last that, above embodiment is merely illustrative of the technical solution of the present invention and unrestricted,
Although the present invention is described in detail with reference to example, it will be understood by those within the art that, can be to the present invention
Technical scheme modify or equivalent, without departing from the spirit and scope of technical solution of the present invention, it all should cover
Among scope of the presently claimed invention.
Claims (10)
1. a kind of time-domain signal optimization Simulation system, it is characterised in that the time-domain signal optimization Simulation system includes center and controlled
Device processed, time constant generator, frequency division module, detector amplefier, integrator, simulation excitation source generator, frequency stabilization tester, plan
Omit controller and frequency multiplier；
The frequency division module, detector amplefier, integrator are sequentially connected in series；The integrator connects with the central controller
Connect；
The central controller connects with the frequency multiplier, simulation excitation source generator, strategy controller and frequency stabilization tester respectively
Connect；
The strategy controller is connected with the detector amplefier, and with the time constant generator, detector amplefier successively
It is connected in series；The time constant generator is connected with the integrator；
The frequency multiplier is connected with the frequency division module, simulation excitation source generator respectively；The simulation excitation source generator with
The frequency stabilization tester connection.
2. time-domain signal optimization Simulation system as claimed in claim 1, it is characterised in that the frequency division module receives the height
The original frequency F of steady reference source0；The original frequency F of the steady reference source of height received0After the frequency division module scaling down processing
Obtain high steady reference source crossover frequency FREF。
3. time-domain signal optimization Simulation system as claimed in claim 2, it is characterised in that the time constant generator module
It is made up of the multistage connection in series-parallel loop of resistance and condenser type.
4. time-domain signal optimization Simulation system as claimed in claim 2, it is characterised in that when the multiplication factor of the integrator
When A is infinity, the transmission function of the integrator is 1/STi；Wherein, S is complex Fourier frequency S=j ω=j2 π f, A
And TiThe respectively multiplication factor and time constant of integrator.
5. time-domain signal optimization Simulation system as claimed in claim 4, it is characterised in that analogue system open-loop gain is：
Wherein, G0=KDETKOSCM；
S is complex Fourier frequency S=j ω=j2 π f；
TiFor time constant；
ThFor the RC time constants of equivalent RC wave filters；
M is the Clock Multiplier Factor of frequency multiplier；
KDETFrequency slope is examined for detector amplefier；
KOSCFor the voltage-controlled slope of simulation excitation generator.
6. time-domain signal optimization Simulation system as claimed in claim 5, it is characterised in that
7. time-domain signal optimization Simulation system as claimed in claim 5, it is characterised in that it is first that the central controller is set
Beginningization simulation excitation generator exports 10MHz frequency signals.
8. time-domain signal optimization Simulation system as claimed in claim 5, it is characterised in that it is first that the central controller is set
Beginningization simulation excitation generator exports 10MHz frequency signals.
9. time-domain signal optimization Simulation system as claimed in claim 5, it is characterised in that the initialization that central controller is set
Frequency multiplier output signal frequency and FREFTheoretical value is identical, is 50.1234MHz.
10. time-domain signal optimization Simulation system as claimed in claim 5, it is characterised in that simulation excitation generator output letter
Number frequency has linkage to correlate with frequency multiplier output signal frequency.
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