CN208797006U - A kind of terminal for semiconductor power device - Google Patents
A kind of terminal for semiconductor power device Download PDFInfo
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- CN208797006U CN208797006U CN201821240990.6U CN201821240990U CN208797006U CN 208797006 U CN208797006 U CN 208797006U CN 201821240990 U CN201821240990 U CN 201821240990U CN 208797006 U CN208797006 U CN 208797006U
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- field plate
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- Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract
The utility model provides a kind of terminal for semiconductor power device, the terminal for being used for semiconductor power device includes: collector, base area, multiple field limiting rings and multiple field plate groups corresponding with the field limiting ring, the field plate group includes the first polysilicon field plate and Metal field plate being electrically connected with each other, first polysilicon field plate, the Metal field plate are sequentially located at the top of the field limiting ring, first polysilicon field plate and the Metal field plate are electrically connected with the field limiting ring, and the Metal field plate covers first polysilicon field plate.The terminal for semiconductor power device of the utility model can be improved breakdown voltage and reduce the spike electric field at field plate edge.
Description
Technical field
The utility model relates to technical field of semiconductor device, more particularly to a kind of end for semiconductor power device
End.
Background technique
For the terminal (Insulated Gate Bipolar Transistor, IGBT) of semiconductor power device, be by
The compound full-control type voltage driven type power semiconductor of BJT (double pole triode) and MOS (insulating gate type field effect tube) composition
Device, it has the advantages that unipolar device and bipolar devices simultaneously, for example, driving circuit is simple, control circuit power consumption and at
This is low, on-state voltage drop is low, becomes one of semiconductor devices power of current mainstream.
In IGBT manufacturing process, multiple oxidation process, mainly thermal oxide, so that being inevitably present in oxide layer
Some positive charges.PN junction intermediate approximation is in planar junction, and in edge, such as near the interface of silicon and silica, by
Positive charge can attract electronics to cause the concentration on silicon face N-type region surface to increase in silicon face concentration in oxide layer, this will be in silicon
The vertical electric field that silicon substrate is directed toward by oxide layer is formed at the near surface of substrate, depletion layer electric field at the electric field and surface
Closing electric field will gather at the silicon face on the outside of PN junction, and then depletion layer is caused to narrow at surface compared to inside, electric-field strength
Degree is higher than in vivo, breakdown is easy to happen, so that the breakdown voltage of device and diffusion junctions phase in ideal plane existing for no interface charge
Than can decrease.
On the other hand, the IGBT device in practical application, chip surface usually cover for encapsulation insulating layer or
Epoxy resin.When IGBT bears big voltage, peak electric field is formed in vivo, the insulating layer or epoxy resin layer of surface covering
Polarization can be generated, and the produced charge that polarizes can inhibit the depletion layer of surface of silicon to extend, and peak surface electric field is caused to increase.
When peak electric field reaches breakdown point, it will lead to the variation or degeneration of pressure resistance, also result in IGBT and lose in some environments
Effect.
However, existing terminal structure includes electric field limitation ring (FLR), field plate techniques, knot extended surface etc., these structures
Actually play the role of outward broadening main knot depletion region, finally improves breakdown voltage.Wherein field plate structure is because it can be with
It is realized using common process, terminal area is small, the advantages that being not very sensitive to interface charge, it is widely used, but the structure
Potential difference between midfield plate edge and silicon is very big, causes to be easy to puncture in the outer edge of field plate.
Therefore, it is necessary to a kind of terminal for semiconductor power device be provided, to solve to ask present in the prior art
Topic.
Utility model content
The purpose of this utility model is to provide a kind of terminals for semiconductor power device, can be improved breakdown voltage
And reduce the spike electric field at field plate edge.
In order to solve the above technical problems, the utility model provides a kind of terminal for semiconductor power device comprising:
Collector, base area, multiple field limiting rings and multiple field plate groups corresponding with the field limiting ring, the field plate group include
The first polysilicon field plate and Metal field plate being electrically connected with each other, first polysilicon field plate, the Metal field plate successively position
In the top of the field limiting ring, first polysilicon field plate and the Metal field plate are electrically connected with the field limiting ring, institute
It states Metal field plate and covers first polysilicon field plate；
The length of the Metal field plate is greater than the length of first polysilicon field plate.
In the terminal for semiconductor power device of the utility model, the terminal for semiconductor power device
It further include the second polysilicon field plate, second polysilicon field plate is between the field limiting ring and the Metal field plate, and institute
It states Metal field plate and only partially covers second polysilicon field plate.
In the terminal for semiconductor power device of the utility model, second polysilicon field plate and described first
Polysilicon field plate is located on the same floor, and setting is spaced between second polysilicon field plate and first polysilicon field plate.
In the terminal for semiconductor power device of the utility model, the first part part of the Metal field plate is covered
Second polysilicon field plate is covered, and the first part of the Metal field plate is in the Metal field plate far from the Metal field plate
With the part of the junction of the field limiting ring.
In the terminal for semiconductor power device of the utility model, the Metal field plate covers second polycrystalline
The half of silicon field plate.
In the terminal for semiconductor power device of the utility model, first polysilicon field plate and field limit
It is provided with field oxide between ring, the first via hole is provided on the field oxide, first polysilicon field plate passes through described
First via hole and the field limiting ring are electrically connected.
In the terminal for semiconductor power device of the utility model, first polysilicon field plate and the metal
Between field plate and the Metal field plate and the field limiting ring that is not covered by first polysilicon field plate and the field oxide it
Between be provided with dielectric layer, be provided with the second via hole on the dielectric layer, the Metal field plate passes through second via hole and institute
State field limiting ring electric connection.
In the terminal for semiconductor power device of the utility model, third mistake is additionally provided on the dielectric layer
Hole, first polysilicon field plate are electrically connected by the third via hole and the Metal field plate.
In the terminal for semiconductor power device of the utility model, second via hole and described first crosses hole location
In the same side of the field limiting ring.
The terminal for semiconductor power device of the utility model, by using the field of polysilicon field plate and Metal field plate
Board group, and Metal field plate is electrically connected with field limiting ring and polysilicon field plate respectively, so that winner is tied depletion region and is effectively broadened outward, from
And it improves breakdown voltage and reduces the spike electric field at field plate edge.
Detailed description of the invention
Fig. 1 is the structural schematic diagram for being currently used for the terminal of semiconductor power device；
Fig. 2 is the structural schematic diagram of the terminal for semiconductor power device of the utility model.
Specific embodiment
The explanation of following embodiment is to can be used to the specific of implementation to illustrate the utility model with reference to additional schema
Embodiment.The direction term that the utility model is previously mentioned, for example, "upper", "lower", "front", "rear", "left", "right", "inner", "
Outside ", " side " etc. is only the direction with reference to annexed drawings.Therefore, the direction term used is to illustrate and understand that this is practical
It is novel, rather than to limit the utility model.The similar unit of structure is to be given the same reference numerals in the figure.
As shown in Figure 1, the existing terminal for semiconductor power device include collector 11, base area 12 (namely lining
Bottom), multiple field limiting rings 13, dielectric layer 14 and field plate 15 between field limiting ring 13 and field plate 15, the field limiting ring 13 are set
Including what is formed by two kinds of doped regions that conduction type is identical but doping concentration is different, which is P+ type.
Referring to figure 2., Fig. 2 is the structural schematic diagram of the terminal for semiconductor power device of the utility model.
As shown in Fig. 2, the terminal for semiconductor power device of the utility model include collector 11, it is base area 12, more
A field limiting ring 13 and multiple field plate groups corresponding with the field limiting ring 13, the field plate group includes first be electrically connected with each other
Polysilicon field plate 22 and Metal field plate 24, the collector 11 are the p semiconductor of the second conduction type, and base area 12 is led for first
The N semiconductor of electric type.The field limiting ring 13 includes by two kinds of doped region shapes that conduction type is identical but doping concentration is different
At, which is P+ type.
First polysilicon field plate 22, the Metal field plate 24 are sequentially located at the top of the field limiting ring 13, Ye Jisuo
The top that the first polysilicon field plate 22 is located at the field limiting ring 13 is stated, the Metal field plate 24 is located at first polysilicon field plate
22 top.First polysilicon field plate 22 and the Metal field plate 24 are electrically connected with the field limiting ring 13, the gold
Belong to field plate 24 and covers first polysilicon field plate 22.In one embodiment, the Metal field plate 24 is completely covered described
One polysilicon field plate 22.The Metal field plate 24 constitutes step-like field plate group with first polysilicon field plate 22.
Wherein the length of the Metal field plate 24 is greater than the length of first polysilicon field plate 22.Due to Metal field plate 24
Length to be longer than the length of the first polysilicon field plate 22 so that the two forms the structure of step field plate, winner is made to tie consumption
Area to the greatest extent effectively broadens outward, further increases breakdown voltage.
Wherein, field oxide 21, the field oxygen are provided between first polysilicon field plate 22 and the field limiting ring 12
Change and be provided with the first via hole 201 on layer 21, first polysilicon field plate 22 is limited by first via hole 201 with the field
Ring 13 is electrically connected.
Wherein, between first polysilicon field plate 22 and the Metal field plate 24 and the Metal field plate 24 with not by
Dielectric layer 25, the medium are provided between the field limiting ring 12 that first polysilicon field plate 22 and the oxide layer 21 cover
The second via hole 202 is provided on layer 25, the Metal field plate 24 is electrical by second via hole 202 and the field limiting ring 13
Connection.In one embodiment, second via hole 202 and first via hole 201 are located at the same side of the field limiting ring 13.
Wherein, it is additionally provided with third via hole 203 on the dielectric layer 25, first polysilicon field plate 22 passes through described the
Three via holes 203 are electrically connected with the Metal field plate 24.In one embodiment, the thickness of the dielectric layer 25 is greater than the field
The thickness of oxide layer 21, so that the depth of second via hole 202 is greater than the depth of first via hole 201.
In another embodiment, the terminal for semiconductor power device further includes the second polysilicon field plate 23, institute
The second polysilicon field plate 23 is stated between the field limiting ring 13 and the Metal field plate 24, and the only portion of the Metal field plate 24
Divide covering second polysilicon field plate 23.Second polysilicon field plate 23 is not electric with field limiting ring 13 and Metal field plate 24
Property connection.Field oxide 21 is also located between the second polysilicon field plate 23 and the field limiting ring 13.Dielectric layer 25 is also located at second
Between polysilicon field plate 23 and the Metal field plate 24.Due to the presence of the second polysilicon field plate, when IGBT bears pressure resistance,
The area N- is high potential, and it is also low potential that P+ field limiting ring area, which is low potential, Metal field plate 24 and 13 equipotential of field limiting ring,.So that one
Some electrical power line is from the area N to the second polysilicon field plate 23 and another part power line from the second polysilicon field plate 23 to metal
Field plate 24.Because field plate is floating thus, the flux of this two parts power line is equal.This is equivalent to the N in semiconductor depletion layer
Area and metal layer introduce opposite polarity charge respectively, and the electric field that both charges generate is contrary with original electric field,
Therefore peak value electric field is reduced.
In one embodiment, in order to simplify making technology, second polysilicon field plate 23 and first polysilicon
Field plate 22 is located on the same floor, and setting is spaced between second polysilicon field plate 23 and second polysilicon field plate 22.Institute
It states between the second polysilicon field plate 23 and first polysilicon field plate 22 by there is dielectric layer 25 to be isolated.In an embodiment
In, second polysilicon field plate 23 is with first polysilicon field plate 22 as made from same making technology.
The first part part of the Metal field plate 24 covers second polysilicon field plate 23, and the Metal field plate 24
First part be the junction in the Metal field plate 24 far from the Metal field plate 24 and the field limiting ring 13 part.Than
If the first part of the Metal field plate 24 is the part far from the second via hole 202 and the first via hole 201.When the second via hole 202
When being located at the left side of Metal field plate 24 with the first via hole 201, the first part of the Metal field plate 24 is such as right part.When
When second via hole 202 and the first via hole 201 are located at the right side of Metal field plate 24, the first part of the Metal field plate 24 is such as
For left part.
The Metal field plate 24 covers the half of second polysilicon field plate 23.That is, and the second polysilicon field plate 23
Center correspond to the right edge position of Metal field plate 24, to further decrease between Metal field plate edge and silicon substrate
Potential difference, and then spike electric field is effectively reduced.
Due to the field plate group by using polysilicon field plate and Metal field plate, so that winner is tied depletion region and effectively broaden outward；
Avoid in silicon and silicon dioxide interface electric field concentration phenomenon, improve breakdown voltage, and Metal field plate respectively with field limiting ring and
Polysilicon field plate is electrically connected, so that Metal field plate keeps equipotential with field limiting ring and polysilicon field plate respectively.Due to metal field
Plate covers polysilicon field plate, so as to form the structure of step field plate, so that winner is tied depletion region and effectively broadens outward, improve and hit
Voltage is worn, in addition, also reducing the spike electric field at field plate edge.
It should be understood that other than the field limiting ring that the utility model is connected in addition to first with IGBT cellular, each field later
The Metal field plate 24 of limit ring 13 joins in vertical direction with the second polysilicon field plate 23 in 13 structure of a upper field limiting ring, i.e.,
The terminal structure that this utility model may be implemented projects the area for being superimposed the section formed and entire terminal in vertical direction
Cross-sectional area it is equal, also may make field plate project in vertical direction superposition formed section area and entire terminal cross
Sectional area is equal, to avoid silica to the shielding of interface charge difference and the processes such as technique manufacture, encapsulation introduce can
The problem of dynamic ion accumulates in oxide layer or enters silicon through oxide layer, field distribution is made to change.
The terminal for semiconductor power device of the utility model, by using the field of polysilicon field plate and Metal field plate
Board group, and Metal field plate is electrically connected with field limiting ring and polysilicon field plate respectively, so that winner is tied depletion region and is effectively broadened outward, from
And it improves breakdown voltage and reduces the spike electric field at field plate edge.
Although above preferred embodiment is not used in conclusion the utility model is disclosed above with preferred embodiment
To limit the utility model, those skilled in the art can make without departing from the spirit and scope of the utility model
It is various to change and retouch, therefore the protection scope of the utility model subjects to the scope of the claims.
Claims (9)
1. a kind of terminal for semiconductor power device characterized by comprising
Collector, base area, multiple field limiting rings and multiple field plate groups corresponding with the field limiting ring, the field plate group include mutual
The first polysilicon field plate and Metal field plate being electrically connected, first polysilicon field plate, the Metal field plate are sequentially located at institute
The top of field limiting ring is stated, first polysilicon field plate and the Metal field plate are electrically connected with the field limiting ring, the gold
Belong to field plate and covers first polysilicon field plate；
The length of the Metal field plate is greater than the length of first polysilicon field plate.
2. the terminal according to claim 1 for semiconductor power device, which is characterized in that described to be used for semiconductor function
The terminal of rate device further includes the second polysilicon field plate, and second polysilicon field plate is located at the field limiting ring and the metal field
Between plate, and the Metal field plate only partially covers second polysilicon field plate.
3. the terminal according to claim 2 for semiconductor power device, which is characterized in that second polysilicon field
Plate is located on the same floor with first polysilicon field plate, and between second polysilicon field plate and first polysilicon field plate
Interval setting.
4. the terminal according to claim 2 for semiconductor power device, which is characterized in that the of the Metal field plate
A part of part covers second polysilicon field plate, and the first part of the Metal field plate is separate in the Metal field plate
The part of the junction of the Metal field plate and the field limiting ring.
5. the terminal according to claim 2 for semiconductor power device, which is characterized in that the Metal field plate covering
The half of second polysilicon field plate.
6. the terminal according to claim 1 for semiconductor power device, which is characterized in that first polysilicon field
It is provided with field oxide between plate and the field limiting ring, the first via hole, first polysilicon are provided on the field oxide
Field plate is electrically connected by first via hole and the field limiting ring.
7. the terminal according to claim 6 for semiconductor power device, which is characterized in that first polysilicon field
Between plate and the Metal field plate and the Metal field plate with do not covered by first polysilicon field plate and the field oxide
It is provided with dielectric layer between the field limiting ring of lid, the second via hole is provided on the dielectric layer, the Metal field plate passes through described
Second via hole and the field limiting ring are electrically connected.
8. the terminal according to claim 7 for semiconductor power device, which is characterized in that also set on the dielectric layer
It is equipped with third via hole, first polysilicon field plate is electrically connected by the third via hole and the Metal field plate.
9. the terminal according to claim 7 for semiconductor power device, which is characterized in that second via hole and institute
State the same side that the first via hole is located at the field limiting ring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821240990.6U CN208797006U (en) | 2018-08-02 | 2018-08-02 | A kind of terminal for semiconductor power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821240990.6U CN208797006U (en) | 2018-08-02 | 2018-08-02 | A kind of terminal for semiconductor power device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208797006U true CN208797006U (en) | 2019-04-26 |
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ID=66204305
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821240990.6U Active CN208797006U (en) | 2018-08-02 | 2018-08-02 | A kind of terminal for semiconductor power device |
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| Country | Link |
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| CN (1) | CN208797006U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108767002A (en) * | 2018-08-02 | 2018-11-06 | 盛廷微电子（深圳）有限公司 | A kind of terminal for semiconductor power device |
-
2018
- 2018-08-02 CN CN201821240990.6U patent/CN208797006U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108767002A (en) * | 2018-08-02 | 2018-11-06 | 盛廷微电子（深圳）有限公司 | A kind of terminal for semiconductor power device |
| CN108767002B (en) * | 2018-08-02 | 2024-03-26 | 盛廷微电子（深圳）有限公司 | Terminal for semiconductor power device |
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