CN113903814A - Fast turn-on diode and manufacturing method - Google Patents
Fast turn-on diode and manufacturing method Download PDFInfo
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Abstract
The invention relates to a fast open diode and a manufacturing method thereof in the technical field of semiconductors, which comprises a cathode layer, an anode layer and a substrate layer, wherein the cathode layer and the anode layer are arranged on the same surface of the substrate layer, the cathode layer and the anode layer are positioned at two ends of the same surface, a first inversion doping layer is embedded on the substrate layer, the anode layer is connected with the substrate layer and the first inversion doping layer, a plurality of second inversion doping layers are embedded on the substrate layer at intervals, a plurality of contact layers are also arranged on the substrate layer, and the contact layers are connected with the substrate layer and the second inversion doping layers.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a fast turn-on diode and a manufacturing method thereof.
Background
In recent years, energy conservation and emission reduction are more and more emphasized internationally, which puts higher requirements on loss control and efficiency improvement of large-scale power electronic equipment. Semiconductor power devices have received much attention in the industry as an important component of power electronic equipment.
The breakdown voltage is an important index of a semiconductor power device and represents the maximum voltage which the device can withstand, when a diode is changed from a reverse blocking state to a forward conducting state, a P-type doped region inside a drift region is not directly connected with an electrode, hole carriers near an anode cannot enter the P-type doped region, negative charges are left in the P-type doped region, a large amount of positive charges are attracted in a substrate layer, an N-type substrate layer is filled with the positive charges in a space charge mode, energy band bending is caused, and therefore the flow of the electron carriers is blocked, namely, the diode with the floating doped region in the drift region cannot be recovered in the forward direction.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a fast turn-on diode and a manufacturing method thereof, which have the advantages of eliminating current obstruction and breaking through the bottleneck that the forward conduction capability can not be recovered under lower forward bias.
In order to solve the technical problem, the invention is solved by the following technical scheme:
the utility model provides a fast open diode, includes cathode layer, anode layer and substrate layer, cathode layer and anode layer set up on the same surface of substrate layer, just cathode layer and anode layer are located the both ends on same surface, it is provided with first inversion doping layer to inlay on the substrate layer, just anode layer connection substrate layer and first inversion doping layer, the interval is inlayed and is provided with a plurality of second inversion doping layers on the substrate layer, still be provided with a plurality of contact layers on the substrate layer, contact substrate layer is connected with second inversion doping layer.
Optionally, the number of the contact layers is the same as the number of the second inversion doping layers.
Optionally, the length of the contact layer is less than the length of the second inversion doping layer.
Optionally, a plurality of groups of contact layers are disposed on each group of the second inversion doping layer and the substrate layer.
Optionally, the total length of the contact layers is less than the length of the second inversion doping layer.
Optionally, the length of the first inversion doping layer is less than or equal to the width of the substrate layer.
Optionally, the length of the second inversion doping layer is less than or equal to the width of the substrate layer.
Optionally, the first inversion doping layer and the second inversion doping layer are made of the same type of semiconductor material.
Optionally, the first inversion doping layer and the substrate layer are of opposite type semiconductor materials.
A manufacturing method of a fast turn-on diode comprises the following steps:
forming a first inversion doping layer and a plurality of second inversion doping layers in a substrate layer by a photoetching method or an ion implantation method, wherein the first inversion doping layer and the plurality of second inversion doping layers are arranged in parallel and are arranged at intervals;
forming a cathode layer and a contact layer on the substrate layer by a metal sputtering method or a metal evaporation method, connecting the contact layer with the substrate layer and the second inversion doping layer by high-temperature annealing, and connecting the cathode layer with the substrate layer;
and forming an anode layer on the substrate layer by a metal sputtering method or a metal evaporation method, and connecting the anode layer with the substrate layer and the first inversion doping layer by high-temperature annealing.
Compared with the prior art, the technical scheme provided by the invention has the following beneficial effects:
through introducing the contact layer, make when the diode becomes forward conduction state by reverse block state, the contact layer that has all formed ohmic contact with substrate layer and second inversion doping area can conduction current, thereby for the unable electric charge that releases provides compound passageway in substrate layer and the second inversion doping area, make electric charge in the drift region also can be eliminated when forward bias is lower, avoid piling up the hindrance effect to the electric current because of the electric charge, make the drift region can switch on the electric current from positive pole to the negative pole smoothly, and then make the diode still can resume forward conduction ability even under lower forward bias.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic perspective view of a fast turn-on diode according to a first embodiment of the present disclosure;
fig. 2 is a top view of a fast turn-on diode according to the first embodiment;
fig. 3 is a front view of a fast turn-on diode according to the first embodiment;
fig. 4 is a schematic perspective view of a fast turn-on diode according to a second embodiment of the present invention;
fig. 5 is a schematic perspective view of a fast turn-on diode according to a third embodiment of the present invention;
FIG. 6 is a graph of the band distribution of a prior art diode changing from a reverse blocking state to a forward conducting state at a lower forward bias;
fig. 7 is a band distribution diagram when the diode changes from the reverse blocking state to the forward conducting state at 692V in the forward bias.
Reference numerals: 1. a cathode layer; 2. an anode layer; 3. a substrate layer; 4. a first inversion doping layer; 5. a second inversion doping layer; 6. a contact layer; 7. a first substrate; 8. a second substrate.
Detailed Description
The present invention will be described in further detail with reference to examples, which are illustrative of the present invention and are not to be construed as being limited thereto.
Example one
When the conventional diode is converted from a reverse blocking state to a forward conducting state, since the P-type doped regions inside the drift region are not directly connected with the electrodes, hole carriers near the anode cannot enter the P-type doped regions, so that negative charges remain in the P-type doped regions, and in the substrate layer 3, a large amount of positive charges are attracted to occupy the N-type substrate layer 3 in the form of space charges, so that energy band bending is caused, and the energy band bending is shown in fig. 6, thereby blocking the flow of electron carriers, whereas the conventional solution is to enable the charges to conduct through the drift region by increasing the forward voltage, as shown in fig. 7, namely, the energy band diagram when the forward voltage is increased to 692V.
As shown in fig. 1, to the above-mentioned problem that the diode can not recover the forward conduction capability under the condition of lower forward bias, this embodiment provides a fast turn-on diode, including cathode layer 1, anode layer 2 and substrate layer 3, cathode layer 1 and anode layer 2 set up the same surface at substrate layer 3, and cathode layer 1 and anode layer 2 are located the both ends of the same surface, it is provided with first anti-type doping layer 4 to inlay on substrate layer 3, and anode layer 2 connects substrate layer 3 and first anti-type doping layer 4, it is provided with a plurality of second anti-type doping layers 5 to inlay at the interval on substrate layer 3, still be provided with a plurality of contact layers 6 on substrate layer 3, contact layer 6 connects substrate layer 3 and second anti-type doping layer 5.
The first counter doping layer 4 and the second counter doping layer 5 are made of the same type of semiconductor material, the first counter doping layer 4 and the substrate layer 3 are made of the opposite type of semiconductor material, the contact layer 6 is made of an alloy material, in this embodiment, the substrate layer 3 includes a first substrate 7 and a second substrate 8, the first substrate 7 is used for protecting the second substrate 8, specifically, the first substrate 7 and the second counter doping layer 5 are made of the same type of semiconductor material, and the second substrate 8 and the first counter doping layer 4 are made of the opposite type of semiconductor material.
As shown in fig. 3, taking the first substrate 7 as an N-type semiconductor material as an example, in this case, the second substrate 8 is a P-type semiconductor material, the first inversion doping layer 4 and the second inversion doping layer 5 are both N-type semiconductor materials, and the doping concentrations of the first substrate 7, the first inversion doping layer 4 and the second inversion doping layer 5 are set to be 1 × 1015cm-3~1×1019cm-3The doping concentration of the second substrate 8 is 1 × 1015cm-3~1×1017cm-3At this time, an ohmic contact is formed between the cathode layer 1 and the second substrate 8, a schottky contact is formed between the anode layer 2 and the second substrate 8, an ohmic contact is formed between the anode layer 2 and the first inversion doping layer 4, an ohmic contact is formed between the contact layer 6 and the second substrate 8, and an ohmic contact is also formed between the anode layer and the second inversion doping layer 5, in the same manner, in order to improve the ohmic contact, an N-type semiconductor material having a higher doping concentration than that of the other second substrate 8 is used at a position where the second substrate 8 is located near the contact layer 6, and the position can be set to a region of 1 μm around the contact layer 6.
As shown in fig. 1 and 2, the number of the contact layers 6 is the same as the number of the second inversion doping layers 5, the length of the contact layers 6 is smaller than the length of the second inversion doping layers 5, the length of the first inversion doping layer 4 is smaller than or equal to the width of the substrate layer 3, the length of the second inversion doping layer 5 is smaller than or equal to the width of the substrate layer 3, wherein the length of the contact layers 6, the length of the second inversion doping layer 5, and the length of the first inversion doping layer 4 are all set to be the side length in the Y direction, and the width of the substrate layer 3 is also set to be the side length in the Y direction.
Each group of the second inversion doping layers 5 may be correspondingly provided with a group of contact layers 6 to connect the second substrate 8 and the second inversion doping layer 5, and further, in this embodiment, the shape and the position of the contact layer 6 only need to be satisfied with the contact with the second substrate 8 and the second inversion doping layer 5 at the same time, on the other hand, when the length of the contact layer 6 is greater than or equal to the length of the second inversion doping layer 5, since the depletion region will expand from left to right during blocking, the second inversion doping layer 5 will be blocked by the contact layer 6, so that the depletion region will be cut off when expanding to the first contact layer 6 from left, and further cause early breakdown, therefore, the length of the contact layer 6 is set to be smaller than the length of the second inversion doping layer 5.
Thereby through introducing contact layer 6, make when the diode becomes forward conducting state by reverse block state, contact layer 6 that all formed ohmic contact with substrate layer 3 and second inversion doping area can conduction current, thereby for the unable electric charge that releases provides compound passageway in substrate layer 3 and the second inversion doping area, make electric charge in the drift region also can be eliminated when forward bias is lower, avoid piling up the hindrance effect to the electric current because of the electric charge, make the drift region can switch on the electric current from positive pole to negative pole smoothly, and then make the diode still can resume forward conducting capacity under lower forward bias.
Example two
To under the lower forward bias condition, the unable problem of recovering forward conduction ability of diode, this embodiment has provided a fast diode of opening, including cathode layer 1, anode layer 2 and substrate layer 3, cathode layer 1 and anode layer 2 set up the same surface at substrate layer 3, and cathode layer 1 and anode layer 2 are located the both ends of same surface, it is provided with first anti-type doping layer 4 to inlay on substrate layer 3, and anode layer 2 connects substrate layer 3 and first anti-type doping layer 4, the interval is inlayed and is provided with a plurality of second anti-type doping layers 5 on the substrate layer 3, still be provided with a plurality of contact layers 6 on the substrate layer 3, substrate layer 3 and second anti-type doping layer 5 are connected to contact layer 6.
The first counter doping layer 4 and the second counter doping layer 5 are made of the same type of semiconductor material, the first counter doping layer 4 and the substrate layer 3 are made of the opposite type of semiconductor material, the contact layer 6 is made of an alloy material, in this embodiment, the substrate layer 3 includes a first substrate 7 and a second substrate 8, the first substrate 7 is used for protecting the second substrate 8, specifically, the first substrate 7 and the second counter doping layer 5 are made of the same type of semiconductor material, and the second substrate 8 and the first counter doping layer 4 are made of the opposite type of semiconductor material.
As shown in fig. 4, taking the first substrate 7 as an N-type semiconductor material as an example, in this case, the second substrate 8 is a P-type semiconductor material, the first inversion doping layer 4 and the second inversion doping layer 5 are both N-type semiconductor materials, and the doping concentrations of the first substrate 7, the first inversion doping layer 4 and the second inversion doping layer 5 are set to be 1 × 1015cm-3~1×1019cm-3The doping concentration of the second substrate 8 is 1 × 1015cm-3~1×1017cm-3At this time, ohmic contact is formed between the cathode layer 1 and the second substrate 8In order to improve ohmic contact, an N-type semiconductor material having a higher doping concentration than a portion of the other second substrate 8 may be used at a position of the second substrate 8 near the contact layer 6, and the position may be set to a region of 1 μm around the contact layer 6.
Compared with the first embodiment, the difference of the present embodiment is that a plurality of groups of contact layers 6 are disposed on each group of second inversion doping layers 5 and the substrate layer 3, the total length of the plurality of groups of contact layers 6 is less than the length of the second inversion doping layers 5, that is, each group of second inversion doping layers 5 can be correspondingly provided with a plurality of groups of contact layers 6 to connect the second substrate 8 layer 3 and the second inversion doping layers 5, and the shape and the position of the contact layers 6 only need to meet the requirement of simultaneously contacting the second substrate 8 and the second inversion doping layers 5, so that the contact layers 6 are disposed on each group of second inversion doping layers 5 at intervals, thereby not only realizing the recovery of the forward conduction capability under a lower forward bias voltage, but also reducing the investment cost of the contact layers 6.
On the other hand, the length of the first inversion doping layer 4 is less than or equal to the width of the substrate layer 3, the length of the second inversion doping layer 5 is less than or equal to the width of the substrate layer 3, wherein the length of the contact layer 6, the length of the second inversion doping layer 5 and the length of the first inversion doping layer 4 are all set to be the side length along the Y direction, and the width of the substrate layer 3 is also set to be the side length along the Y direction.
Thereby through introducing contact layer 6, make when the diode becomes forward conducting state by reverse block state, contact layer 6 that all formed ohmic contact with substrate layer 3 and second inversion doping area can conduction current, thereby for the unable electric charge that releases provides compound passageway in substrate layer 3 and the second inversion doping area, make electric charge in the drift region also can be eliminated when forward bias is lower, avoid piling up the hindrance effect to the electric current because of the electric charge, make the drift region can switch on the electric current from positive pole to negative pole smoothly, and then make the diode still can resume forward conducting capacity under lower forward bias.
EXAMPLE III
As shown in fig. 5, for the problem that the diode cannot recover the forward conduction capability under the condition of a lower forward bias voltage, the embodiment provides a fast turn-on diode, which includes a cathode layer 1, an anode layer 2 and a substrate layer 3, the cathode layer 1 and the anode layer 2 are disposed on the same surface of the substrate layer 3, and the cathode layer 1 and the anode layer 2 are disposed at two ends of the same surface, a first inverse doping layer 4 is inlaid on the substrate layer 3, the anode layer 2 is connected with the substrate layer 3 and the first inverse doping layer 4, a plurality of second inverse doping layers 5 are inlaid on the substrate layer 3 at intervals, a plurality of contact layers 6 are further disposed on the substrate layer 3, and the contact layers 6 are connected with the substrate layer 3 and the second inverse doping layers 5.
The difference between this embodiment and the first embodiment is that the substrate layer 3 is provided with only one layer, and at this time, since the first and second inversion doping layers 4 and 5 are the same type of semiconductor material, the first and second inversion doping layers 4 and 3 are opposite type of semiconductor material, and the contact layer 6 is made of alloy material.
Therefore, taking the substrate layer 3 as an N-type semiconductor material as an example, in this case, the first and second inversion- type doping layers 4 and 5 are both P-type semiconductor materials, and the doping concentrations of the first and second inversion- type doping layers 4 and 5 are set to 1 × 1015cm-3~1×1019cm-3The doping concentration of the substrate layer 3 is 1 x 1015cm-3~1×1017cm-3At this time, ohmic contact is formed between the cathode layer 1 and the substrate layer 3, schottky contact is formed between the anode layer 2 and the substrate layer 3, ohmic contact is formed between the anode layer 2 and the first inversion doping layer 4, ohmic contact is formed between the contact layer 6 and the substrate layer 3, and ohmic contact is formed between the contact layer and the second inversion doping layerOhmic contacts are similarly formed between the type-doping layers 5, and in order to improve the ohmic contacts, an N-type semiconductor material having a higher doping concentration than that of the other substrate layer 3 may be used at a position of the substrate layer 3 in the vicinity of the contact layer 6, and the position may be set to a region of 1 μm around the contact layer 6.
The number of the contact layers 6 is the same as that of the second inversion doping layers 5, the length of the contact layers 6 is smaller than that of the second inversion doping layers 5, the length of the first inversion doping layer 4 is smaller than or equal to the width of the substrate layer 3, the length of the second inversion doping layer 5 is smaller than or equal to the width of the substrate layer 3, the length of the contact layers 6, the length of the second inversion doping layer 5 and the length of the first inversion doping layer 4 are all set to be along the side length in the Y direction, and the width of the substrate layer 3 is also set to be along the side length in the Y direction.
Each group of second inversion doping layers 5 can be correspondingly provided with a group of contact layers 6 for connecting the substrate layer 3 and the second inversion doping layer 5, further, in this embodiment, the shape and the position of the contact layer 6 only need to be satisfied with the substrate layer 3 and the second inversion doping layer 5 at the same time, on the other hand, when the length of the contact layer 6 is greater than or equal to the length of the second inversion doping layer 5, since the depletion region will expand from left to right during blocking, the second inversion doping layer 5 will be blocked by the contact layer 6, so that the depletion region is blocked when expanding to the first contact layer 6 from left, and further early breakdown is caused, and therefore, the length of the contact layer 6 is set to be smaller than the length of the second inversion doping layer 5.
Therefore, by introducing the contact layer 6, when the diode is changed from a reverse blocking state to a forward conducting state, the contact layer 6 which forms ohmic contact with the substrate layer 3 and the second inversion doping region can conduct current, thereby providing a composite channel for charges which cannot be released in the substrate layer 3 and the second inversion doping region, eliminating the charges in the drift region when the forward bias voltage is lower, avoiding the blocking effect on the current due to charge accumulation, enabling the drift region to smoothly conduct the current from the anode to the cathode, further enabling the diode to still recover the forward conducting capability even under the lower forward bias voltage, and simultaneously, by directly introducing the contact layer 6, the first inversion doping layer 4 and the second inversion doping layer 5 on the basis of the existing substrate layer 3, reducing the input cost of the material of the substrate layer 3 and reducing the processing procedure, the processing load is reduced.
Example four
A manufacturing method of a fast turn-on diode comprises the following steps: forming a first inversion doping layer 4 and a plurality of second inversion doping layers 5 in the substrate layer 3 by a photolithography method or an ion implantation method, wherein the first inversion doping layer 4 and the plurality of second inversion doping layers 5 are arranged in parallel, and the plurality of second inversion doping layers 5 are arranged at intervals; forming a cathode layer 1 and a contact layer 6 on the substrate layer 3 by a metal sputtering method or a metal evaporation method, connecting the contact layer 6 with the substrate layer 3 and the second inversion doping layer 5 by high-temperature annealing, and connecting the cathode layer 1 with the substrate layer 3; the anode layer 2 is formed on the substrate layer 3 by a metal sputtering method or a metal evaporation method, and the anode layer 2 connects the substrate layer 3 and the first inversion doping layer 4 by high-temperature annealing.
Taking the first embodiment as an example, when the substrate layer 3 includes the first substrate 7 and the second substrate 8, the P-type second substrate 8 is grown on the N-type first substrate 7, if only one layer is disposed on the substrate layer 3, another substrate layer 3 does not need to be grown on the substrate layer 3, and then the first and second opposite-type doping layers 4 and 5 are formed in the second substrate 8 by photolithography, ion implantation, and the like, so that the first and second opposite-type doping layers 4 and 5 are distributed at intervals and arranged in parallel, and the implanted first and second opposite-type doping layers 4 and 5 are both doped at a doping concentration of 1 × 1015cm-3~1×1019cm-3The N-type semiconductor material of (1).
After the injection of the first and second inversion doping layers 4 and 5 is completed, the cathode layer 1, the anode layer 2, and the contact layer 6 are formed on the second substrate 8 by a metal sputtering method or a metal evaporation method, and the contact layer 6 formed at this time is an ohmic metal, and then ohmic contacts are formed between the cathode layer 1 and the second substrate 8, between the ohmic metal and the second inversion doping layer 5, and between the anode layer 2 and the first inversion doping layer 4 by high-temperature annealing, so that schottky contacts are formed between the anode layer 2 and the second substrate 8, and the ohmic metal forms an alloy with the first and second inversion doping layers 4 and 8 during the high-temperature annealing process, thereby implementing ohmic contacts, and the temperature of the high-temperature annealing in this embodiment may be set to one thousand degrees, thereby completing the manufacturing process.
In addition, it should be noted that the specific embodiments described in the present specification may differ in the shape of the components, the names of the components, and the like. All equivalent or simple changes of the structure, the characteristics and the principle of the invention which are described in the patent conception of the invention are included in the protection scope of the patent of the invention. Various modifications, additions and substitutions for the specific embodiments described may be made by those skilled in the art without departing from the scope of the invention as defined in the accompanying claims.
Claims (10)
1. The utility model provides a fast open diode, its characterized in that includes cathode layer, anode layer and substrate layer, cathode layer and anode layer set up the same surface at the substrate layer, just cathode layer and anode layer are located the both ends on same surface, inlay on the substrate layer and be provided with first anti-type doping layer, just anode layer connection substrate layer and first anti-type doping layer, the interval is inlayed and is provided with a plurality of second anti-type doping layers on the substrate layer, still be provided with a plurality of contact layers on the substrate layer, the contact layer is connected substrate layer and second anti-type doping layer.
2. The fast turn-on diode of claim 1, wherein the number of contact layers is the same as the number of second inversion doped layers.
3. The fast turn-on diode of claim 2, wherein the contact layer has a length less than a length of the second inversion doping layer.
4. The fast turn-on diode of claim 1, wherein each of the second inversion doping layer and the substrate layer has a plurality of contact layers disposed thereon.
5. The fast turn-on diode of claim 4, wherein the total length of the plurality of sets of contact layers is less than the length of the second inversion doped layer.
6. The fast turn-on diode of claim 1, wherein the length of the first inversion doping layer is less than or equal to the width of the substrate layer.
7. The fast turn-on diode of claim 1, wherein the length of the second inversion doping layer is less than or equal to the width of the substrate layer.
8. The fast turn-on diode of claim 1, wherein the first and second counter-doped layers are the same type of semiconductor material.
9. The fast turn-on diode of claim 8, wherein the first counter doping layer and the substrate layer are of opposite type semiconductor material.
10. A method for manufacturing a fast turn-on diode is characterized by comprising the following steps:
forming a first inversion doping layer and a plurality of second inversion doping layers in a substrate layer by a photoetching method or an ion implantation method, wherein the first inversion doping layer and the plurality of second inversion doping layers are arranged in parallel and are arranged at intervals;
forming a cathode layer and a contact layer on the substrate layer by a metal sputtering method or a metal evaporation method, connecting the contact layer with the substrate layer and the second inversion doping layer by high-temperature annealing, and connecting the cathode layer with the substrate layer;
and forming an anode layer on the substrate layer by a metal sputtering method or a metal evaporation method, and connecting the anode layer with the substrate layer and the first inversion doping layer by high-temperature annealing.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569067A (en) * | 2012-02-17 | 2012-07-11 | 北京时代民芯科技有限公司 | Method for manufacturing planar high-voltage ultrafast soft recovery diode |
| CN103811336A (en) * | 2014-02-21 | 2014-05-21 | 成都方舟微电子有限公司 | IGBT (Insulated Gate Bipolar Translator) power device applied at low power and manufacturing method thereof |
| CN112687749A (en) * | 2020-12-14 | 2021-04-20 | 株洲中车时代半导体有限公司 | Fast recovery diode and manufacturing method thereof |
| CN112786708A (en) * | 2021-03-04 | 2021-05-11 | 深圳吉华微特电子有限公司 | Ultra-low VF soft fast recovery diode and manufacturing method thereof |
| CN113675277A (en) * | 2021-10-21 | 2021-11-19 | 浙江大学杭州国际科创中心 | Diode and manufacturing method thereof |
-
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569067A (en) * | 2012-02-17 | 2012-07-11 | 北京时代民芯科技有限公司 | Method for manufacturing planar high-voltage ultrafast soft recovery diode |
| CN103811336A (en) * | 2014-02-21 | 2014-05-21 | 成都方舟微电子有限公司 | IGBT (Insulated Gate Bipolar Translator) power device applied at low power and manufacturing method thereof |
| CN112687749A (en) * | 2020-12-14 | 2021-04-20 | 株洲中车时代半导体有限公司 | Fast recovery diode and manufacturing method thereof |
| CN112786708A (en) * | 2021-03-04 | 2021-05-11 | 深圳吉华微特电子有限公司 | Ultra-low VF soft fast recovery diode and manufacturing method thereof |
| CN113675277A (en) * | 2021-10-21 | 2021-11-19 | 浙江大学杭州国际科创中心 | Diode and manufacturing method thereof |
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