CN103794550A - Formation method for electrical interconnection structure - Google Patents

Formation method for electrical interconnection structure Download PDF

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CN103794550A
CN103794550A CN201210429412.8A CN201210429412A CN103794550A CN 103794550 A CN103794550 A CN 103794550A CN 201210429412 A CN201210429412 A CN 201210429412A CN 103794550 A CN103794550 A CN 103794550A
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layer
opening
photoresist layer
photoresist
conductive
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CN103794550B (en
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洪中山
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A formation method for an electrical interconnection structure comprises the following steps: providing a dielectric layer on the surface of a semiconductor substrate, wherein the dielectric layer is internally provided with a first opening running through the thickness of the dielectric layer; forming a seed layer on the surface of the dielectric layer and the side walls and the bottom surface of the first opening; forming a second photoresist layer on the seed layer, wherein the material of the second photoresist layer is conductive photoresist, and the second photoresist layer is internally provided with a third opening running through the thickness of the second photoresist layer, the bottom of the third opening exposing the first opening; forming a first photoresist layer on the surface of the second photoresist layer, wherein the material of the first photoresist layer is non-conductive photoresist, and the first photoresist layer is internally provided with a second opening running through the thickness of the first photoresist layer, the second opening being communicated with the third opening; utilizing an electroplating process to form a conductive structure on the surface of the seed layer in the first opening and the bottom of the third opening, wherein the top surface of the conductive structure is lower than or equal to the top surface of the first photoresist layer; and after the conductive structure is formed, removing the second photoresist layer and the first photoresist layer. The electrical interconnection structure is stable in performance.

Description

The formation method of electric interconnection structure
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to the formation method of electric interconnection structure.
Background technology
In field of semiconductor manufacture, in order to realize the electrical connection between semiconductor device, develop at present various metal interconnect structures and formed technique, for example copper interconnection structure, and the copper electroplating technology (ECP, electro-coppering plating) of formation copper interconnection structure.But along with the development of very lagre scale integrated circuit (VLSIC) (ULSI), the characteristic size of semiconductor device (CD) is constantly dwindled, the technique that forms metal interconnect structure has also been subject to challenge.
The cross-sectional view of the forming process of the copper interconnection structure of prior art, as shown in Figure 1 to Figure 3, comprising:
Please refer to Fig. 1, form dielectric layer 101 on Semiconductor substrate 100 surfaces, have the opening 102 that runs through its thickness in described dielectric layer 101, the sidewall of the surface of described dielectric layer 101 and opening 102 and lower surface have the Seed Layer 103 take metal as material.
Please refer to Fig. 2, adopt electroplating technology to form copper interconnection layer 104 on described Seed Layer 103 surfaces.
Please refer to Fig. 3, the copper interconnection layer 104(on dielectric layer surface is as shown in Figure 2 described in etched portions), form copper interconnection structure 104a.
In addition, also can adopt CMP (Chemical Mechanical Polishing) process to remove higher than the copper interconnection layer 104(on dielectric layer 101 surfaces as shown in Figure 2), form copper interconnection structure (not shown).
But the copper interconnection structure pattern that adopts prior art to form is not good, poor stability.
The related data of more copper interconnection structures please refer to the U.S. patent documents that publication number is US2008/0026579.
Summary of the invention
The problem that the present invention solves is to provide the formation method of electric interconnection structure, improves the pattern of the electric interconnection structure forming, and improves stability.
For addressing the above problem, the invention provides a kind of formation method of electric interconnection structure, comprising: Semiconductor substrate is provided, and described semiconductor substrate surface has dielectric layer in described dielectric layer, thering is the first opening that runs through its thickness; Sidewall and lower surface at described dielectric layer surface and described the first opening form Seed Layer; Form the second photoresist layer on described Seed Layer surface, the material of described the second photoresist layer is conduction photoresist, and in described the second photoresist layer, has the 3rd opening that runs through its thickness, and the bottom-exposed of described the 3rd opening goes out described the first opening; Form the first photoresist layer on described the second photoresist layer surface, the material of described the first photoresist layer is non-conductive photoresist, and has the second opening that runs through its thickness in described the first photoresist layer, and described the second opening and the perforation of the 3rd opening; Adopt electroplating technology to form conductive structure on the Seed Layer surface of described the first opening and the 3rd open bottom, the top surface of described conductive structure is less than or equal to the top surface of described the first photoresist layer; Forming after conductive structure, remove described the second photoresist layer and the first photoresist layer.
Alternatively, described the 3rd opening is by forming described the second photoresist layer exposure; Described the second opening is by forming described the first photoresist layer exposure.
Alternatively, the conductivity of described the second photoresist layer is every centimetre of every centimetre of 10-10 Siemens ~ 10-6 Siemens, in the conduction photoetching glue material of described the second photoresist layer, contain propylene oxide ester, thermal curing agents, lithographic printing active component, photoactive component, additive and electric conductive polymer, described electric conductive polymer comprises: polyaniline, polypyrrole, one or more in polythiophene, polyphenylene vinylene, poly-diakyl fluorenes, polyaniline derivative, poly-plug fen derivative or nano composite polymer.
Alternatively, the material of described conductive structure is copper, and the formation technique of described conductive structure is copper electroplating technology.
Alternatively, in the Semiconductor substrate of described the first open bottom, have conductive layer, described the first opening exposes described conductive layer, and the material of described conductive layer is copper, tungsten, aluminium or silver.
Alternatively, also comprise: before forming Seed Layer, form barrier layer in sidewall and the lower surface of described dielectric layer surface and described the first opening, the material on described barrier layer comprises tantalum, tantalum nitride, titanium, titanium nitride, copper manganese, copper aluminium, cobalt or lanthanum.
Alternatively, the material of described Seed Layer is copper, copper titanium or copper manganese, and formation technique is physical gas-phase deposition.
Alternatively, also comprise: removing after the first photoresist layer, take described conductive structure as mask, the Seed Layer on dielectric layer surface is until expose described dielectric layer described in etching.
The formation method of electric interconnection structure, is characterized in that as claimed in claim 8, and in the time that the technique of the Seed Layer on dielectric layer surface described in etching is dry etching, etching gas comprises Cl 2and BCl 3in one or both, bias power is greater than 200 watts; In the time that the technique of the Seed Layer on dielectric layer surface described in etching is wet etching, etching liquid comprises H 2o 2with one or both in HCl.
Alternatively, in the time of the Seed Layer on dielectric layer surface described in etching, the drift angle at conductive structure top described in etching, makes described drift angle form fillet.
Accordingly, the present invention also provides the formation method of another kind of electric interconnection structure, comprising: Semiconductor substrate is provided, and described semiconductor substrate surface has dielectric layer, has the first opening that runs through its thickness in described dielectric layer; Sidewall and lower surface at described dielectric layer surface and described the first opening form Seed Layer; Form the first photoresist layer on described Seed Layer surface, the material of described the first photoresist layer is non-conductive photoresist, and has the second opening that runs through its thickness in described the first photoresist layer, and described the second open bottom exposes described the first opening; Adopt electroplating technology to form conductive structure on the Seed Layer surface of described the first opening inner bottom part, the top surface of described conductive structure is less than or equal to the top surface of described the first photoresist layer; Forming after conductive structure, remove described the first photoresist layer.
Alternatively, described the second opening is by forming described the first photoresist layer exposure.
Alternatively, the material of described conductive structure is copper, and the formation technique of described conductive structure is copper electroplating technology.
Alternatively, in the Semiconductor substrate of described the first open bottom, have conductive layer, described the first opening exposes described conductive layer, and the material of described conductive layer is copper, tungsten, aluminium or silver.
Alternatively, also comprise: before forming Seed Layer, form barrier layer in sidewall and the lower surface of described dielectric layer surface and described the first opening, the material on described barrier layer comprises tantalum, tantalum nitride, titanium, titanium nitride, copper manganese, copper aluminium, cobalt or lanthanum.
Alternatively, the material of described Seed Layer is copper, copper titanium or copper manganese, and formation technique is physical gas-phase deposition.
Alternatively, also comprise: removing after the first photoresist layer, take described conductive structure as mask, the Seed Layer on dielectric layer surface is until expose described dielectric layer described in etching.
Alternatively, in the time that the technique of the Seed Layer on dielectric layer surface described in etching is dry etching, etching gas comprises Cl 2and BCl 3in one or both, bias power is greater than 200 watts; In the time that the technique of the Seed Layer on dielectric layer surface described in etching is wet etching, etching liquid comprises H 2o 2with one or both in HCl.
Alternatively, in the time of the Seed Layer on dielectric layer surface described in etching, the drift angle at conductive structure top described in etching, makes described drift angle form fillet.
Alternatively, the material of described the first photoresist layer or described the second photoresist layer comprises: propylene oxide ester, thermal curing agents, lithographic printing active component, photoactive component and additive.
Compared with prior art, technical scheme of the present invention has the following advantages:
After forming Seed Layer, before forming the first photoresist layer, form on described Seed Layer surface the second photoresist layer that exposes the first opening, and the material of described the second photoresist layer is conduction photoresist; And described the first photoresist layer is formed at described the second photoresist layer surface; In the time adopting electroplating technology to form conductive structure on the Seed Layer surface of described the first open bottom, because the material of described the second photoresist layer is conduction photoresist, therefore in the Seed Layer superficial growth electric conducting material of the first open bottom, the sidewall surfaces of described the second photoresist layer electric conducting material of also can growing, thereby accelerate to form the speed of conductive structure, saved the process time; Secondly, because the top surface of described the second photoresist layer is covered by described the first photoresist layer, and the material of described the first photoresist layer is non-conductive photoresist, therefore in described electroplating technology, the top surface of described the second photoresist layer electric conducting material of can not growing, avoid after electroplating technology, carrying out again etching technics, and then avoided described etching technics to cause formed conductive structure deformation and made device performance unstable; And described the first photoresist layer and the second photoresist layer easily form and easily remove, and can not produce residual.
Having after the dielectric layer surface of the first opening and the sidewall of the first opening and lower surface formation Seed Layer, form the first photoresist layer on described Seed Layer surface, and described the first photoresist layer has the second opening that exposes the first opening; When adopt electroplating technology described first open with the second opening in after the conductive structure that forms, because described the first photoresist layer is non-conductive photoresist material, the top surface of described the first photoresist layer electric conducting material of can not growing, therefore described the first photoresist layer has defined position and the shape of the conductive structure forming, without formed conductive structure being carried out to etching after electroplating technology, the damage having avoided in etching process, device being caused, make device deformation or adhere to accessory substance at device surface; In addition, described the first photoresist layer easily forms and easily removes, and can not produce residual and simplification technique; The electric interconnection structure stable performance forming.
Accompanying drawing explanation
Fig. 1 to Fig. 3 is the cross-sectional view of the forming process of the copper interconnection structure of prior art;
Fig. 4 to Fig. 8 is the cross-sectional view of the formation method of the electric interconnection structure described in the first embodiment of the present invention;
Fig. 9 to Figure 12 is the cross-sectional view of the formation method of the electric interconnection structure described in the second embodiment of the present invention.
Embodiment
As stated in the Background Art, the copper interconnection structure pattern that adopts prior art to form is not good, poor stability.
Study discovery through the present inventor, please continue to refer to Fig. 1 to Fig. 3, because prior art is after Seed Layer 103 surfaces adopt electroplating technology formation copper interconnection layer 104, need to carry out etching to described copper interconnection layer 104, to form needed copper interconnection structure 104a, especially in the structure of Damascus (damascene), the formation technique of described copper interconnection structure 104a is particularly widely used; But, the technique of existing etching copper easily produces accessory substance, and easily makes the copper interconnection structure 104a after etching deform, thereby affects the stability of device, especially at the size node of semiconductor device in the situation that continuing to dwindle, these problems are particularly outstanding; Particularly, the gas of existing dry etching copper comprises fluorine gas or chlorine, while carrying out etching, need under hot environment, carry out, and described hot environment easily makes metal generation deformation, and then easily open circuit or the problem such as short circuit with described fluorine gas or chlorine; And, after etching technics, easily adhere at device surface the accessory substance that is difficult to removal, can affect equally the performance of device.
Further study through the present inventor, after forming Seed Layer, form on described Seed Layer surface the photoresist layer that exposes described opening, and being formed at the electric interconnection structure on described Seed Layer surface, following adopted electroplating technology defines shape by described photoresist layer, without adopting etching technics or flatening process can form required electric interconnection structure, avoided the device performance that brings due to described etching technics unstable.And, described photoresist layer can be non-conductive photoresist, can also be that conduction photoresist and the non-conductive photoresist that is positioned at conduction photoresist surface form, the sidewall of the described conduction photoresist copper of also can growing in electroplating technology, the speed that therefore can make to form electric interconnection structure is faster, thereby saves the process time.In addition, described photoresist layer can form by exposure, and it is simply thorough to remove technique, can simplify technique, and can not bring the impact of accessory substance.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
The first embodiment
As shown in Fig. 4 to Fig. 8, it is the cross-sectional view of the formation method of the electric interconnection structure described in the first embodiment of the present invention.
Please refer to Fig. 4, Semiconductor substrate 300 is provided, described Semiconductor substrate 300 surfaces have dielectric layer 301, have the first opening 302 that runs through its thickness in described dielectric layer 301.
Described Semiconductor substrate 300 is used to subsequent technique that workbench is provided; Described Semiconductor substrate 300 is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) substrate, glass substrate or III-V compounds of group substrate (such as silicon nitride or GaAs etc.).
In described Semiconductor substrate 300, there is conductive layer 310, the surface of described conductive layer flushes with described semiconductor substrate surface 300, the material of described conductive layer 310 is copper, tungsten, aluminium or silver, and described conductive layer 310 is for electrode or electric connection layer etc. as semiconductor device; The follow-up conductive structure that is formed at described conductive layer 310 surfaces is for being electrically connected described conductive layer 310 and device outside.
The material of described dielectric layer 301 is silica, silicon nitride or low-K dielectric material, and the first opening 302 in described dielectric layer 301 exposes the surface of described conductive layer 310, and the first opening 302 in described dielectric layer 301 is used to form the part in conductive structure; The formation technique of described dielectric layer 301 is: at described Semiconductor substrate 300 and conductive layer 310 surface deposition dielectric films; Etching is positioned at the part dielectric film on described conductive layer 310 surfaces, until expose described conductive layer 310, forms the first opening 302 and dielectric layer 301.
Please refer to Fig. 5, form Seed Layer 303 in sidewall and the lower surface of described dielectric layer 301 surfaces and described the first opening 302.
The material of described Seed Layer 303 is copper, copper titanium or copper manganese, and formation technique is depositing operation, preferably physical gas-phase deposition; Described Seed Layer 303 surfaces are used at follow-up electroplating technology the electric conducting material of growing, to form conductive structure.
Due to the surface of described Seed Layer 303 electric conducting material of all can growing in electroplating technology, therefore, prior art is after electroplating technology, described Seed Layer 303 surfaces are all formed with conductive film, and the conductive film that therefore formed covers sidewall and the lower surface of described dielectric layer 301 and the first opening 302; But, the conductive structure of required formation only needs to cover part dielectric layer 301 surfaces that are positioned at conductive layer 310 correspondence positions, prior art is after forming conductive film, need to carry out etching until expose dielectric layer 301 surfaces to the described conductive film of part and Seed Layer, to form required conductive structure.
But, because the technique of described etching conductive film and Seed Layer 303 is dry etch process, and because etching gas comprises fluorine gas or chlorine, described fluorine gas or chlorine need to can be used for etching technics under hot environment, and the etching environment of described high temperature easily makes formed conductive structure generation deformation and affect device performance, therefore the conductive structure unstable properties that, prior art forms.
Therefore, in the present embodiment, adopting electroplating technology before Seed Layer 303 superficial growth electric conducting materials, forming and expose second photoresist layer on described the first opening 302 and part dielectric layer 301 surfaces and first photoresist layer on the second photoresist layer surface on described Seed Layer 303 surfaces; Wherein, the material of described the first photoresist layer is non-conductive photoresist, can be used in shape and position higher than dielectric layer 301 surface conductive structures partly that definition forms, thereby avoid the conductive film that adopts etching technics etching to grow after electroplating technology, made formed conductive structure stable performance; And the material of described the second photoresist layer is conduction photoresist, in electroplating technology, the sidewall surfaces of described the second photoresist layer and the Seed Layer surface electric conducting material of all can growing, thus accelerate the formation speed of conductive structure, shorten the process time.
It should be noted that, before forming Seed Layer 303, form barrier layer in sidewall and the lower surface of described dielectric layer 301 surfaces and described the first opening 302; The material on described barrier layer comprises tantalum, tantalum nitride, titanium, titanium nitride, copper manganese, copper aluminium, cobalt or lanthanum; Described barrier layer is for transad sublayer 303 and Semiconductor substrate 300, avoid the metallic atom in described Seed Layer 303, or metallic atom in the conductive structure of follow-up formation spreads in technical process, and enter in Semiconductor substrate 300 device performance is declined.
Please refer to Fig. 6, form the second photoresist layer 307 on described Seed Layer 303 surfaces, the material of described the second photoresist layer 307 is conduction photoresist, and in described the second photoresist layer 307, have the 3rd opening 308 that runs through its thickness, the bottom-exposed of described the 3rd opening 308 goes out described the first opening 302; Form the first photoresist layer 304 on described the second photoresist layer 307 surfaces, the material of described the first photoresist layer 304 is non-conductive photoresist, and in described the first photoresist layer 304, there is the second opening 305 that runs through its thickness, described the second opening 305 bottom-exposed go out described the first opening 302, and described the second opening 305 and the 3rd opening 308 connect.
The conductivity of described the second photoresist layer 307 is 10 -10siemens every centimetre ~ 10 -6every centimetre of Siemens, contains electric conductive polymer in the conduction photoetching glue material of described the second photoresist layer 307; Described electric conductive polymer comprises: polyaniline, polypyrrole, one or more in polythiophene, polyphenylene vinylene, poly-diakyl fluorenes, polyaniline derivative, poly-plug fen derivative or nano composite polymer; In addition, the material of described the first photoresist layer 304 or described the second photoresist layer 307 comprises: propylene oxide ester, thermal curing agents, lithographic printing active component, photoactive component and additive.
Described the second photoresist layer 307 exposes the Seed Layer 303 on described the first opening 302 and part dielectric layer 201 surfaces, and described the first photoresist layer 304 covers described the second photoresist layer 307 surfaces, thereby the 3rd opening 308 in the second opening 305, the second photoresist layers 307 in the first photoresist layer 304 and the first opening 302 have defined shape and the position of the conductive structure of follow-up formation; The Seed Layer 303 of described the first opening 302 and the 3rd opening 308 bottoms, and the second photoresist layer 307 surfaces of described the 3rd opening 308 sidewalls electric conducting material of can growing in follow-up electroplating technology, to form conductive structure; And because described the first photoresist layer 304 covers the top surface of described the second photoresist layer 307, therefore, in follow-up electroplating technology, the described electric conducting material of can not growing take conduction photoresist as the top surface of the second photoresist layer 307 of material; And then, after electroplating technology, can form conductive structure without etching technics, guarantee the stability of the conductive structure forming.
The formation technique of described the second photoresist layer 307 and the first photoresist layer 304 is: adopt spin coating proceeding, Seed Layer 303 surfaces in Seed Layer 303 surfaces and first opening 302 at dielectric layer 301 tops form conduction photoresist film, and heat-treat with post bake; Again in the non-conductive photoresist film of described conduction photoresist film surface spin coating, and heat-treat with post bake; Described non-conductive photoresist film and described conduction photoresist film are carried out to exposure figure, to remove in the first opening 302 and non-conductive photoresist film and the described conduction photoresist film on Seed Layer 303 surfaces at part dielectric layer 301 tops, form the second photoresist layer 307 and the first photoresist layer 304.
Described the second photoresist layer 307 and the first photoresist layer 304 form by spin coating and exposure technology, and technique is simple, and follow-up removing photoresist thoroughly, are difficult at the residual accessory substance of device surface; Because the material of described the second photoresist layer 307 is conduction photoresist, in follow-up electroplating technology, electric conducting material is not only in Seed Layer 303 superficial growths of the first opening 302 and the second opening 305 bottoms, also simultaneously can be in the second photoresist layer 307 superficial growths of the 3rd opening 308 sidewalls, therefore can make the formation speed of conductive structure accelerate, be conducive to save the process time; Again because the material of described the first photoresist layer 304 is non-conductive photoresist, and described the first photoresist layer 304 covers the top surface of described the second photoresist layer 307, therefore in follow-up electroplating technology, the top surface of described the first lithography layer 204 and sidewall, and the top surface of the second photoresist layer 307 electric conducting material of all can not growing; Therefore, the conductive structure that electroplating technology forms is only positioned at the first opening 302, the 3rd opening 308 and the second opening 305, and can not be formed at the surface of the first photoresist layer 304; Therefore, be covered in position and shape that second photoresist layer 308 on 303 surfaces, Some Species sublayer and the first photoresist layer 304 can define the conductive structure of required formation, and after follow-up electroplating technology, the conductive structure forming, without through etching technics, has been avoided due to the etching of metal is caused to device performance stability problem; In addition, the formation technique of described the first photoresist layer 204 is simple, and removes technique easily and thoroughly, can not produce residually, further improves device performance.
Please refer to Fig. 7, adopt electroplating technology to form conductive structure 306 on Seed Layer 303 surfaces of described the first opening 302 inner bottom parts, the top surface of described conductive structure 306 is less than or equal to the top surface of described the first photoresist layer 304.
Because described the second photoresist layer 307 is take conduction photoresist as material, therefore in electroplating technology process, the second photoresist layer 307 surfaces of the 3rd opening 308 sidewalls, with Seed Layer 303 surfaces of the first opening 302 and the second opening 305 bottoms electric conducting material of all can growing, thereby can accelerate the formation speed of conductive structure 306, reduce between technique is; Simultaneously, because the material of described the first photoresist layer 304 is non-conductive photoresist, therefore in described electroplating technology, the lower surface of described the first photoresist layer 304 and the sidewall electric conducting material of can not growing, thereby the conductive structure forming 306 is only positioned at the first opening 302, the 3rd opening 308 and the second opening 304, and after described electroplating technology, can form conductive structure 306 without carrying out etching technics, guaranteed the stability of device, and characteristic size is accurate.
In the present embodiment, the material of described conductive structure 306 is copper, and the formation technique of described conductive structure 306 is that copper is electroplated (ECP) technique; It should be noted that, because described conductive structure 306 is formed by electroplating technology, therefore the height of described conductive structure 306 is by the time of concrete electroplating technology, and the thickness of first photoresist layer 304 and the second photoresist layer 307 determines, by controlling the time of electroplating technology with the conductive structure 306 of formation desired height, and the top of the conductive structure 306 forming can be higher than the top of described the first photoresist layer 304.
Please refer to Fig. 8, forming after conductive structure 306, remove described the first photoresist layer 304(as shown in Figure 7) and the second photoresist layer 307(is as shown in Figure 7).
The degumming process that the technique of described removal the first photoresist layer 304 and the second photoresist layer 307 is photoresist is well known to those skilled in the art, and therefore not to repeat here.The technique of described removal the first photoresist layer 204 and the second photoresist layer 307 is simple and remove thoroughly, can be at conductive structure 306 or Seed Layer 303 surface attachment accessory substances, and the device performance forming is stable.
After removing the first photoresist layer 304 and the second photoresist layer 307, take described conductive structure 206 as mask, the Seed Layer 303 on dielectric layer 301 surfaces described in etching, until expose described dielectric layer 201, when the technique of described etching Seed Layer 303 is dry etching, etching gas comprises Cl 2and BCl 3in one or both, bias power is greater than 300 watts; In the time that the technique of the Seed Layer 303 on dielectric layer 301 surfaces described in described etching is wet etching, etching liquid comprises H 2o 2with one or both in HCl.Due to the thinner thickness of described Seed Layer 303, therefore described in etching, the process time of Seed Layer 303 is shorter, less on the impact of device performance.
In the present embodiment, in the time of the Seed Layer 303 on 301 surfaces of dielectric layer described in etching, the drift angle at conductive structure 306 tops described in etching, and by controlling the direction of the gas ion bombardment in described etching technics, make described drift angle form fillet, thereby avoided the drift angle generation electric discharge phenomena at described conductive structure 206 tops.
In the present embodiment, form the second photoresist layer 307 of the Seed Layer 203 that exposes described the first opening 302 and part dielectric layer 201 surfaces on Seed Layer 303 surfaces, then form the first photoresist layer 304 in the second photoresist layer 307 surfaces; Because the material of described the second photoresist layer 307 is conduction photoresist, therefore in electroplating technology, the Seed Layer 303 of described the first opening 302 and the 3rd opening 308 bottoms, and the second photoresist layer 307 surfaces of described the 3rd opening 308 sidewalls electric conducting material of can growing in follow-up electroplating technology, thereby accelerate the formation speed of conductive structure 306, saved the process time; Simultaneously, because the material of described the first photoresist layer 304 is non-conductive photoresist, therefore in described electroplating technology, the top surface of described the first lithography layer 304 and sidewall, and the top surface of the second photoresist layer 307 electric conducting material of all can not growing, make conductive structure only be positioned at the first opening 302, the 3rd opening 308 and the second opening 305, avoided carrying out etching technics after electroplating technology; The conductive structure characteristic size forming is accurate, and stable performance; In addition, the formation technique of described the first photoresist layer 304 and the second photoresist layer 307 is simple, and removes thoroughly, can, at the residual accessory substance of device surface, further not improve the reliability of device.
The second embodiment
As shown in Fig. 9 to Figure 12, it is the cross-sectional view of the formation method of the electric interconnection structure described in the second embodiment of the present invention.
Please refer to Fig. 9, Semiconductor substrate 200 is provided, described Semiconductor substrate 200 surfaces have dielectric layer 201, have the first opening 202 that runs through its thickness in described dielectric layer 201; Sidewall and lower surface at described dielectric layer 201 surfaces and described the first opening 202 form Seed Layer 203.
Described Semiconductor substrate 200, dielectric layer 201, the first opening 202, conductive layer 210 and Seed Layer 203 are as described in the first embodiment, and therefore not to repeat here.
Please refer to Figure 10, form the first photoresist layer 204 on described Seed Layer 203 surfaces, the material of described the first photoresist layer 204 is non-conductive photoresist, and in described the first photoresist layer 204, have the second opening 205 that runs through its thickness, described the second opening 205 bottom-exposed go out described the first opening 202.
Described the first photoresist layer 204 exposes described the first opening 202, and the Seed Layer 203 on part dielectric layer 201 surfaces, and the second opening 205 and the first opening 202 in described the first photoresist layer 204 can define shape and the position that need to form conductive structure; Seed Layer 203 surfaces of described the first opening 202 bottoms and sidewall surfaces and Seed Layer 203 surfaces of the second opening 205 bottoms in follow-up electroplating technology for the electric conducting material of growing, to form conductive structure; And the Seed Layer 203 being covered by described the first photoresist layer 204 is in follow-up electroplating technology, the electric conducting material of can not growing, therefore, after follow-up electroplating technology, only need to remove described the first photoresist layer 204 and can form required conductive structure, and without through etching technics, guaranteed the stability of the conductive structure forming.
The material of described the first photoresist layer 204 comprises: propylene oxide ester, thermal curing agents, lithographic printing active component, photoactive component and additive; The formation technique of described the first photoresist layer 204 is: adopt Seed Layer 203 surfaces of spin coating proceeding in Seed Layer 203 surfaces and first opening 202 at dielectric layer 201 tops to form the first photoresist film; Adopt graphical described the first photoresist film of exposure technology, to remove in the first opening 202 and to be partly positioned at first photoresist film on Seed Layer 203 surfaces on dielectric layer 201, form the first photoresist layer 204.
Because described the first photoresist layer 204 forms by exposure technology, therefore form technique simple; And, because the material of described the first photoresist layer 204 is non-conductive photoresist, therefore in follow-up electroplating technology, the surface of described the first lithography layer 204 electric conducting material of can not growing, therefore the conductive structure of follow-up formation is only positioned at Seed Layer 203 surfaces of the first opening 202 and the second opening 205 bottoms, and can not form on the surface of the first photoresist layer 204; Therefore, the first photoresist layer 204 that is covered in 203 surfaces, Some Species sublayer can define position and the shape of the conductive structure of required formation, and after follow-up electroplating technology, the conductive structure forming, without through etching technics, has been avoided due to the etching of metal is caused to device performance stability problem; In addition, the formation technique of described the first photoresist layer 204 is simple, and removes technique easily and thoroughly, can not produce residually, further improves device performance.
Please refer to Figure 11, adopt electroplating technology at described the first opening 202(as shown in Figure 6) Seed Layer of inner bottom part 203 surfaces form conductive structures 206, and the top surface of described conductive structure 206 is less than or equal to the top surface of described the first photoresist layer 204.
Because the first photoresist layer 204 take non-conductive photoresist as material exposes the Seed Layer 203 of the first opening 202 bottoms, and the Seed Layer 203 on part dielectric layer 201 surfaces, therefore, in described electroplating technology process, only Seed Layer 203 surfaces of the first opening 202 and the second opening 205 bottoms, to the grown on top electric conducting material of described the second opening 205, form conductive structure 206; The electric conducting material and can not grow in described the first photoresist layer 204 surfaces and Seed Layer 203 surfaces that covered by described the first photoresist layer 204, therefore, after described electroplating technology, can form conductive structure 206 without carrying out etching technics, guarantee the stability of device.
In the present embodiment, the material of described conductive structure 206 is copper, and the formation technique of described conductive structure 206 is that copper is electroplated (ECP) technique; It should be noted that, because described conductive structure 206 is formed by electroplating technology, therefore the height of described conductive structure 206 is by the time of concrete electroplating technology, and the thickness of the first photoresist layer 204 determines, by controlling the time of electroplating technology with the conductive structure 206 of formation desired height, and the top of the conductive structure 206 forming can be higher than the top of described the first photoresist layer 204.
Please refer to Figure 12, forming after conductive structure 206, remove described the first photoresist layer 204(as shown in Figure 7).
The degumming process that the technique of described removal the first photoresist layer 204 is photoresist is well known to those skilled in the art, and therefore not to repeat here.The technique of described removal the first photoresist layer 204 is simple and remove thoroughly, can be at conductive structure 206 or Seed Layer 203 surface attachment accessory substances, and the device performance forming is stable.
Removing after the first photoresist layer 204, take described conductive structure 206 as mask, the Seed Layer 203 on dielectric layer 201 surfaces described in etching, until expose described dielectric layer 201; When the technique of the Seed Layer 203 on 201 surfaces of dielectric layer described in etching is as described in the first embodiment, therefore not to repeat here.
In the present embodiment, in the time of the Seed Layer 203 on 201 surfaces of dielectric layer described in etching, the drift angle at conductive structure 206 tops described in etching, and by controlling the direction of the gas ion bombardment in described etching technics, make described drift angle form fillet, thereby avoided the drift angle generation electric discharge phenomena at described conductive structure 206 tops.
The present embodiment forms the first photoresist layer 204 of the Seed Layer 203 that exposes the first opening 202 and part dielectric layer 201 surfaces on Seed Layer 203 surfaces, form the second opening 205; The Seed Layer surface of working as in described the first opening 202 and the second opening 205 bottoms forms conductive structure 206 by electroplating technology, because described the first photoresist layer 204 is non-conductive photoresist, therefore described the first photoresist layer 204 surfaces, and Seed Layer 203 surfaces that covered by described the first photoresist layer 204 can not form conductive structure 206; Therefore, the position of described conductive structure 206 and shape are defined by described the first photoresist layer 204, and after electroplating technology without through etching technics, thereby guaranteed that the pattern of the conductive structure 206 forming is accurate, stable performance; And the formation technique of described the first photoresist layer 204 is simple, and remove thoroughly, further improved the stability of the device that forms.
In sum, after forming Seed Layer, before forming the first photoresist layer, form on described Seed Layer surface the second photoresist layer that exposes the first opening, and the material of described the second photoresist layer is conduction photoresist; And described the first photoresist layer is formed at described the second photoresist layer surface; In the time adopting electroplating technology to form conductive structure on the Seed Layer surface of described the first open bottom, because the material of described the second photoresist layer is conduction photoresist, therefore in the Seed Layer superficial growth electric conducting material of the first open bottom, the sidewall surfaces of described the second photoresist layer electric conducting material of also can growing, thereby accelerate to form the speed of conductive structure, saved the process time; Secondly, because the top surface of described the second photoresist layer is covered by described the first photoresist layer, and the material of described the first photoresist layer is non-conductive photoresist, therefore in described electroplating technology, the top surface of described the second photoresist layer electric conducting material of can not growing, avoid after electroplating technology, carrying out again etching technics, and then avoided described etching technics to cause formed conductive structure deformation and made device performance unstable; And described the first photoresist layer and the second photoresist layer easily form and easily remove, and can not produce residual.
Having after the dielectric layer surface of the first opening and the sidewall of the first opening and lower surface formation Seed Layer, form the first photoresist layer on described Seed Layer surface, and described the first photoresist layer has the second opening that exposes the first opening; When adopt electroplating technology described first open with the second opening in after the conductive structure that forms, because described the first photoresist layer is non-conductive photoresist material, the top surface of described the first photoresist layer electric conducting material of can not growing, therefore described the first photoresist layer has defined position and the shape of the conductive structure forming, without formed conductive structure being carried out to etching after electroplating technology, the damage having avoided in etching process, device being caused, make device deformation or adhere to accessory substance at device surface; In addition, described the first photoresist layer easily forms and easily removes, and can not produce residual and simplification technique; The electric interconnection structure stable performance forming.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.

Claims (20)

1. a formation method for electric interconnection structure, is characterized in that, comprising:
Semiconductor substrate is provided, and described semiconductor substrate surface has dielectric layer, has the first opening that runs through its thickness in described dielectric layer;
Sidewall and lower surface at described dielectric layer surface and described the first opening form Seed Layer;
Form the second photoresist layer on described Seed Layer surface, the material of described the second photoresist layer is conduction photoresist, and in described the second photoresist layer, has the 3rd opening that runs through its thickness, and the bottom-exposed of described the 3rd opening goes out described the first opening;
Form the first photoresist layer on described the second photoresist layer surface, the material of described the first photoresist layer is non-conductive photoresist, and has the second opening that runs through its thickness in described the first photoresist layer, and described the second opening and the perforation of the 3rd opening;
Adopt electroplating technology to form conductive structure on the Seed Layer surface of described the first opening and the 3rd open bottom, the top surface of described conductive structure is less than or equal to the top surface of described the first photoresist layer;
Forming after conductive structure, remove described the second photoresist layer and the first photoresist layer.
2. the formation method of electric interconnection structure as claimed in claim 1, is characterized in that, described the 3rd opening is by forming described the second photoresist layer exposure; Described the second opening is by forming described the first photoresist layer exposure.
3. the formation method of electric interconnection structure as claimed in claim 1, is characterized in that, the conductivity of described the second photoresist layer is 10 -10siemens every centimetre ~ 10 -6every centimetre of Siemens, in the conduction photoetching glue material of described the second photoresist layer, contain propylene oxide ester, thermal curing agents, lithographic printing active component, photoactive component, additive and electric conductive polymer, described electric conductive polymer comprises: polyaniline, polypyrrole, one or more in polythiophene, polyphenylene vinylene, poly-diakyl fluorenes, polyaniline derivative, poly-plug fen derivative or nano composite polymer.
4. the formation method of electric interconnection structure as claimed in claim 1, is characterized in that, the material of described conductive structure is copper, and the formation technique of described conductive structure is copper electroplating technology.
5. the formation method of electric interconnection structure as claimed in claim 1, is characterized in that having conductive layer in the Semiconductor substrate of described the first open bottom, and described the first opening exposes described conductive layer, and the material of described conductive layer is copper, tungsten, aluminium or silver.
6. the formation method of electric interconnection structure as claimed in claim 1, it is characterized in that, also comprise: before forming Seed Layer, sidewall and lower surface at described dielectric layer surface and described the first opening form barrier layer, and the material on described barrier layer comprises tantalum, tantalum nitride, titanium, titanium nitride, copper manganese, copper aluminium, cobalt or lanthanum.
7. the formation method of electric interconnection structure as claimed in claim 1, is characterized in that, the material of described Seed Layer is copper, copper titanium or copper manganese, and formation technique is physical gas-phase deposition.
8. the formation method of electric interconnection structure as claimed in claim 1, is characterized in that, also comprises: after removing the first photoresist layer, take described conductive structure as mask, the Seed Layer on dielectric layer surface is until expose described dielectric layer described in etching.
9. the formation method of electric interconnection structure as claimed in claim 8, is characterized in that, in the time that the technique of the Seed Layer on dielectric layer surface described in etching is dry etching, etching gas comprises Cl 2and BCl 3in one or both, bias power is greater than 200 watts; In the time that the technique of the Seed Layer on dielectric layer surface described in etching is wet etching, etching liquid comprises H 2o 2with one or both in HCl.
10. the formation method of electric interconnection structure as claimed in claim 8, is characterized in that, in the time of the Seed Layer on dielectric layer surface described in etching, the drift angle at conductive structure top, makes described drift angle form fillet described in etching.
The formation method of 11. 1 kinds of electric interconnection structures, is characterized in that, comprising:
Semiconductor substrate is provided, and described semiconductor substrate surface has dielectric layer, has the first opening that runs through its thickness in described dielectric layer;
Sidewall and lower surface at described dielectric layer surface and described the first opening form Seed Layer;
Form the first photoresist layer on described Seed Layer surface, the material of described the first photoresist layer is non-conductive photoresist, and has the second opening that runs through its thickness in described the first photoresist layer, and described the second open bottom exposes described the first opening;
Adopt electroplating technology to form conductive structure on the Seed Layer surface of described the first opening inner bottom part, the top surface of described conductive structure is less than or equal to the top surface of described the first photoresist layer;
Forming after conductive structure, remove described the first photoresist layer.
The 12. formation methods of electric interconnection structure as claimed in claim 11, is characterized in that, described the second opening is by forming described the first photoresist layer exposure.
The 13. formation methods of electric interconnection structure as claimed in claim 11, is characterized in that, the material of described conductive structure is copper, and the formation technique of described conductive structure is copper electroplating technology.
The 14. formation methods of electric interconnection structure as claimed in claim 11, is characterized in that having conductive layer in the Semiconductor substrate of described the first open bottom, and described the first opening exposes described conductive layer, and the material of described conductive layer is copper, tungsten, aluminium or silver.
The 15. formation methods of electric interconnection structure as claimed in claim 11, it is characterized in that, also comprise: before forming Seed Layer, sidewall and lower surface at described dielectric layer surface and described the first opening form barrier layer, and the material on described barrier layer comprises tantalum, tantalum nitride, titanium, titanium nitride, copper manganese, copper aluminium, cobalt or lanthanum.
The 16. formation methods of electric interconnection structure as claimed in claim 11, is characterized in that, the material of described Seed Layer is copper, copper titanium or copper manganese, and formation technique is physical gas-phase deposition.
The 17. formation methods of electric interconnection structure as claimed in claim 11, is characterized in that, also comprise: after removing the first photoresist layer, take described conductive structure as mask, the Seed Layer on dielectric layer surface is until expose described dielectric layer described in etching.
The 18. formation methods of electric interconnection structure as claimed in claim 17, is characterized in that, in the time that the technique of the Seed Layer on dielectric layer surface described in etching is dry etching, etching gas comprises Cl 2and BCl 3in one or both, bias power is greater than 200 watts; In the time that the technique of the Seed Layer on dielectric layer surface described in etching is wet etching, etching liquid comprises H 2o 2with one or both in HCl.
The 19. formation methods of electric interconnection structure as claimed in claim 17, is characterized in that, in the time of the Seed Layer on dielectric layer surface described in etching, the drift angle at conductive structure top, makes described drift angle form fillet described in etching.
The 20. formation methods of electric interconnection structure as claimed in claim 11, is characterized in that, the material of described the first photoresist layer or described the second photoresist layer comprises: propylene oxide ester, thermal curing agents, lithographic printing active component, photoactive component and additive.
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