CN109216321A - Semiconductor devices and forming method thereof with plug - Google Patents
Semiconductor devices and forming method thereof with plug Download PDFInfo
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- CN109216321A CN109216321A CN201710537017.4A CN201710537017A CN109216321A CN 109216321 A CN109216321 A CN 109216321A CN 201710537017 A CN201710537017 A CN 201710537017A CN 109216321 A CN109216321 A CN 109216321A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 87
- 238000000034 method Methods 0.000 title claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 104
- 239000002184 metal Substances 0.000 claims abstract description 104
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 238000011049 filling Methods 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims description 45
- 239000007769 metal material Substances 0.000 claims description 37
- 229910021332 silicide Inorganic materials 0.000 claims description 31
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 31
- 230000005669 field effect Effects 0.000 claims description 14
- 229910008486 TiSix Inorganic materials 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
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- 230000000694 effects Effects 0.000 description 3
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- 229910002601 GaN Inorganic materials 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
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- 229910052733 gallium Inorganic materials 0.000 description 2
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical group [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
Abstract
A kind of semiconductor devices and forming method thereof with plug, the device include: semiconductor substrate, are formed in semiconductor substrate to electrical connecting element；Dielectric layer in semiconductor substrate is formed with the through-hole exposed to electrical connecting element in dielectric layer；Conductive layer in through-hole, covers the side wall of through-hole and to electrical connecting element, and is formed fluted, and the upper surface of conductive layer is lower than the opening of through-hole；Filling through-hole and the metal layer for covering conductive layer.Has reeded conductive layer by being formed in the lower end of through-hole, so that the upper end side wall of through-hole and the surface of conductive layer surround hole wide at the top and narrow at the bottom, thus improve the ability of metal layer filling through-hole, so that plug is not easy the defects of forming cavity, gap.So, the excessively high problem of plug resistance value is not only avoided, and avoids the lapping liquid being used to form in the chemical mechanical milling tech of plug and remains in the cavity of plug, gap internal corrosion plug, thus the problem of influencing semiconductor device reliability.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of with the semiconductor devices of plug and its formation side
Method.
Background technique
As shown in Figure 1, transistor includes semiconductor substrate 1, the grid 2 in semiconductor substrate 1, source electrode 3 and drain electrode
4, source electrode 3, drain electrode 4 are located in the semiconductor substrate 1 of 2 two sides of grid.Interlayer dielectric layer 5 covers on semiconductor substrate 1,
And it is formed with the through-hole 6 for exposing source electrode 3, drain electrode 4, by forming the gold for covering the upper surface of interlayer dielectric layer 5 and filling through-hole 6
Belong to layer and chemical mechanical grinding then is carried out to the metal layer, the plug 7 being electrically connected with source electrode 3, drain electrode 4 can be formed.
As integrated circuit technology node constantly reduces, the size of through-hole 6 is smaller and smaller, the ability of filling hole with metal 6
Worse and worse, thus in plug 7 it is easy to form cavity, gap the defects of.Cavity, gap in plug 7 not only result in plug 7
Resistance value it is high, moreover, when cavity, gap are formed in the upper surface of plug 7, for forming the chemical mechanical grinding work of plug 7
Lapping liquid in skill can remain in the cavity of plug 7, in gap, and gradually corrode plug 7, so that influence semiconductor devices can
By property.
Summary of the invention
The technical problem to be solved in the present invention: the plug in existing semiconductor devices easily forms the defects of cavity, gap, no
The resistance value for only resulting in plug is high, and is used to form the lapping liquid in the chemical mechanical milling tech of plug and easily remains in plug
In cavity, gap, and gradually corrode plug, to influence the reliability of semiconductor devices.
To solve the above-mentioned problems, An embodiment provides a kind of semiconductor devices with plug,
Include: semiconductor substrate, is formed in the semiconductor substrate to electrical connecting element；Dielectric in the semiconductor substrate
Layer, it is formed in the dielectric layer and exposes the through-hole to electrical connecting element；Conductive layer in the through-hole covers institute
The side wall of through-hole and described to electrical connecting element is stated, and is formed fluted, the upper surface of the conductive layer is lower than the through-hole
Opening；It fills the through-hole and covers the metal layer of the conductive layer.
Optionally, the ratio between the height of the conductive layer and the depth of the through-hole are 1:5 to 1:2.
Optionally, the conductive layer includes:
The covering metal silicide layer to electrical connecting element；
The metal material layer of the bottom side of the wall of the through-hole is covered, described in the metal material layer is used to generate with pasc reaction
Metal silicide layer.
Optionally, the metal silicide layer includes TiSix, the metal material layer includes Ti layers and being covered on the Ti
TiN layer on layer.
Optionally, the metal layer includes tungsten.
Optionally, the plug is contact plunger.
Optionally, the source electrode and/or drain electrode to electrical connecting element for transistor.
Optionally, the transistor is fin formula field effect transistor.
Optionally, the fin formula field effect transistor includes fin and gate structure, and the gate structure is located at the fin
On portion, the source electrode, drain electrode include the groove being located in the fin and the semiconductor material being filled in the groove.
To solve the above-mentioned problems, another embodiment of the present invention provides a kind of semiconductor devices with plug
Forming method comprising: semiconductor substrate is provided, is formed in the semiconductor substrate to electrical connecting element；It is partly led described
Dielectric layer is formed in body substrate, is formed in the dielectric layer and is exposed the through-hole to electrical connecting element；In the through-hole
Form conductive layer, the conductive layer covers the side wall of the through-hole and described to electrical connecting element, and formed it is fluted, it is described
The upper surface of conductive layer is lower than the opening of the through-hole；Metal layer is filled into the through-hole to form the plug, the gold
Belong to layer and covers the conductive layer.
Optionally, the ratio between the height of the conductive layer and the depth of the through-hole are 1:5 to 1:2.
Optionally, the forming method of the conductive layer includes:
Form the entire side wall and the gold to electrical connecting element of the upper surface, the through-hole that cover the dielectric layer
Belong to material layer；
It anneals, so as to cover the part to electrical connecting element in the metal material layer with described wait be electrically connected
Element reaction generates metal silicide layer；
After carrying out the annealing, sacrificial layer of the surface lower than the opening of the through-hole is formed, the sacrificial layer covers institute
State the metal material layer in the bottom side of the wall of metal silicide layer and the through-hole；
Remove the metal material layer not covered by the sacrificial layer；
Remove the sacrificial layer.
Optionally, the metal material layer includes Ti layers and the TiN layer that is covered on the Ti layer, the metal silicide
Layer includes TiSix。
Optionally, the forming method of the sacrificial layer includes:
It is formed and covers the metal material layer, the metal silicide layer and the sacrificial material layer for filling the through-hole；
The sacrificial material layer carve, it is remaining to be only filled in the sacrificial of the through-hole lower end after described time is carved
Domestic animal material layer constitutes the sacrificial layer.
Optionally, the sacrificial layer is BARC layer or ODL layers.
Optionally, the metal layer includes tungsten.
Optionally, the plug is contact plunger.
Optionally, the source electrode and/or drain electrode to electrical connecting element for transistor.
Optionally, the transistor is fin formula field effect transistor.
Optionally, the fin formula field effect transistor includes fin and gate structure, and the gate structure is located at the fin
On portion, the source electrode, drain electrode include the groove being located in the fin and the semiconductor material being filled in the groove.
In the inventive solutions, it is electrically connected with to electrical connecting element with being formed filling metal layer into through-hole
Before plug, is formed in the lower end of through-hole and have reeded conductive layer, so that the upper end side wall of through-hole and the surface of conductive layer
Hole wide at the top and narrow at the bottom is surrounded, thus improves the ability of metal layer filling through-hole, so as to be not easy to be formed cavity, gap etc. scarce for plug
It falls into.So, the excessively high problem of plug resistance value is not only avoided, and avoids the chemical mechanical grinding for being used to form plug
Lapping liquid in technique remains in the cavity of plug, gap internal corrosion plug, thus the problem of influencing semiconductor device reliability.
By referring to the drawings to the detailed description of exemplary embodiment of the present invention, other feature of the invention, side
Face and its advantage will become apparent.
Detailed description of the invention
Attached drawing forms part of this specification, and which depict exemplary embodiment of the present invention, and together with specification
Principle for explaining the present invention together, in the accompanying drawings:
Fig. 1 is a kind of diagrammatic cross-section of existing semiconductor devices with plug；
Fig. 2 is the production flow diagram of the semiconductor devices in one embodiment of the present of invention with plug；
Fig. 3 to Figure 16 is semiconductor devices the cuing open in each production phase in one embodiment of the present of invention with plug
Face schematic diagram.
Specific embodiment
As previously mentioned, the plug in existing semiconductor devices easily forms the defects of cavity, gap, the resistance of plug is not only resulted in
Value is high, and is used to form the lapping liquid in the chemical mechanical milling tech of plug and easily remains in the cavity of plug, in gap, and
Gradually corrode plug, to influence the reliability of semiconductor devices.
In order to solve this problem, the invention proposes a kind of improved plans, are filling metal layer into through-hole with shape
Before the plug being electrically connected with to electrical connecting element, is formed in the lower end of through-hole and have reeded conductive layer, so that through-hole
The surface of upper end side wall and conductive layer surrounds hole wide at the top and narrow at the bottom, thus improves the ability of metal layer filling through-hole, so that
Plug is not easy the defects of forming cavity, gap.So, the excessively high problem of plug resistance value is not only avoided, and is avoided
The lapping liquid being used to form in the chemical mechanical milling tech of plug remains in the cavity of plug, gap internal corrosion plug, thus
The problem of influencing semiconductor device reliability.
Carry out the various exemplary embodiments of detailed description of the present invention now with reference to attached drawing.It should be understood that unless in addition specific
Illustrate, the component and the positioned opposite of step, numerical expression and numerical value otherwise illustrated in these embodiments is not understood that
For limitation of the scope of the invention.
In addition, it should be understood that for ease of description, the size of all parts shown in attached drawing is not necessarily according to reality
The proportionate relationship on border is drawn, such as certain layers of thickness or width can be exaggerated relative to other layers.
The description of exemplary embodiment is merely illustrative below, in any sense all not as to the present invention and
Its any restrictions applied or used.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of these technologies, method and apparatus, these technologies, method and apparatus should be considered as a part of this specification.
It should be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined or illustrates in attached drawing, then will not need that it is further discussed in the explanation of subsequent attached drawing.
Detailed Jie is below with reference to production method of the Fig. 2 to Figure 16 to the semiconductor devices with plug of the present embodiment
It continues.
Firstly, with reference to Fig. 3, execute the step S1 in Fig. 2, semiconductor substrate 1 be provided, be formed in semiconductor substrate 1 to
Electrical connecting element.It is described to be used to be electrically connected with the subsequent plug formed above to electrical connecting element to electrical connecting element, pass through
The plug can apply electric signal to electrical connecting element to described, so that semiconductor devices be driven to work.
In the present embodiment, transistor 2, transistor 3 are formed in semiconductor substrate 1, wherein transistor 2 is NMOS brilliant
Body pipe, and it is located at the NMOS area of semiconductor substrate 1, transistor 3 is PMOS transistor, and is located at the area PMOS of semiconductor substrate 1.
The source S 1 of transistor 2, the source S 2 of drain D 1 and transistor 3, drain D 2 are described to electrical connecting element, it is described to
Electrical connecting element is electrically connected with the subsequent plug formed above, by the plug can to source S 1, drain D 1, source S 2,
Drain D 2 applies electric signal, so that transistor 2, transistor 3 be driven to work.
Semiconductor substrate 1 can for monocrystalline substrate, multicrystalline silicon substrate, amorphous silicon substrate, germanium silicon substrate, carbon silicon substrate,
Silicon-on-insulator substrate, germanium substrate on insulator, glass substrate, III-V compound substrate (such as gallium nitride substrate or arsenic
Change gallium substrate etc.) etc. substrates.
Transistor 2 is fin formula field effect transistor, and the gate structure G1 including fin 20, on fin 20, with
And source S 1, drain D 1 positioned at the two sides gate structure G1.Further, gate structure G1 includes metal gates 21, metal gate
Cap layer 22 on pole 21, and the side wall (not identifying) being covered on around metal gates 21 and cap layer 22, metal gates
21 can be single-layer metal or metal laminated, and the side wall can be single-layer or multi-layer.Source S 1, drain D 1 include being located at fin
Groove (not identifying) in portion 20 and the semiconductor material (not identifying) being filled in the groove, the semiconductor material can
It is filled in a manner of through epitaxial growth in the groove.In a particular embodiment, the semiconductor material selects SiC, with
Apply stress to the channel of NMOS transistor to improve the carrier mobility of transistor.Further, source S 1, drain D 1
It is set as the source/drain (surface that the top for the source/drain being lifted exceeds fin 20) of lifting, to improve NMOS transistor
Performance.
Transistor 3 is fin formula field effect transistor, and the gate structure G2 including fin 30, on fin 30, with
And source S 2, drain D 2 positioned at the two sides gate structure G2.Further, gate structure G2 includes metal gates 31, metal gate
Cap layer 32 on pole 31, and the side wall (not identifying) being covered on around metal gates 31 and cap layer 32, metal gates
31 can be single-layer metal or metal laminated, and the side wall can be single-layer or multi-layer.Source S 2, drain D 2 include being located at fin
Groove (not identifying) in portion 30 and the semiconductor material (not identifying) being filled in the groove, the groove can be set
For ∑ type (illustrating in figure) or rectangle, the semiconductor material can be filled in the groove by way of epitaxial growth.
In a particular embodiment, the semiconductor material selects SiGe, to apply stress to the channel of PMOS transistor to improve crystalline substance
The carrier mobility of body pipe.Further, source S 2, drain D 2 are also configured as the source/drain (source/drain being lifted of lifting
The top of pole exceeds the surface of fin 30), to improve the performance of PMOS transistor.
It should be noted that in the inventive solutions, the type of transistor should not be limited to fin field effect crystalline substance
Body pipe can be adapted for any kind of transistor, such as MOS transistor.In the alternative of the present embodiment, semiconductor substrate
PMOS transistor, one in NMOS transistor can be simply formed on 1.
Then, with continued reference to Fig. 3, the step S2 in Fig. 2 is executed, forms dielectric layer on semiconductor substrate 1.
In the present embodiment, the dielectric layer includes the first dielectric layer 40, second Jie on the first dielectric layer 40
Electric layer 42 and the third dielectric layer 43 on the second dielectric layer 42, wherein the first dielectric layer 40, the second dielectric layer 42 are filled out
Fill the gap between transistor 2 and transistor 3, the top of the upper surface of the second dielectric layer 42 and gate structure G1, gate structure G2
Portion flushes.
In a preferred embodiment, the first dielectric layer 40 selects the lesser insulating materials of hardness, to obtain better fillibility
Energy.Second dielectric layer 42 selects the biggish insulating materials of hardness, preferably to carry out flatening process to the second dielectric layer 42, from
And flush the surface of the second dielectric layer 42 with the surface of gate structure G1, gate structure G2.In the present embodiment, the first dielectric
Layer 40 and the second dielectric layer 42 select identical material (such as silica), but the manufacture craft of the two is different, different to obtain
Hardness.In the alternative of the present embodiment, the first dielectric layer 40 and the second dielectric layer 42 can select identical material.
Third dielectric layer 43 can select material identical with the first dielectric layer 40, the second dielectric layer 42, can also select
The material different from the first dielectric layer 40, the second dielectric layer 42.In the present embodiment, third dielectric layer 43 is silica.
It should be noted that although in the technical scheme of this embodiment, the dielectric layer is that laminated construction (includes two layers
The dielectric layer of above stacking), but in other embodiments, the dielectric layer may be single layer structure.
In a preferred embodiment, contact hole etching barrier layer is formed between the first dielectric layer 40 and the second dielectric layer 42
41, a part on contact hole etching barrier layer 41 be covered in the side wall, source S 1, drain D 1, source S 2 and drain D 2 it
On.In a particular embodiment, the material on contact hole etching barrier layer 41 is silicon nitride.
Then, with reference to Fig. 4, the step S3 in Fig. 2 is executed, is formed in the dielectric layer described in exposing to electrical connecting element
Through-hole.
In the present embodiment, it is formed and is exposed respectively as described to electrical connecting element in the dielectric layer of NMOS area
Two through-hole C1 of source S 1, drain D 1, and formed and exposed respectively as described to electricity in the dielectric layer in the area PMOS
Two through-hole C2 of the source S 2 of connecting element, drain D 2, through-hole C1, through-hole C2 at least run through Jie of third dielectric layer 43, second
Electric layer 42 and contact hole etching barrier layer 41, and as contact hole.
In a particular embodiment, through-hole C1, through-hole C2 forming method include: to be formed in the upper surface of third dielectric layer 43
Patterned photoresist layer (not shown)；It is performed etching using the patterned photoresist layer as exposure mask, until exposing source S 1,
Drain D 1, source S 2 and drain D 2, the etching can be dry etching；Then, the patterned photoresist layer is removed.
Then, with reference to Fig. 5 to Fig. 8, the step S4 in Fig. 2 is executed, is formed in the dielectric layer and exposes cap layer 22
Through-hole C3 and expose cap layer 32 through-hole C4, through-hole C3, through-hole C4 run through third dielectric layer 43, subsequently through to through-hole C3,
Filling metal can form plug to be electrically connected with metal gates 21, metal gates 31 in through-hole C4, by with metal gates
21, the plug that metal gates 31 are electrically connected applies electric signal, transistor can be driven to work.
In the present embodiment, through-hole C3, through-hole C4 forming method include:
As shown in figure 5, forming the upper surface of covering third dielectric layer 43 and filling the BARC of through-hole C1, through-hole C2
(Bottom Anti-reflective Coating, bottom antireflective coating) layer 44a, due to BARC layer 44a good fluidity, therefore
Sufficiently through-hole C1, through-hole C2 can not only be filled up, additionally it is possible to even curface is obtained, in the alternative of the present embodiment, BARC
Layer 44a could alternatively be ODL (Organic Dielectric Layer, organic dielectric layer) layer, and ODL layers have and BARC layer
The identical technical effect of 44a；
With continued reference to shown in Fig. 5, forming patterned photoresist layer 45, patterned photoresist layer on BARC layer 44a
45 are formed with the first opening 450 in the position of corresponding metal gates 21, metal gates 31, and the first opening 450 is for defining and gold
Belong to the position of grid 21, the plug that metal gates 31 are electrically connected；
In conjunction with shown in Fig. 5 to Fig. 6, with patterned photoresist layer 45 be exposure mask BARC layer 44a is performed etching, with
The position of corresponding first opening 450 forms the second opening (not identifying) in BARC layer 44a, to form patterned BARC layer
44, in a particular embodiment, which is dry etching；
As shown in fig. 7, being performed etching with patterned photoresist layer 45 and patterned BARC layer 44 for exposure mask, until dew
Cap layer 22, cap layer 32 out, to form through-hole C3, through-hole C4, in a particular embodiment, which is dry etching；
In conjunction with shown in Fig. 7 to Fig. 8, patterned photoresist layer 45 and patterned BARC layer 44 are removed, is being embodied
In example, the minimizing technology of patterned photoresist layer 45 and patterned BARC layer 44 is cineration technics, the removal of cineration technics
Ability is strong, and very small to the damage of semiconductor devices, which can be by patterned photoresist layer 45 and patterned BARC
44 clean removal of layer, the patterned BARC layer 44 for being difficult to remove including through-hole C1, the bottom through-hole C2.
Then, refering to what is shown in Fig. 9, executing the step S5 in Fig. 2, metal material layer 5a, metal material layer 5a covering are formed
The upper surface of third dielectric layer 43 in the dielectric layer, the side wall of entire through-hole C1, C2, C3, C4, as described to electrical connection element
Source S 1, the drain D 1 of part, and as the source S 2 to electrical connecting element, drain D 2.Metal material layer 5a is used for
Metal silicide layer is generated with pasc reaction in subsequent step S6.
In a particular embodiment, metal material layer 5a includes Ti layers and the TiN layer on Ti layer.But it should be noted
It is that in the inventive solutions, the material of metal material layer 5a should not be limited to this, can also is Co, Ni, Pt etc.
It is used to form the metal material of metal silicide.
Then, it refering to what is shown in Fig. 10, executing the step S6 in Fig. 2, anneals, makees so as to be covered in metal material layer 5a
For the source S 1 to electrical connecting element, drain D 1, and as the portion of the source S 2 to electrical connecting element, drain D 2
Point, it is reacted with source S 1, drain D 1, source S 2, drain D 2 and generates metal silicide layer 6, and its remaining part of metal material layer 5a
Divide and unreacted generates metal silicide layer 6.
In the present embodiment, metal silicide layer 6 is TiSix, TiSixWith lower schottky barrier height (SBH),
It thus being capable of the significantly more contact resistance for reducing source S 1, drain D 1, source S 2, drain D 2.
In the present embodiment, described to be annealed into laser annealing.
Then, with reference to figures 11 to Figure 12, the step S7 in Fig. 2 is executed, forms opening of the surface lower than through-hole C1, through-hole C2
Sacrificial layer 7, sacrificial layer 7 cover through-hole C1 in metal silicide layer 6 and through-hole C1 bottom side of the wall on metal material layer 5a,
And the metal material layer 5a on the metal silicide layer 6 and through-hole C2 bottom side of the wall in covering through-hole C2.
In the present embodiment, the forming method of sacrificial layer 7 includes: as shown in figure 11, to form covering metal material layer 5a simultaneously
Fill the sacrificial material layer 7a of through-hole C1, C2, C3；In conjunction with shown in Figure 11 to Figure 12, sacrificial material layer 7a carve, returns and carves
Later, the remaining sacrificial material layer 7a being only filled in the bottom through-hole C1, C2 constitutes sacrificial layer 7.
In the present embodiment, sacrificial layer 7 is BARC (Bottom Anti-reflective Coating, bottom anti-reflective
Coating) layer, have the advantages that good fluidity, thus can sufficiently fill up through-hole C1, through-hole C2, C3, in addition, in subsequent step
It is easy to remove the sacrificial layer 7 for being located at the bottom through-hole C1, C2 completely in S10.In the alternative of the present embodiment, sacrificial layer 7
It may be ODL (Organic Dielectric Layer, organic dielectric layer) layer, there is technology identical with BARC layer effect
Fruit.
In the present embodiment, sacrificial material layer 7a carve using the technique for forming sacrificial layer 7 as cineration technics, work
Skill parameter includes: CH4Flow be 10SCCM to 100SCCM, H2Flow be 100SCCM to 1000SCCM, N2Flow be
20SCCM to 200SCCM, pressure be 5mtorr to 150mtorr, radio-frequency power be 500W to 2000W, bias voltage be 50V extremely
300V, temperature are 25 DEG C to 80 DEG C, and the time is 20S to 1000S.
Then, referring to figs 12 to Figure 13, the step S8 in Fig. 2 is executed, removal is not sacrificed the metal material layer of the covering of layer 7
5a, i.e. removal are covered on the upper surface of third dielectric layer 43, and are covered on the side wall of the upper end through-hole C1, C2 and cover and is logical
The side wall of hole C3, C4 and the metal material layer 5a of bottom, the metal material in the remaining bottom side of the wall for being covered on through-hole C1, C2
The metal silicide layer 6 of the bottom 5 and through-hole C1, C2 of layer is used to form the generally U-shaped conduction with groove (not identifying)
Layer E.
By above-mentioned steps it is found that the effect of sacrificial layer 7 includes: (horizontal i.e. in figure for defining the height H of conductive layer E
Size on direction), and make the upper surface (surface where the highest point of conductive layer 5) of conductive layer E lower than through-hole C1, C2
Opening.
In the present embodiment, the method that removal is not sacrificed the metal material layer 5a of the covering of layer 7 is wet etching, to reduce
It is damaged caused by semiconductor devices in etching process.Further, etching agent is SC1 solution, and technological parameter includes: temperature
It is 25 DEG C to 80 DEG C, the volume ratio of each ingredient is NH4OH:H2O2:H20=1:(1~10 in SC1 solution): (4~200).
Then, with reference to figures 13 to Figure 14, the step S9 in Fig. 2, the cap layer exposed below removal through-hole C3, C4 are executed
22,32, to expose metal gates 21,31.
In the present embodiment, the minimizing technology for the cap layer 22,32 exposed below through-hole C3, C4 is dry etching, this is dry
The technological parameter of method etching includes: CH2F2Flow be 8SCCM to 50SCCM, O2Flow be 2SCCM to 30SCCM, CF4's
Flow is 30SCCM to 200SCCM, and pressure is 10mTorr to 2000mTorr, and radio-frequency power is 100W to 1000W, Dc bias
For 30V to 500V, the time is 4S to 500S.
During cap layer 22,32 exposed below dry etching through-hole C3, C4, exposure mask is not necessarily formed, is directly carried out
Etching.During dry etching, the sacrificial layer 7 in through-hole C1, C2 is used to that the metal silicide layer 6 of lower section to be protected not to be damaged
Wound.In consideration of it, the height (size i.e. in figure in horizontal direction) of sacrificial layer 7 cannot be too small.
Then, with reference to figs. 14 to Figure 15, the step S10 in Fig. 2 is executed, removes sacrificial layer 7.
In the present embodiment, the minimizing technology of sacrificial layer 7 is ashing, can include angle by each position in through-hole C1, C2
The sacrificial layer 7 fallen removes completely.
Further, the parameter of the cineration technics includes: N2Flow be 2000SCCM to 8000SCCM, H2Flow be
500SCCM to 2000SCCM, pressure are 200mTorr to 900mTorr, and radio-frequency power is 1000W to 2700W, and temperature is 180 DEG C
To 450 DEG C.
Finally, executing the step S11 in Fig. 2 with reference to Figure 16, metal layer 8 is filled into through-hole C1, C2, C3, C4 to be formed
Plug P1, P2, P3, P4, wherein two plug P1 contact electrical connection, two plugs with the source S 1 of NMOS area, drain D 1 respectively
P2 contacts electrical connection with the source S 2 in the area PMOS, drain D 2 respectively, and plug P3 contacts electrical connection with the metal gates 21 of NMOS area,
Plug P4 contacts electrical connection with the metal gates 31 in the area PMOS, therefore plug P1, P2, P3, P4 are also referred to as contact plunger.
In the present embodiment, the forming method of plug P1, P2, P3, P4 includes: the upper table to form covering third dielectric layer 43
Face and the metal layer for filling through-hole C1, C2, C3, C4；Chemical mechanical grinding (CMP) is carried out until exposing the upper of third dielectric layer 43
Surface, after chemical mechanical grinding, the metal layer beyond 43 upper surface of third dielectric layer is removed.
Further, in the present embodiment, formed covering third dielectric layer 43 upper surface and fill through-hole C1, C2,
Before the metal layer of C3, C4, adhering layer (not shown) at least is formed on the surface of through-hole C1, C2, C3, C4, which is used for
The adhesive ability for improving through-hole C1, C2, C3, C4 inner metal layer, prevents the metal layer of through-hole C1, C2, C3, C4 from peeling off.Specific
In embodiment, metal layer 8 is tungsten (W), which is TiN.In the alternative of the present embodiment, metal layer 8 can also be selected
Other are suitable as the metal of plug.
Since the bottom of through-hole C1, C2 are formed with conductive layer E with groove and generally U-shaped, therefore the upper end of through-hole C1
The surface of side wall and conductive layer E define hole wide at the top and narrow at the bottom, and the upper end side wall of through-hole C2 and the surface of conductive layer E surround
Hole wide at the top and narrow at the bottom so when forming plug P1, P2, improves the ability that metal layer 8 fills through-hole C1, C2, subtracts
The possibility for the defects of cavity, gap are formed in small plug P1, P2, and then the resistance value for reducing plug P1, P2 is high, and is used for
The lapping liquid formed in the chemical mechanical milling tech of plug P1, P2 remains in the cavity of plug P1, P2, in gap, and gradually
Corrode the possibility of plug P1, P2.
It can be seen that in the technical scheme of this embodiment, forming shape in the source electrode of transistor, drain electrode it makes use of existing
Conductive layer E is formed to reduce the technique of contact resistance at metal silicide, to simplify manufacturing process, saves and is produced into
This.
In order to improve the ability that metal layer 8 fills through-hole C1, C2 as far as possible, the height of conductive layer E cannot be too big.And it is another
Aspect, according to noted earlier it is found that as shown in figure 14, the height of conductive layer E determines by the height of sacrificial layer 7, and sacrificial layer 7
Height cannot the too small metal silicide layer 6 to protect lower section, therefore the height of conductive layer E cannot be too small.It is found through numerous studies,
It, can be in the energy of the filling of metal layer 8 through-hole C1, C2 when the ratio between the height of conductive layer E and the depth of through-hole C1, C2 are 1:5 to 1:2
Preferable balance is obtained between power, and the ability of protection metal silicide layer 6.
In addition, the present embodiment additionally provides a kind of semiconductor devices with plug, the semiconductor device with reference to shown in Figure 16
Part includes semiconductor substrate 1, is formed in semiconductor substrate 1 to electrical connecting element.
It is described to be used to be electrically connected with the subsequent plug formed above to electrical connecting element to electrical connecting element, it is inserted by this
Plug can apply electric signal to electrical connecting element to described, so that semiconductor devices be driven to work.
In the present embodiment, transistor 2, transistor 3 are formed in semiconductor substrate 1, wherein transistor 2 is NMOS brilliant
Body pipe, and it is located at the NMOS area of semiconductor substrate 1, transistor 3 is PMOS transistor, and is located at the area PMOS of semiconductor substrate 1.
The source S 1 of transistor 2, the source S 2 of drain D 1 and transistor 3, drain D 2 are described to electrical connecting element, it is described to
Electrical connecting element is electrically connected with the subsequent plug formed above, by the plug can to source S 1, drain D 1, source S 2,
Drain D 2 applies electric signal, so that transistor 2, transistor 3 be driven to work.
Semiconductor substrate 1 can for monocrystalline substrate, multicrystalline silicon substrate, amorphous silicon substrate, germanium silicon substrate, carbon silicon substrate,
Silicon-on-insulator substrate, germanium substrate on insulator, glass substrate, III-V compound substrate (such as gallium nitride substrate or arsenic
Change gallium substrate etc.) etc. substrates.
Transistor 2 is fin formula field effect transistor, and the gate structure G1 including fin 20, on fin 20, with
And source S 1, drain D 1 positioned at the two sides gate structure G1.Further, gate structure G1 includes metal gates 21, metal gate
Cap layer 22 on pole 21, and the side wall (not identifying) being covered on around metal gates 21 and cap layer 22, metal gates
21 can be single-layer metal or metal laminated, and the side wall can be single-layer or multi-layer.Source S 1, drain D 1 include being located at fin
Groove (not identifying) in portion 20 and the semiconductor material (not identifying) being filled in the groove, the semiconductor material can
It is filled in a manner of through epitaxial growth in the groove.In a particular embodiment, the semiconductor material selects SiC, with
Apply stress to the channel of NMOS transistor to improve the carrier mobility of transistor.Further, source S 1, drain D 1
It is set as the source/drain (surface that the top for the source/drain being lifted exceeds fin 20) of lifting, to improve NMOS transistor
Performance.
Transistor 3 is fin formula field effect transistor, and the gate structure G2 including fin 30, on fin 30, with
And source S 2, drain D 2 positioned at the two sides gate structure G2.Further, gate structure G2 includes metal gates 31, metal gate
Cap layer 32 on pole 31, and the side wall (not identifying) being covered on around metal gates 31 and cap layer 32, metal gates
31 can be single-layer metal or metal laminated, and the side wall can be single-layer or multi-layer.Source S 2, drain D 2 include being located at fin
Groove (not identifying) in portion 30 and the semiconductor material (not identifying) being filled in the groove, the groove can be set
For ∑ type (illustrating in figure) or rectangle, the semiconductor material can be filled in the groove by way of epitaxial growth.
In a particular embodiment, the semiconductor material selects SiGe, to apply stress to the channel of PMOS transistor to improve crystalline substance
The carrier mobility of body pipe.Further, source S 2, drain D 2 are also configured as the source/drain (source/drain being lifted of lifting
The top of pole exceeds the surface of fin 30), to improve the performance of PMOS transistor.
It should be noted that in the inventive solutions, the type of transistor should not be limited to fin field effect crystalline substance
Body pipe can be adapted for any kind of transistor, such as MOS transistor.In the alternative of the present embodiment, semiconductor substrate
PMOS transistor, one in NMOS transistor can be simply formed on 1.
Dielectric layer is formed in semiconductor substrate 1.In the present embodiment, the dielectric layer includes the first dielectric layer 40, position
The second dielectric layer 42 on the first dielectric layer 40 and the third dielectric layer 43 on the second dielectric layer 42, wherein
Gap between first dielectric layer 40, the second dielectric layer 42 filling transistor 2 and transistor 3, the upper surface of the second dielectric layer 42
It is flushed at the top of gate structure G1, gate structure G2.
In a preferred embodiment, the first dielectric layer 40 selects the lesser insulating materials of hardness, to obtain better fillibility
Energy.Second dielectric layer 42 selects the biggish insulating materials of hardness, preferably to carry out flatening process to the second dielectric layer 42, from
And flush the surface of the second dielectric layer 42 with the surface of gate structure G1, gate structure G2.In the present embodiment, the first dielectric
Layer 40 and the second dielectric layer 42 select identical material (such as silica), but the manufacture craft of the two is different, different to obtain
Hardness.In the alternative of the present embodiment, the first dielectric layer 40 and the second dielectric layer 42 can select identical material.
Third dielectric layer 43 can select material identical with the first dielectric layer 40, the second dielectric layer 42, can also select
The material different from the first dielectric layer 40, the second dielectric layer 42.In the present embodiment, third dielectric layer 43 is silica.
It should be noted that although in the technical scheme of this embodiment, the dielectric layer is that laminated construction (includes two layers
The dielectric layer of above stacking), but in other embodiments, the dielectric layer may be single layer structure.
In a preferred embodiment, contact hole etching barrier layer is formed between the first dielectric layer 40 and the second dielectric layer 42
41, a part on contact hole etching barrier layer 41 be covered in the side wall, source S 1, drain D 1, source S 2 and drain D 2 it
On.In a particular embodiment, the material on contact hole etching barrier layer 41 is silicon nitride.
It is formed in the dielectric layer in semiconductor substrate 1 and exposes the through-hole to electrical connecting element.In this implementation
In example, it is formed with and exposes respectively as source S 1, the drain D 1 to electrical connecting element in the dielectric layer of NMOS area
Two through-hole C1, and expose metal gates 21 through-hole C3, be formed in the dielectric layer in the area PMOS and expose respectively
As two through-hole C2 of the source S 2 to electrical connecting element, drain D 2, and expose the through-hole C4 of metal gates 31, leads to
Hole C1, through-hole C2 at least run through third dielectric layer 43, the second dielectric layer 42 and contact hole etching barrier layer 41, and as contact
Hole.
Conductive layer E is generally U-shaped, covers the side wall of through-hole C1, C2 and described to electrical connecting element, and be formed with recessed
Slot, the upper surface (surface where highest point) of conductive layer E are lower than the opening of through-hole C1, C2.In the present embodiment, conductive layer E
The metal silicide layer of metal material layer 5 and the bottom through-hole C1, C2 in bottom side of the wall including being covered on through-hole C1, C2
6, metal material layer 5 with silicon for reacting to form metal silicide layer 6.
Further, metal material layer 5a includes Ti layers and the TiN layer on Ti layer, and metal silicide layer 6 is
TiSix, TiSixWith lower schottky barrier height (SBH), it is thus possible to significantly more reduction source S 1, drain D 1,
The contact resistance of source S 2, drain D 2.But it should be noted that in the inventive solutions, the material of metal material layer 5 is simultaneously
It should not be limited to thoses mentioned above, the metal material of metal silicide can also be used to form for Co, Ni, Pt etc..
In the present embodiment, the ratio between the height of conductive layer E and the depth of through-hole C1, C2 are 1:5 to 1:2.
Metal layer 8 filled with covering conductive layer E in through-hole C1, C2, to form plug P1, P2, two plug P1 difference
Electrical connection is contacted with the source S 1 of NMOS area, drain D 1, two plug P2 contact electricity with the source S 2 in the area PMOS, drain D 2 respectively
Connection, therefore plug P1, P2 are also referred to as contact plunger.
Metal layer 8 is filled in through-hole C3, C4, to form plug P3, P4, the metal gates 21 of plug P3 and NMOS area are connect
Electric shock connection, plug P4 contacts electrical connection with the metal gates 31 in the area PMOS, therefore plug P3, P4 are also referred to as contact plunger.
In the present embodiment, metal layer 8 is tungsten (W).In the alternative of the present embodiment, metal layer 8 can also select it
He is suitable as the metal of plug.
It should be noted that in the inventive solutions, what is be electrically connected with plug should not limit to electrical connecting element
Source electrode, drain electrode in transistor, are adapted to any required element being powered on, such as metal wire, resistance, capacitor, doping
Area etc..In addition, plug both can be contact plunger, or the non-contact plug positioned at contact plunger upper layer for example interconnects
M1 layers of plug in structure.
In addition, foregoing invention design according to the present invention is not it is found that the construction of conductive layer should be limited as the present embodiment institute
Give including the metal silicide layer that is covered on through-hole bottom wall, and be covered in through-hole bottom side of the wall and be used to form metallic silicon
The metal material layer of compound selects the material of any conduction to can solve the technical issues of present invention is claimed.Conductive layer
Various pieces can select identical material, different materials can also be selected.
So far, semiconductor device according to an embodiment of the present invention and its manufacturing method is described in detail.In order to avoid
Cover design of the invention, do not describe some details known in the field, those skilled in the art as described above,
Completely it can be appreciated how implementing technical solution disclosed herein.In addition, each embodiment for being instructed of this disclosure can be with
Independent assortment.It should be appreciated by those skilled in the art, can to embodiments illustrated above carry out it is a variety of modification without departing from
The spirit and scope of the present invention as defined in the appended claims.
Claims (20)
1. a kind of semiconductor devices with plug characterized by comprising
Semiconductor substrate is formed with to electrical connecting element in the semiconductor substrate；
Dielectric layer in the semiconductor substrate, be formed in the dielectric layer expose it is described to the logical of electrical connecting element
Hole；
Conductive layer in the through-hole covers the side wall of the through-hole and described to electrical connecting element, and is formed with recessed
Slot, the upper surface of the conductive layer are lower than the opening of the through-hole；
It fills the through-hole and covers the metal layer of the conductive layer.
2. semiconductor devices as described in claim 1, which is characterized in that the depth of the height of the conductive layer and the through-hole
The ratio between be 1:5 to 1:2.
3. semiconductor devices as described in claim 1, which is characterized in that the conductive layer includes:
The covering metal silicide layer to electrical connecting element；
The metal material layer of the bottom side of the wall of the through-hole is covered, the metal material layer is used to generate the metal with pasc reaction
Silicide layer.
4. semiconductor devices as claimed in claim 3, which is characterized in that the metal silicide layer includes TiSix, the gold
Belong to the TiN layer that material layer includes Ti layers and is covered on the Ti layer.
5. semiconductor devices as described in claim 1, which is characterized in that the metal layer includes tungsten.
6. such as semiconductor devices described in any one of claim 1 to 5, which is characterized in that the plug is contact plunger.
7. semiconductor devices as claimed in claim 6, which is characterized in that it is described to electrical connecting element be transistor source electrode
And/or drain electrode.
8. semiconductor devices as claimed in claim 7, which is characterized in that the transistor is fin formula field effect transistor.
9. semiconductor devices as claimed in claim 8, which is characterized in that the fin formula field effect transistor includes fin and grid
Pole structure, the gate structure are located on the fin, the source electrode, drain electrode include groove in the fin and
The semiconductor material being filled in the groove.
10. a kind of forming method of the semiconductor devices with plug characterized by comprising
Semiconductor substrate is provided, is formed in the semiconductor substrate to electrical connecting element；
Dielectric layer is formed on the semiconductor substrate, is formed in the dielectric layer and is exposed the leading to electrical connecting element
Hole；
Forming conductive layer in the through-hole, the conductive layer covers the side wall of the through-hole and described to electrical connecting element,
And being formed fluted, the upper surface of the conductive layer is lower than the opening of the through-hole；
Metal layer is filled into the through-hole to form the plug, the metal layer covers the conductive layer.
11. forming method as claimed in claim 10, which is characterized in that the depth of the height of the conductive layer and the through-hole
The ratio between be 1:5 to 1:2.
12. forming method as claimed in claim 10, which is characterized in that the forming method of the conductive layer includes:
Form the entire side wall and the metal material to electrical connecting element of the upper surface, the through-hole that cover the dielectric layer
The bed of material；
It anneals, so as to cover the part to electrical connecting element in the metal material layer with described to electrical connecting element
Reaction generates metal silicide layer；
After carrying out the annealing, sacrificial layer of the surface lower than the opening of the through-hole is formed, the sacrificial layer covers the gold
Belong to the metal material layer in the bottom side of the wall of silicide layer and the through-hole；
Remove the metal material layer not covered by the sacrificial layer；
Remove the sacrificial layer.
13. forming method as claimed in claim 12, which is characterized in that the metal material layer includes Ti layers and is covered on institute
The TiN layer on Ti layer is stated, the metal silicide layer includes TiSix。
14. forming method as claimed in claim 12, which is characterized in that the forming method of the sacrificial layer includes:
It is formed and covers the metal material layer, the metal silicide layer and the sacrificial material layer for filling the through-hole；
The sacrificial material layer carve, after described time is carved, the remaining sacrifice material being only filled in the through-hole lower end
The bed of material constitutes the sacrificial layer.
15. forming method as claimed in claim 12, which is characterized in that the sacrificial layer is BARC layer or ODL layers.
16. such as the described in any item forming methods of claim 10 to 15, which is characterized in that the metal layer includes tungsten.
17. such as the described in any item forming methods of claim 10 to 15, which is characterized in that the plug is contact plunger.
18. forming method as claimed in claim 17, which is characterized in that it is described to electrical connecting element be transistor source electrode
And/or drain electrode.
19. forming method as claimed in claim 18, which is characterized in that the transistor is fin formula field effect transistor.
20. forming method as claimed in claim 19, which is characterized in that the fin formula field effect transistor includes fin and grid
Pole structure, the gate structure are located on the fin, the source electrode, drain electrode include groove in the fin and
The semiconductor material being filled in the groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710537017.4A CN109216321A (en) | 2017-07-04 | 2017-07-04 | Semiconductor devices and forming method thereof with plug |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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