CN103779232A - 一种薄膜晶体管的制作方法及薄膜晶体管 - Google Patents
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Abstract
本发明公开了一种薄膜晶体管的制作方法及薄膜晶体管,采用该方法用以实现一种良品率较高的薄膜晶体管。所述薄膜晶体管的制作方法包括:包括在基板上形成栅极图形和栅极绝缘层的过程,以及形成源极、漏极和有源层图形的过程;所述形成源极、漏极和有源层图形的过程具体为:在基板上依次形成覆盖整个基板的半导体层和导电层;分别在所述导电层上待形成源极的区域和待形成漏极的区域形成设定厚度的第一光刻胶层;至少在所述导电层上待形成源极和漏极之间的间隙形成第二光刻胶层;对形成有所述第一光刻胶层、第二光刻胶层、半导体层和导电层的基板进行刻蚀工艺形成有源层、源极和漏极的图形。
Description
技术领域
本发明涉及半导体器件制作技术领域,尤其涉及一种薄膜晶体管的制作方法及薄膜晶体管。
背景技术
薄膜晶体管(Thin Film Transistor,TFT)作为开关器件在显示技术领域发挥着重要的作用。为制作出低成本高性能的TFT一直是人们追求的目标。
一般地,薄膜晶体管至少包括栅极(Gate)、源极和漏极(Source和Drain,简称源漏极SD),以及沟道层(Channel,也称有源层)等。近年来,为了简化工艺流程或减少掩模板的使用数量,会先沉积制作有源层图形的半导体层和制作源极和漏极图形的导电层,然后通过灰色调掩模板(gray tone mask,简称GTM)或半色调掩模板(half tone mask,简称HTM)技术形成不同厚度的光刻胶图形,最后经刻蚀工艺制作出有源层、源极和漏极图形等。
以底栅型TFT为例说明现有技术制作TFT的方法,主要包括以下步骤:
(1)采用常规工艺在基板上制作栅极和栅极绝缘层;
(2)在形成有所述栅极和栅极绝缘层的基板上依次沉积半导体层和导电层;
(3)通过灰色调掩模板或半色调掩模板在所述导电层上形成光刻胶图形,所述灰色调或半色调掩模板用以实现不同厚度的光刻胶层,使得导电层待形成源漏极的区域与源极和漏极之间的区域的光刻胶的厚度不等。
(4)先后对所述导电层和半导体层进行刻蚀工艺,形成有源层、源极和漏极图形。
近年来,随着图形线宽不断减小的趋势,源极和漏极之间的距离越来越小,一般在几微米量级,源极和漏极很容易由于刻蚀不完全而短路(即形成GTBridge不良)。此外,有源层也会因为过度刻蚀而被损坏,造成有源层断开(即形成channel open不良)。现有技术通过灰色调掩模板或半色调掩模板形成不同区域厚度不同的光刻胶层,由于涂胶均一性和曝光均一性的限制,不完全曝光区域(即沟道对应的区域)对应制作出来的光刻胶层的厚度均一性难以准确控制,有些区域较薄有些区域较厚,而后续刻蚀是按照等厚度的条件进行的,这就导致较厚区域的光刻胶刻蚀不完全,产生源漏极短路(GT Bridge)不良,较薄区域的光刻胶刻蚀过度造成TFT通电时沟道开路(channel open)不良的问题。严重影响TFT的工作性能,或造成TFT的不良,使得批量生产的TFT的良品率下降。
发明内容
本发明实施例提供的一种薄膜晶体管的制作方法,采用该方法用以实现一种良品率较高的薄膜晶体管。
所述薄膜晶体管的制作方法包括:在基板上形成栅极图形和栅极绝缘层的过程,以及形成源极、漏极和有源层图形的过程;
所述形成源极、漏极和有源层图形的过程具体为:
在基板上依次形成覆盖整个基板的半导体层和导电层;
分别在所述导电层上待形成源极的区域和待形成漏极的区域形成设定厚度的第一光刻胶层;
至少在所述导电层上待形成源极和漏极之间的间隙形成第二光刻胶层;
对形成有所述第一光刻胶层、第二光刻胶层、半导体层和导电层的基板进行刻蚀工艺形成有源层、源极和漏极的图形。
较佳地,在形成所述第二光刻胶层的同时还包括,形成位于所述第一光刻胶层上方的第二光刻胶层。
较佳地,所述对形成有第一光刻胶层、第二光刻胶层、半导体层和导电层的基板进行刻蚀工艺形成有源层、源极和漏极的图形,具体为:
对所述导电层进行刻蚀工艺,保留第一光刻胶层和第二光刻胶层覆盖区域的导电层,露出第一光刻胶层和第二光刻胶层未覆盖区域的半导体层;
对所述半导体层进行刻蚀工艺,去除第一光刻胶层和第二光刻胶层未覆盖区域的半导体层,第一光刻胶层和第二光刻胶层覆盖区域的半导体层作为有源层图形;
按照所述第二光刻胶的设定厚度对所述第二光刻胶层进行灰化处理,露出待形成的源极和漏极之间的间隙对应的导电层;
再次对所述导电层进行刻蚀,去除待形成的源极和漏极之间的间隙对应的导电层,形成相互绝缘的源极漏极图形。
较佳地,形成所述有源层、源极和漏极的图形之后还包括:剥离所述源极和漏极上的第一光刻胶层。
较佳地,所述在基板上形成栅极图形、栅极绝缘层的过程,具体为:
在形成所述源极、漏极和有源层图形之前,在所述基板上形成栅极图形以及位于所述栅极图形上的栅极绝缘层;或者
在形成所述源极、漏极和有源层图形之后在所述基板上形成栅极绝缘层,以及位于栅极绝缘层之上的栅极图形。
较佳地,所述第一光刻胶层的厚度为1.5~2.5μm。
较佳地,所述第二光刻胶层为厚度均一的膜层;所述第二光刻胶层的厚度为0.3~0.8μm。
较佳地,所述待形成的源极和漏极之间的距离为2.5~4.55μm。
较佳地,所述有源层由非晶硅、多晶硅或金属氧化物半导体制作而成。
本发明实施例还提供一种薄膜晶体管,采用上述薄膜晶体管的制作方法制作而成。
本发明实施例提供的上述薄膜晶体管的制作方法,通过两次构图工艺形成两层光刻胶层,第一光刻胶层仅覆盖待形成的源极和漏极对应的区域,第二光刻胶层覆盖待形成的源极和漏极之间的间隙区域。第二光刻胶层的厚度可以按照实际需求而制作,由于待形成的源极和漏极之间的间隙不存在第一光刻胶层,避免了通过灰色调掩模板或半色调掩模板形成位于源极和漏极上方的光刻胶和位于源极和漏极之间的间隙上的光刻胶时引起的源极和漏极之间的间隙上的光刻胶厚度不均一的问题。本发明实施例提供的TFT的制作方法,未采用灰色调掩模板或半色调掩模板,通过两次构图工艺形成两层光刻胶层,源极和漏极之间的间隙上的光刻胶厚度均一,后续对第二层光刻胶层进行去除时,按照等厚度的条件可以完全去除,因此不会造成过度去除或未完全去除的情况,形成的源极和漏极短路,通电时有源层的沟道开路的问题,提高TFT的良品率。附图说明
图1本发明实施例提供的制作TFT的总体流程示意图;
图2为本发明实施例提供的包括有栅极和栅极绝缘层的TFT结构示意图;
图3为本发明实施例提供的包括用于形成有源层的半导体层和用于形成源
极和漏极的导电层的TFT结构示意图;
图4为本发明实施例提供的包括第一光刻胶层的TFT结构示意图;
图5为本发明实施例提供的包括第二光刻胶层的TFT结构示意图;
图6为本发明实施例提供的形成源极、漏极和有源层过程的结构示意图;
图7为本发明实施例提供的包括有源层的TFT结构示意图;
图8为本发明实施例提供的去除第二光刻胶层的TFT结构示意图;
图9为本发明实施例提供的包括源极和漏极的TFT结构示意图;
图10为本发明实施例提供的去除第一光刻胶层的TFT结构示意图。
具体实施方式
本发明实施例提供一种薄膜晶体管的制作方法及薄膜晶体管,通过两次构图工艺分别在用以形成源极、漏极和有源层图形的膜层上制作两层光刻胶层。第一层光刻胶层保证光刻胶仅覆盖待形成的源极和漏极所在区域,露出待形成的源极和漏极之间的间隙对应的区域;第二层光刻胶保证光刻胶覆盖待形成的源极和漏极之间的间隙对应的区域。源极和漏极之间的间隙对应的区域设置的第二层光刻胶厚度均一。后续刻蚀按照等厚度的条件进行时,由于第二层光刻胶厚度均一,不会产生源漏极短路(GT Bridge)不良,或者产生TFT通电时沟道开路(channel open)不良的问题,使得批量生产的TFT的良品率提高。
需要说明的是,TFT的有源层位于源极和漏极的下方,源极和漏极之间的间隙对应的有源层的部分在TFT导通时为TFT的沟道区域,沟道的长度约等于源极和漏极之间的间隙的宽度,沟道的宽度约等于源极和漏极之间的间隙的长度。
以下将结合附图具体说明本发明实施例提供的薄膜晶体管的制作方法。
本发明实施例提供的薄膜晶体管的制作方法,主要包括以下步骤:在基板上形成栅极图形和栅极绝缘层的过程,以及形成源极、漏极和有源层图形的过程。
需要说明的是,本发明提供的TFT中的有源层的材料不限,例如可以为非晶硅层、多晶硅层或金属氧化物半导体层;所述TFT的结构不限,可以为底栅型也可以为顶栅型。
以下将具体说明本发明制作源极、漏极和有源层图形的过程。
参见图1,制作源极、漏极和有源层图形的过程总体包括以下步骤:
S11、在基板上依次形成覆盖整个基板的半导体层和导电层;
S12、分别在所述导电层上待形成源极的区域和待形成漏极的区域形成设定厚度的第一光刻胶层;
S13、至少在所述导电层上待形成源极和漏极之间的间隙对应的区域形成设定厚度的第二光刻胶层;
S14、对形成有所述第一光刻胶层、第二光刻胶层、半导体层和导电层的基板进行刻蚀工艺形成有源层、源极和漏极图形。
进一步地,在形成所述第二光刻胶层的同时还包括,形成位于所述第一光刻胶层上方的第二光刻胶层。
本发明实施例提到的构图工艺至少包括光刻胶涂覆或滴注、曝光、显影、光刻刻蚀等步骤。
以下将以底栅型TFT为例,从工艺流程方面具体说明本发明实施例提供的薄膜晶体管的制作方法。
步骤一:制作栅极和栅极绝缘层的过程。
参见图2,在基板1上沉积一层导电层,通过构图工艺形成栅极2图形;该步骤采用第一掩模板制作栅极图形;制作栅极的过程与现有技术类似,栅极的材料不限。
参见图2,在形成有栅极2的基板1上形成一层或多层绝缘层作为栅极绝缘层3。形成栅极绝缘层的方法不限,栅极绝缘层的材料不限。
需要说明的是,制作栅极和栅极绝缘层的过程与现有技术类似。
针对底栅型TFT,在形成所述源极、漏极和有源层图形之前,在所述基板上形成栅极图形以及位于所述栅极图形上的栅极绝缘层;
针对顶栅型TFT,在形成所述源极、漏极和有源层图形之后在所述基板上形成栅极绝缘层,以及位于栅极绝缘层之上的栅极图形。
步骤二:制作源极、漏极和有源层图形的过程。
以下将结合步骤一的描述具体说明图1所示的制作源极、漏极和有源层图形的具体过程。
上述步骤S11在基板上依次形成覆盖整个基板的半导体层和导电层,具体为:
在上述步骤一形成有所述栅极和栅极绝缘层的基板上采用采用化学气相沉积法或热蒸镀等方法沉积一层覆盖整个基板的半导体层;该半导体层可以为非晶硅、多晶硅或金属氧化物半导体等膜层;该半导体层用于制作有源层图形;
在形成有所述半导体层的基板上采用采用化学气相沉积法或热蒸镀等方法沉积一层覆盖整个基板的导电层,该导电层用于制作源极和漏极图形;
如图3所示,TFT包括位于栅极绝缘层3上的半导体层10和位于半导体层10上的导电层11。
步骤S12分别在所述导电层上待形成源极的区域和待形成漏极的区域形成设定厚度的第一光刻胶层,具体为:
在形成有所述半导体层10和导电层11的基板1上形成一层设定厚度的光刻胶(Photoresist,简称PR)层,此时光刻胶层覆盖整个用于形成源极和漏极的导电层;通过第二掩模板对所述光刻胶层进行曝光和显影,保留待形成的源极和漏极正上方的光刻胶,其余位置的光刻胶完全去除,待形成的源极上方的光刻胶和待形成的漏极上方的光刻胶一起作为第一光刻胶层。如图4所示,包括位于待形成的源极和漏极正上方的第一光刻胶层4。
所述光刻胶可以为正性光刻胶也可以为负性光刻胶。
以光刻胶为正性光刻胶为例说明,通过第二掩模板对所述源极和漏极对应区域之外的区域完全曝光,曝光区域的光刻胶被完全显影掉。当然,源极和漏极之间的间隙对应区域的光刻胶完全曝光,显影时完全被显影掉,露出导电层11。
在导电层上形成光刻胶可以通过涂覆或滴注旋转法等,具体实现方法可以根据实际需求而定,这里不做限制。
较佳地,图4所示的第一光刻胶层4为疏水性的光刻胶层。由于半导体层10上方用于形成源极和漏极的导电层11为亲水性膜层,第一光刻胶层4为疏水性的光刻胶层时,后续在光刻胶的剥离(也称去除)工艺过程中光刻胶完全去除较容易。
较佳地,如图4所示,位于待形成的源极上方的第一光刻胶层和位于待形成的漏极上方的第一光刻胶层之间的距离L为2.0~4.5μm,该距离L等于源极和漏极之间的间隙宽度,TFT导通时,该距离L等于有源层上沟道的长度。源极和漏极之间间隙的宽度越小,TFT导通时,沟道的长度较短,TFT的开启电流Ion越大,有利于提高TFT的性能。
步骤S13至少在所述导电层上待形成源极的区域和待形成漏极的区域上的第一光刻胶层之间形成设定厚度的第二光刻胶层,具体为:
在第一光刻胶层上方形成一层设定厚度为h的光刻胶层。通过第三掩模板对所述光刻胶层进行曝光显影,至少保留待形成的源极和漏极之间的间隙对应区域的光刻胶,去除其余区域的光刻胶(该步骤保证不去除第一光刻胶层)。或者通过第三掩模板对所述光刻胶层进行曝光显影,保留待形成的源极和漏极之间的间隙对应区域的光刻胶以及第一光刻胶层正上方的光刻胶。保留下的光刻胶层为第二光刻胶层。具体是否保留第一光刻胶层正上方的光刻胶视具体工艺条件或其他因素决定。如图5所示,包括位于第一光刻胶层4上方的第二光刻胶层5,第二光刻胶层5的厚度为h,由于第二光刻胶层5下方的导电层11的表面平坦,因此,第二光刻胶层5的厚度均一。
步骤S13中覆盖整个基板的光刻胶的形成与步骤S12中覆盖整个基板的光刻胶的形成过程类似,可以通过涂覆或滴注旋转等方法进行,具体实施时可以根据实际需求而定,这里不做限制。
优选地,第二光刻胶层5的厚度约为0.5μm(对应5000)。
较佳地,所述第二光刻胶层由疏水性的光刻胶制作而成。
第二光刻胶层的材料与第一光刻胶层的材料可以相同也可以不同。
第二光刻胶层的材料优选地满足以下条件:第二光刻胶层与第一光刻胶层的粘附性大于与用于形成源极和漏极的导电层之间的粘附性。
步骤S14对形成有所述第一光刻胶层、第二光刻胶层、半导体层和导电层的基板进行刻蚀工艺形成有源层、源极和漏极的图形,具体为:
1)首先对所述待形成源极和漏极的导电层11进行刻蚀工艺,参见图6,保留导电层11上第一光刻胶层4和第二光刻胶层5覆盖的区域,露出第一光刻胶层4和第二光刻胶层5未覆盖区域的半导体层10。该步骤中的刻蚀工艺优选使用湿法刻蚀。
2)接着对图6所示的半导体层10进行刻蚀工艺,去除第一光刻胶层4和第二光刻胶层5未覆盖区域的半导体层,保留第一光刻胶层4和第二光刻胶层5覆盖区域的半导体层,此时的TFT结构如图7所示,第一光刻胶层4和第二光刻胶层5覆盖区域的半导体层作为有源层6的图形;该步骤中的刻蚀工艺优选使用干法刻蚀。
3)接着按照图7所示的第二光刻胶5的设定厚度h对第二光刻胶层5进行灰化(ashing)处理,完全去除第二光刻胶层5,参见图8,露出第二光刻胶层5下方的导电层11部分(即露出导电层11上待形成的源极和漏极之间的间隙部分);该过程由于第二光刻胶层5的厚度均一,对第二光刻胶层5进行灰化处理时,可以根据灰化光刻胶的厚度h准确灰化光刻胶,不会形成过度灰化光刻胶或对光刻胶灰化不足引起TFT GT Bridge不良,或者channel open不良的问题。灰化为干法刻蚀的一种,当然步骤3)中不限于通过灰化法处理第二光刻胶层5,可以通过任何能够准确去除第二光刻胶层不会产生过度刻蚀或刻蚀不到位的方法刻蚀第二光刻胶。
4)紧接着再次对导电层11进行刻蚀,去除导电层11上待形成的源极和漏极之间的间隙部分,形成图9所示的相互绝缘的源极7和漏极8图形。该步骤中的刻蚀过程优选使用干法刻蚀。
在步骤S14的基础上,所述方法还进一步包括:剥离所述源极和漏极上的第一光刻胶层。
具体地,在上述步骤4)的基础上,通过干法刻蚀去除第一光刻胶层(RPstrip),形成的TFT参见图10所示,TFT包括栅极2、上级绝缘层3,有源层6、源极7和漏极8。
上述过程为制作底栅型TFT的详细过程。
制作顶栅型TFT的过程与上述制作底栅型TFT的过程类似,不同之处在于,先制作有源层、源极和漏极图形,后制作栅极和栅极绝缘层图形,这里不再赘述。
上述制作TFT的过程仅是针对解决本发明的技术问题而提出的,任何包含本发明实施例提供的技术方案的TFT制作过程均包含在本发明范围之内。例如,在具体实施过程中还包括制作位于有源层与源极和漏极之间的欧姆接触层,以减小半导体层与源极和漏极之间的接触电阻,提高TFT的性能。举例说明,针对非晶硅半导体层材料制作有源层的情况,可以在有源层与源极和漏极之间制作经氮离子掺杂过的非晶硅层(制作N+a-Si)。
本发明实施例提供的TFT的制作方法可以取代任何包括通过半色调或灰色调掩模板实现不同厚度的光刻胶的过程,不仅适用于形成源极、漏极和有源层,同样适用于通过半色调或灰色调掩模板形成大面积不同厚度光刻胶的过程。
本发明实施例还提供一种薄膜晶体管,采用上述本发明实施例提供的薄膜晶体管的制作方法制作而成。薄膜晶体管中的有源层的材料类型不限。薄膜晶体管的结构至少包括栅极、栅极绝缘层、有源层、源极和漏极,还可以包括刻蚀阻挡层、欧姆接触层,与基板接触的缓冲层、覆盖整个TFT的钝化层等。这里就不一一详述。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (10)
1.一种薄膜晶体管的制作方法,其特征在于,包括在基板上形成栅极图形和栅极绝缘层的过程,以及形成源极、漏极和有源层图形的过程;
所述形成源极、漏极和有源层图形的过程具体为:
在基板上依次形成覆盖整个基板的半导体层和导电层;
分别在所述导电层上待形成源极的区域和待形成漏极的区域形成设定厚度的第一光刻胶层;
至少在所述导电层上待形成源极和漏极之间的间隙形成第二光刻胶层;
对形成有所述第一光刻胶层、第二光刻胶层、半导体层和导电层的基板进行刻蚀工艺形成有源层、源极和漏极的图形。
2.根据权利要求1所述的方法,其特征在于,在形成所述第二光刻胶层的同时还包括,形成位于所述第一光刻胶层上方的第二光刻胶层。
3.根据权利要求1或2所述的方法,其特征在于,所述对形成有第一光刻胶层、第二光刻胶层、半导体层和导电层的基板进行刻蚀工艺形成有源层、源极和漏极的图形,具体为:
对所述导电层进行刻蚀工艺,保留第一光刻胶层和第二光刻胶层覆盖区域的导电层,露出第一光刻胶层和第二光刻胶层未覆盖区域的半导体层;
对所述半导体层进行刻蚀工艺,去除第一光刻胶层和第二光刻胶层未覆盖区域的半导体层,第一光刻胶层和第二光刻胶层覆盖区域的半导体层作为有源层图形;
按照所述第二光刻胶的设定厚度对所述第二光刻胶层进行灰化处理,露出待形成的源极和漏极之间的间隙对应的导电层;
再次对所述导电层进行刻蚀,去除待形成的源极和漏极之间的间隙对应的导电层,形成相互绝缘的源极漏极图形。
4.根据权利要求3所述的方法,其特征在于,形成所述有源层、源极和漏极的图形之后还包括:剥离所述源极和漏极上的第一光刻胶层。
5.根据权利要求1或2所述的方法,其特征在于,所述在基板上形成栅极图形、栅极绝缘层的过程,具体为:
在形成所述源极、漏极和有源层图形之前,在所述基板上形成栅极图形以及位于所述栅极图形上的栅极绝缘层;或者
在形成所述源极、漏极和有源层图形之后在所述基板上形成栅极绝缘层,以及位于栅极绝缘层之上的栅极图形。
6.根据权利要求1或2所述的方法,其特征在于,所述第一光刻胶层的厚度为1.5~2.5μm。
7.根据权利要求1或2所述的方法,其特征在于,所述第二光刻胶层为厚度均一的膜层;所述第二光刻胶层的厚度为0.3~0.8μm。
8.根据权利要求1或2所述的方法,其特征在于,所述待形成的源极和漏极之间的距离为2.5~4.55μm。
9.根据权利要求1所述的方法,其特征在于,所述有源层由非晶硅、多晶硅或金属氧化物半导体制作而成。
10.一种薄膜晶体管,其特征在于,采用权利要求1-9任一所述的方法制作而成。
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WO2018182738A1 (en) * | 2017-03-31 | 2018-10-04 | Intel Corporation | Thin film transistors with spacer controlled gate length |
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