CN103776907B - Ultrasonic phase array based on sinc interpolation receives signal essence time-delay method - Google Patents

Abstract

The present invention has announced a kind of ultrasonic phase array based on sinc interpolation and has received signal essence time-delay method. The time-delay accuracy that receives signal in view of ultrasonic phase array has material impact to systematic function, considering on the basis of the precision of signal delay, processing speed and system optimization flexibility etc., the present invention proposes a kind of smart time-delay method based on sinc interpolation, the present invention has less secondary lobe and compared with the advantage of high attenuation speed, obtains interpolation coefficient accurately in conjunction with feature and the Hanning window of sinc function release signal. Utilize real-time parallel disposal ability and storage capacity that FPGA is powerful, carry out rapidly and accurately sinc interpolation with pipeline system, complete the accurate delay of any step-length of sampled signal. The present invention has higher precision and treatment effeciency, can obviously improve the time-delay accuracy of ultrasonic phase array reception signal, improves contrast resolution and the spatial resolution of detection system.

Description

Ultrasonic phase array based on sinc interpolation receives signal essence time-delay method

Technical field

The invention belongs to industrial ultrasonic non-destructive inspection techniques field, relate to a kind of surpassing based on sinc interpolationSound phase control array receiving signal essence time-delay method.

Background technology

Ultrasonic phase array detection technique is a kind of advanced person's ultrasonic non-destructive inspection techniques, because it is significantAdvantage, is widely used in fields such as aviation, nuclear energy, machinery, electric power, petrochemical industry and railways,Create huge Social benefit and economic benefit. Ultrasonic phase array detection system is used array energy transducer,Realize phase delay by the time delay of adjusting each array element transmitting/receiving signal, can control composite waveThe curvature of front, sensing, aperture etc., reach wave beam focusing, deflection, wave beam formation etc. multiple phasedEffect, forms image clearly. Time-delay accuracy has determined phase delay precision, to detection systemContrast resolution and spatial resolution have material impact, be one of important indicator of measurement system.

The precision of digital delay is high, controls convenient, good stability, can greatly improve ultrasonic phase arrayImage quality. The realization of digital delay can be divided into thick time delay and smart time delay, when slightly time delay is based on samplingClock counting, implements fairly simplely, and precision can reach 10ns, and smart delay requirement can reach 10nsIn, implement more difficult. Realize at present smart time delay and mainly contain two kinds of methods, one is eachIndividual passage uses a special sampling clock sampling, and the phase place of these clocks staggers mutually, is worth for respectivelyChannel delay poor. Increase to 32 passages even manyly when the autonomous channel of system, system cannot be carriedHeight is multi-clock resource so. Another kind is first the same clock of whole passages to be sampled, then to respectivelyThe signal of individual passage carries out interpolation and increases counting of sampling, to improve the precision of smart time delay, is called letterNumber restore. Sinc interpolation is a kind of agonic signal restoring method, according to Shannon sampling thheorem,Under the condition that meets sampling thheorem, any frequency limit signal can be real by its discrete samplesExisting Accurate Reconstruction, the smart time delay that therefore utilizes sinc interpolation to realize signal is a kind of effective method.But, sinc interpolation needs infinite summation, in the time of specific implementation, will carry out truncation, conventionally limitBuilt in below 8 o'clock, inevitably like this can produce some errors, as Gibbs effect. In order to subtractLittle this impact, reply interpolation kernel is carried out windowing sharpening processing.

FPGA(fieldprogrammablegatearrays, FPGA in recent years) at speed and capacityOn develop rapidly it is widely used in high-speed digital signal process field, due to ultrasonic phaseControl array 1 system has the features such as big data quantity, computing complexity, flow process be relatively fixing, and therefore FPGA becomesFor the optimal selection of processing in real time of ultrasonic phase array system data.

Summary of the invention

The present invention is directed to the deficiencies in the prior art, a kind of ultrasonic phase array based on sinc interpolation is providedReceive signal essence time-delay method.

The present invention can obtain the release signal of any time by sinc interpolation, realize any step-lengthReceive the time delay of signal essence. Cause Gibbs phenomenon for fear of directly blocking sinc function, to sincFunction carries out windowing process, to obtain more accurate inhibit signal. Utilize FPGA powerful in real timeParallel processing capability, carries out sinc interpolation rapidly with pipeline system, directly exports crude sampling letterSignal after number smart time delay. The time that the present invention can obviously improve ultrasonic phase array reception signal prolongsPrecision late, and there is higher treatment effeciency, greatly improve contrast resolution and the sky of detection systemBetween resolution ratio.

Technical problem of the present invention is solved by following technical scheme:

Step 1: main control computer is according to the reception signal lag accuracy computation 8 point interpolation needs that arrange8 sinc interpolation coefficients, obtain 8 interpolation coefficients corresponding to each delay value in the sampling period.

Step 2: convert 8 corresponding each delay value interpolation coefficients to 32 floating numbers, respectivelyBe stored to 8 dual port RAMs in FPGA.

Step 3: generate corresponding address of reading interpolation coefficient dual port RAM according to smart time delay.

Step 4: FPGA starts sampling, converts the valid data of input to 32 floating type data,And in 8 data cache registers, transmit successively storage with pipeline mode.

Step 5: taking sampling clock as step, the data in current 8 data cache registers are dividedDo not multiply each other with each self-corresponding interpolation coefficient, to 8 products summations, flowing water is exported after a succession of interpolationData.

Step 6: the data after interpolation are converted to the processing of integer as floating type, after output time delaySignal, completes the smart time delay of sampled input signal.

Beneficial effect of the present invention is mainly manifested in:

(1) utilize sinc function to there is the functional characteristics of release signal, and it is added with Hanning windowWindow processing, obtains interpolation coefficient accurately.

(2) utilize FPGA processing capability in real time design fast sinc interpolating module, real efficientlyThe smart time delay of existing signal.

(3) high-precision signal delay determines the phase delay of signal, can control and close more accuratelyBecome the curvature, sensing, aperture of wave surface etc., reach wave beam focusing, deflection, wave beam formation etc. multiplePhased effect, forms image more clearly.

(4) greatly improve contrast resolution and the spatial resolution of detection system.

Brief description of the drawings

Fig. 1 is that sinc interpolation realizes the operational flowchart that ultrasonic phase array reception signal essence postpones.

Fig. 2 is sinc function and adds Hanning window sinc function schematic diagram.

Fig. 3 is that sinc interpolation realizes the MATLAB emulation that ultrasonic phase array receives the time delay of signal essence and showsIntention.

Fig. 4 is that sinc interpolation realizes the FPGA functional block diagram that ultrasonic phase array reception signal essence postpones.Detailed description of the invention

Below in conjunction with accompanying drawing, the invention will be further described.

As shown in Figure 1, the present invention utilizes sinc interpolation to realize ultrasonic phase array and receives signal essence time delayOperating process can be divided into following step:

Step 1: main control computer is according to the reception signal lag accuracy computation 8 point interpolation needs that arrange8 sinc interpolation coefficients, obtain 8 interpolation coefficients corresponding to each delay value in the sampling period.

Step 2: convert 8 corresponding each delay value interpolation coefficients to 32 floating numbers, respectivelyBe stored to 8 dual port RAMs in FPGA.

Step 3: generate corresponding address of reading interpolation coefficient dual port RAM according to smart time delay.

Step 4: FPGA starts sampling, converts the valid data of input to 32 floating type data,And in 8 data cache registers, transmit successively storage with pipeline mode.

Step 5: taking sampling clock as step, the data in current 8 data cache registers are dividedDo not multiply each other with each self-corresponding interpolation coefficient, to 8 products summations, flowing water is exported after a succession of interpolationData.

Step 6: the data after interpolation are converted to the processing of integer as floating type, after output time delaySignal, completes the smart time delay of sampled input signal.

8 interpolation coefficients corresponding to each delay value in a kind of described calculating sampling cycle of step, areBy to sinc function windowing block and obtain. The essence that ultrasonic phase array receives smart time delay is by numberThe method of word signal processing realizes the interpolation of signal, and this process can be with an ideal low-pass filterDevice is realized, and sinc function is regarded ideal low-pass filter always, and its interpolation formula is

$\hat{x}\left(t\right)=\underset{n=-\∞}{\overset{+\∞}{\mathrm{\Σ}}}x\left(\mathrm{nT}\right)\frac{\sin [\mathrm{\π}(t-\mathrm{nT})/T]}{\mathrm{\π}(t-\mathrm{nT})/T}=\underset{n=-\∞}{\overset{+\∞}{\mathrm{\Σ}}}x\left(\mathrm{nT}\right)\sin c(t/T-n)$

In formula,For the signal after postponing, t is time delay, and x (nT) is original sampled signal, nFor sampled point sequence number, T is the sampling period, sinc function expression be sinc (t)=sin (π t)/π t, canSee, the sinc interpolation that realizes some points needs infinite summation, and this is in actual use can notRow. In fact, signal is postponed just need to draw after primary signal to letter sometimeNumber value, do not need complete restoring signal, can block to carry out to sinc function finite lengthInterpolation, each interpolation point only uses the information of contiguous several points, generally uses 8 point interpolations, with to be insertedThe complete cycle of value point is centered by point, selects its first three point and four points thereafter. Therefore, sinc interpolationFormula become

$\hat{x}\left(t\right)==\underset{m=-3}{\overset{4}{\mathrm{\Σ}}}x\left(\mathrm{nT}\right)\sin c(t/T-n)$

But when using the sinc function that directly blocks when existing the signal of brink to carry out interpolation, meetingThere is a kind of ringing that is called Gibbs effect. In order to reduce the impact of Gibbs effect, needTo the windowing process of sinc function. Because Hanning window has less secondary lobe and the larger rate of decay, because ofThis adds Hanning window processing to sinc function, calculates corresponding 8 interpolation coefficients according to delay value.Fig. 2 is sinc function and adds the schematic diagram of Hanning window sinc function, can after sinc function is added to Hanning windowSo that secondary lobe is decayed fast, reduce the leakage of energy, thereby reduce the impact of Gibbs effect. Fig. 3For sinc interpolation realizes ultrasonic phase array and receive the MATLAB emulation schematic diagram of signal essence time delay, defeatedEntering signal is that frequency is the True Data of the sampling clock collection of 100MHz, utilizes sinc interpolation algorithmIn MATLAB software, carry out smart time delay simulation, sampled signal is carried out respectively to the essence of 3ns and 8nsTime delay simulation, the simulated effect obtaining is very good.

Described in step 2, interpolation coefficient is converted to 32 floating numbers, be stored to respectively in FPGA8 dual port RAMs. Fig. 4 is that sinc interpolation realizes the FPGA that ultrasonic phase array reception signal essence postponesFunctional block diagram. Because interpolation coefficient is the decimal that is less than 1, in FPGA, can not store fractional formatData, therefore all convert interpolation coefficient to 32 floating numbers, can directly be stored to FPGA,Can keep again precision. The degree of depth of 8 dual port RAMs in FPGA is 100, can be according to time delay essenceDegree uses the space of part or all of dual port RAM, and delay precision is the highest can reach the sampling period1/100。

Described in step 3, generate corresponding address of reading interpolation coefficient dual port RAM according to smart time delay,Essence time delay is divided by the delay precision arranging, and business's processing that rounds up, is interpolation coefficient under this time delayMemory address, read 8 interpolation coefficients in dual port RAM simultaneously.

Described in step 4, the valid data of input are converted to 32 floating type data, and with flowing water sideFormula is successively 8 data cache register transmission storages. Because interpolation coefficient is 32 floating types, forOperative data type unified, will input data transaction and become 32 floating types. Sampled data is according to successivelySequentially, with pipeline mode successively 8 data cache register transmission storages.

Input data described in step 5 interpolation coefficient respectively and separately multiplies each other and the summation that adds up, streamWater is exported the data after a succession of interpolation. According to the formula of 8 sinc interpolation, calculate certain data and prolongTime certain time interpolated data need 3 data and below 4 data above, totally 8 data are dividedNot with interpolation coefficient phase multiply accumulating, because input data are with flowing water in 8 data cache registersMode is transmitted storage, and therefore the data after interpolation are continuous wave outputs. Should be noted that, sampling startsSeveral interpolation points likely get less than three whole points before it, now by get less than dataThe whole zero setting of point. Last several interpolation point is got less than four whole thereafter points, now also will will get notThe data that arrive are all zero setting all.

The processing that the data after interpolation is converted to integer as floating type described in step 6, output is prolongedTime after signal, complete the smart time delay of sampled input signal. Because the interpolated data after phase multiply accumulating isFloating type, for the needs of subsequent treatment, converts interpolated data to integer, and output signal is completeBecome to receive the smart time delay of signal.

Claims (2)

1. the ultrasonic phase array based on sinc interpolation receives signal essence time-delay method, and its feature comprises the following steps in the method:

Step 1: 8 sinc interpolation coefficients that main control computer needs according to reception signal lag accuracy computation 8 point interpolations that arrange, obtain 8 interpolation coefficients corresponding to each delay value in the sampling period;

Step 2: convert 8 corresponding each delay value interpolation coefficients to 32 floating numbers, be stored to respectively 8 dual port RAMs in FPGA;

Step 3: generate corresponding address of reading interpolation coefficient dual port RAM according to smart time delay;

Step 4: FPGA starts sampling, converts the valid data of input to 32 floating type data, and in 8 data cache registers, transmits successively storage with pipeline mode;

Step 5: taking sampling clock as step, the data in current 8 data cache registers are multiplied each other with each self-corresponding interpolation coefficient respectively, to 8 product summations, flowing water is exported the data after a succession of interpolation;

Step 6: the data after interpolation are converted to the processing of integer as floating type, the signal after output time delay, completes the smart time delay of sampled input signal.

2. the ultrasonic phase array based on sinc interpolation according to claim 1 receives signal essence time-delay method, it is characterized in that:

8 interpolation coefficients corresponding to each delay value in sampling period described in step 1, by sinc function windowing block and obtain.