CN103745680B - Shift register module and control method thereof - Google Patents
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Abstract
The invention provides a shift register module and a control method thereof, and the shift register module comprises: a first shift register, a second shift register, a third shift register and a fourth shift register. The first shift register receives a first input signal to generate a first driving signal; the second shift register receives a second input signal independent of the first input signal and generates a second driving signal; the third shift register receives a third input signal independent of the first input signal and the second input signal and generates a third driving signal; the fourth shift register receives a fourth input signal independent of the first input signal, the second input signal, and the third input signal, and outputs a fourth driving signal. In addition, a control method corresponding to the shift register module is also provided.
Description
Technical field
The present invention relates to the circuit of a kind of shift register, especially relate to a kind of shift register for display device
Circuit.
Background technology
Fig. 1 is shown as the block chart of existing grid electrode drive module.Refer to Fig. 1, existing grid electrode drive module 100 can
To be applicable to a display device, it includes multiple shift register, such as 102,104,106 and 108.Additionally, in FIG, mark
Show that Vst is expressed as initial signal, sign CK and XCK is all expressed as frequency signal, indicates Bi1And Bi2All it is expressed as input signal,
And indicate Gn-1、Gn、Gn+1And Gn+2All it is expressed as gate drive signal.It addition, each shift register all has three crystal
Pipe, indicates with M3 with M1, M2 respectively.As a example by the operation of shift register 102, the gate terminal of its transistor M1 Yu M2 is respectively
Receive initial signal Vst and gate drive signal Gn, and decide whether input signal Bi according to this1It is sent to the grid of transistor M3
Extremely, it is charged with the gate terminal to transistor M3.Transistor M3 in shift register 102 is then according to its gate terminal
Voltage swing and decide whether to be sent to frequency signal CK the outfan of shift register 102, to form gate drive signal
Gn-1.As for the operation of shift register 104～108, this area has personnel's Ke Yi aforementioned shift register of usual knowledge
The mode of operation of 102 and push away, just repeat no more at this.
Knowable to the grid electrode drive module 100 shown in Fig. 1, shift register 102 and 104 receives same input signal Bi1,
Shift register 106 and 108 then receives same input signal Bi2.The most same input signal provides to continuous adjacent two-stage
Shift register.But, such way can make picture obvious band occur, illustrates with Fig. 2.Fig. 2 is shown as Fig. 1
The sequential chart of main signal of grid electrode drive module.In fig. 2, indicate the sign person being same as in Fig. 1 and be expressed as identical letter
Number.Additionally, in fig. 2, G is indicatedn-1_ NODE1 represents the voltage swing of the gate terminal of the transistor M3 in shift register 102,
And Gn_ NODE1 represents the voltage swing of the gate terminal of the transistor M3 in shift register 104.As shown in Figure 2, post when displacement
(as indicated G when the gate terminal of the transistor M3 in storage 102 is charged to high levelsn-1Shown in _ NODE1), shift register
102 correspondence can produce and export gate drive signal Gn-1, and when the gate terminal of the transistor M3 in shift register 104 is filled
Electricity to high levels time (as indicate GnShown in _ NODE1), shift register 104 correspondence can produce and export gate drive signal Gn。
When the gate terminal of the transistor M3 in shift register 102 and 104 is charged to high levels, corresponding transistor M1 Yu M2 is just
Can be closed, when being charged to high levels yet with the gate terminal of the transistor M3 in shift register 102, input signal
Bi1Present high levels, and when the gate terminal of the transistor M3 in shift register 104 is charged to high levels, input signal Bi1
Presenting low level, the gate terminal thus resulting in the transistor M3 in shift register 104 flows to input signal Bi1Electric leakage
Stream, can flow to input signal Bi much larger than the gate terminal of the transistor M3 in shift register 1021Leakage current.Such one
Come, will result in gate drive signal Gn-1With GnThe pulse of both has different level fall time, and then makes display dress
Obvious band is produced on the picture put.Similarly, shift register 106 and 108 also has identical situation.
Summary of the invention
In view of this, the present invention provides a kind of shift register module, can apply to display device, with avoid above-mentioned
The situation of band is there is in display device.
The present invention also provides for a kind of display device, can avoid the above-mentioned situation producing band on picture.
Additionally, the present invention also provides for the control method of a kind of display device, the above-mentioned picture in display device can be avoided
On band.
Shift register module provided by the present invention, including one first shift register, one second shift register, one
3rd shift register and one the 4th shift register, this is respectively provided with on-off circuit, output circuit and forbidden energy circuit.?
In first shift register, on-off circuit can receive the first input signal, and initiates signal deciding by the first input letter according to one
Number output.Output circuit is then coupled to on-off circuit, to receive the first input signal from on-off circuit output.When the first input
When the level of signal is switched to first level, output circuit can be by first frequency signal from the output of the first shift register
End output, to produce one first driving signal.It addition, forbidden energy circuit also can couple on-off circuit, defeated with according to on-off circuit
Go out the state of end and determine that forbidden energy first drives signal.The framework of the second shift register and the framework of the first shift register are big
In cause identical.Except for the difference that, to receive independent of the first input signal second defeated for the on-off circuit in the second shift register
Enter signal, so that the second shift register output two driving signal.The framework of the 3rd shift register and the first shift LD
The framework of device and the second shift register is substantially the same.Except for the difference that, the on-off circuit in the 3rd shift register can receive
Independent of the first input signal and the 3rd input signal of the second input signal, so that the 3rd shift register output the 3rd drives
Signal.The framework of the 4th shift register and the first shift register, the second shift register and the frame of the 3rd shift register
Structure is substantially the same.Except for the difference that, the on-off circuit in the 4th shift register can receive independent of the first input signal, second
Input signal and the 4th signal of the 3rd input signal, so that the 4th shift register output fourth drive signal.
From the point of view of another viewpoint, display device provided by the present invention, including substrate, pel array, the first shift LD
Device, the second shift register, the 3rd shift register and the 4th shift register.Pel array is formed on substrate, and has
There is multiple pixel column.Similarly, the first shift register, the second shift register, the 3rd shift register and the 4th displacement are posted
Storage is also formed on substrate.Wherein, the first shift register produces corresponding raster data model according to corresponding input signal
Signal.Second shift register produces corresponding gate drive signal according to corresponding input signal.3rd shift register depends on
Corresponding gate drive signal is produced according to corresponding input signal.4th shift register then produces according to corresponding input signal
Raw corresponding gate drive signal.Wherein, first, second, third input signal received with the 4th shift register is each
Independent.
From the point of view of another viewpoint, the control method of display device provided by the present invention, including producing multiple respective independence
Input signal to the multiple shift registers in display device produce multiple grids drive so that each shift register be corresponding respectively
Dynamic signal to the multiple pixel columns in display device one of them；And when when gate drive signal, one of them is disabled, then
The input signal that forbidden energy is corresponding.
The present invention provides the most independent multiple input signal to use to the shift register in shift register module, because of
As long as the sequential of these input signals is carried out suitable design by this, each shift register just can be made to produce and export grid
When pole drives signal, the input signal received by each shift register all can present high levels.Thus, it is possible to
Avoid the situation that on the picture of display device, band produces.
Accompanying drawing explanation
Fig. 1 is shown as the block chart of existing grid electrode drive module；
Fig. 2 is shown as the sequential chart of the main signal of the grid electrode drive module of Fig. 1；
Fig. 3 is shown as the Organization Chart of a kind of display device；
Fig. 4 is shown as the block chart of a kind of grid electrode drive module of the preferred embodiment according to the present invention；
Fig. 5 is shown as the circuit diagram of a kind of 3rd shift register of the preferred embodiment according to the present invention；
Fig. 6 is shown as the circuit diagram of a kind of 4th shift register of the preferred embodiment according to the present invention；
The sequential chart of the signal that Fig. 7 is shown as in Fig. 4；
Fig. 8 is shown as the steps flow chart of the control method of a kind of display device of the preferred embodiment according to the present invention
Figure.
Reference
100,306: grid electrode drive module
102,104,106,108,402,404,406,408,410,412: shift register
300: display device 302: substrate
304: pel array 312: pixel column
502,602: on-off circuit 504,604: output circuit
506,604,606: forbidden energy circuit 512,514,612,614: switch
522,532,534,536,538,622,632,634,636,638, M1, M2, M3: transistor
524,540,624,640: electric capacity
Bi1、Bi2, B1, B2, B3, B4: input signal
CK, XCK: frequency signal
Gn-1、Gn、Gn+1、Gn+2、G4n-1、G4n、G4n+1、G4n+2、G4n+3、G4n+4、G4n+5: gate drive signal
Vst: initial signal
The steps flow chart of the control method of S802, S804: display device
2t1,2t2,7t1,7t2,7t3: time point
Gn-1_NODE1、Gn_ NODE1: the voltage swing of the gate terminal of transistor M3
N1: node Vgl: low-voltage
Detailed description of the invention
Fig. 3 is shown as the Organization Chart of a kind of display device.Refer to Fig. 3, the display device 300 that the present embodiment is provided,
Including substrate 302, pel array 304 and grid electrode drive module 306.Pel array 304 is configured on substrate 302, has multiple
Pixel column 312, towards a preset direction sequential.It addition, grid electrode drive module 306 is also disposed on substrate 302, and join
It is placed in the side of pel array 304.In this example it is shown that device 300 is the framework using monolateral raster data model, but this
Invention is not limited thereto.The present invention can be applied framework aobvious at bilateral raster data model by those skilled in the art voluntarily
On showing device, have no effect on the spirit that the present invention is main.
Fig. 4 is shown as the block chart of a kind of grid electrode drive module of the preferred embodiment according to the present invention, its shown with
The shift register of continuous six grades in one grid electrode drive module.Refer to Fig. 4, it is shown with in grid electrode drive module 306
One shift register the 402, second shift register the 404, the 3rd shift register the 406, the 4th shift register the 408, the 5th moves
Bit register 410 and the 6th shift register 412, these six shift registers are in order to produce gate drive signal G respectively4n、
G4n+1、G4n+2、G4n+3、G4n+4With G4n+5To 4n, 4n+1,4n+2,4n+3,4n+4,4n+5 pixel column.It addition, each displacement
Depositor 402,404,406,408,410 and 412 receives previous stage and the output of rear stage shift register the most respectively.Particularly
It is that input signal B1, B2, B3 and B4 that each shift register receives are independent each other.
Fig. 5 is shown as the circuit diagram of a kind of 3rd shift register of the preferred embodiment according to the present invention.Shown in Fig. 5
The circuit framework of the 3rd shift register 406 being in Fig. 4, this area has the personnel of usual knowledge and is understanding the 3rd displacement
After the mode of operation of depositor 406, the shift register to other grade can be applied voluntarily, due to the shift register of other grade
Circuit framework is all similar with mode of operation with the circuit framework of the 3rd shift register 406 with mode of operation, for simplicity,
Illustrating as a example by the 3rd shift register 406 at this, one skilled in the art can learn the shift LD of other grade whereby
The mode of operation of device.Please merge with reference to Fig. 4 and Fig. 5, the 3rd shift register 406 has on-off circuit 502, output circuit 504
With forbidden energy circuit 506.
On-off circuit 502 has switch 512 and 514.In the present embodiment, switch 512 and 514 is to utilize nmos pass transistor
Realize, but those skilled in the art can replace with PMOS transistor according to practical situation, has no effect on the present invention
Spirit.
In the present embodiment, switch 512 and below 514(represents with transistor 512 and 514) the first source/drain the most common
With input signal B3 coupling correspondence.Wherein, the gate terminal of transistor 512 couples the grid that previous stage shift register is exported
Drive signal G4n+1As an initial signal, the gate terminal of transistor 514 is then coupled to rear stage shift register and is exported
Gate drive signal G4n+3As another initial signal.It addition, the second extreme couple nodes of source/drain of transistor 512 and 514
N1。
Output circuit 504 includes transistor 522, e.g. nmos pass transistor, and its first source/drain extremely couples frequency signal
CK, its second source/drain extremely couples the outfan of the 3rd shift register 406, its gate terminal then couple nodes N1, and leads to
The outfan crossing electric capacity 524 and the 3rd shift register 406 is coupled against each other.
Forbidden energy circuit 506 then includes transistor 532,534,536 and 538(e.g. nmos pass transistor) and electric capacity 540.Brilliant
First source/drain of body pipe 532,534,536 and 538 extremely couples low-voltage Vgl.Wherein, the gate terminal of transistor 532 couples joint
Point N1, its second source/drain extremely couples frequency signal CK by electric capacity 540.It addition, the gate terminal of transistor 534 and 536 is common
The second source/drain being coupled to transistor 532 is extreme, and both the second source/drain are extremely respectively coupled to node N1 and the 3rd
The outfan of shift register 406.Second source/drain of transistor 538 is extremely also coupled to the output of the 3rd shift register 406
End, gate terminal is then coupled to frequency signal XCK.
Fig. 6 is shown as the circuit diagram of a kind of 4th shift register of the preferred embodiment according to the present invention.Shown in Fig. 6
The circuit framework of the 4th shift register 408 being in Fig. 4, those skilled in the art is understanding the 4th shift register
After the mode of operation of 408, the framework of shift register of other grade can be pushed away to obtain voluntarily.Please merge with reference to Fig. 4 and Fig. 6, similarly,
4th shift register 408 also includes on-off circuit 602, output circuit 604 and forbidden energy circuit 606.
On-off circuit 602 also includes switching 612 and 614, and it couples relation can be to equal to switch 512 He in Fig. 5
514.It addition, output circuit 604 also includes transistor 622 and electric capacity 624, it couples relation can be to equal to the crystal in Fig. 5
Pipe 522 and electric capacity 524.Except for the difference that, the first source/drain of transistor 622 is extremely coupled to frequency signal XCK.
Forbidden energy circuit 606 also include transistor 632,634,636,638(e.g. nmos pass transistor) with electric capacity 640, its
Annexation can not repeat them here equal to the transistor 532,534,536,538 in Fig. 5 and electric capacity 540.Different
It is that the first source/drain of transistor 632 is extremely to be coupled to frequency signal XCK, and the grid of transistor 638 by electric capacity 640
End is then coupled to frequency signal CK.
The sequential chart of the signal that Fig. 7 is shown as in Fig. 4, wherein frequency signal CK and XCK is inverting each other.Please merge with reference to figure
4, Fig. 5 and Fig. 7.When 7t1, frequency signal CK and XCK is respectively set at low level and high levels.It addition, input signal B3
It is arranged on high levels.Now, the gate drive signal G of previous stage4n+1For high levels, therefore, transistor 512 can be switched on,
And input signal B3 of high levels is sent to the node N1 of the 3rd shift register 406.Therefore, transistor 522 and 532 all can
Switched on.Owing to transistor 532 is switched on, therefore low-voltage Vgl is carried to the gate terminal of transistor 534 and 536, and
It is turned off.On the other hand, the 3rd displacement because frequency signal XCK is that high levels is switched on, and then can be posted by transistor 538
The outfan of storage 406 is pulled down to low level.
Then, when 7t2, the gate drive signal G of previous stage4n+1And frequency signal XCK pulled down to low level,
Frequency signal CK is then pulled to high levels.Therefore, transistor 512 and 538 all can be closed, and transistor 522 and 532 is then held
Continuous conducting.Owing to frequency signal CK has been pulled to high levels, therefore the 3rd shift register 406 can export tool when 7t2
There is the gate drive signal G of high levels4n+2.When 7t3, frequency signal CK is pulled down to again low level, and frequency signal XCK is then
It is pulled to high levels, therefore gate drive signal G4n+2Just it pulled down to low level.Now, input signal B3 can be pulled down to
Low level.Referring again to Fig. 4, Fig. 6 and Fig. 7, those skilled in the art can push away to obtain the 4th shift LD according to above narration
The mode of operation of device 408, therefore repeats no more.
Sequential as shown in Figure 7 understands, when the gate terminal of the transistor 522 in the shift register of each odd level is filled
When electricity produces according to this to high levels and exports the gate drive signal of correspondence, its corresponding input signal received all presents height
Level, and when the gate terminal of the transistor 622 in the shift register of each even level is charged to high levels and produces according to this
And when exporting the gate drive signal of correspondence, its corresponding input signal received the most all presents high levels.This represents, from arbitrary
The gate terminal of the transistor 522 in the shift register of odd level flows to the leakage current of corresponding input signal, can be equal to from arbitrary
The gate terminal of the transistor 622 in the shift register of even level flows to the leakage current of corresponding input signal.Thus, so that it may
To avoid the situation that band occurs on the picture of display device.
It is noted that in order to ensure each shift register when producing and exporting gate drive signal, it is connect
The corresponding input signal received all presents high levels, the trailing edge of the most each gate drive signal can be set at corresponding defeated
Before entering the trailing edge of signal.As a example by signal shown in Fig. 7, gate drive signal G4n+2Trailing edge can be set at defeated
Before entering the trailing edge of signal B3 so that gate drive signal G4n+2Trailing edge and the trailing edge of input signal B3 between have
One very first time is poor.Similarly, gate drive signal G4n+3Trailing edge can also be the decline being set at input signal B4
Along before so that gate drive signal G4n+3Trailing edge and the trailing edge of input signal B4 between there is one second time difference.
In the present embodiment, this second time difference is poor with the above-mentioned very first time the most equal.In the case of preferably, above-mentioned the
One time difference and the second time difference can be equal to 0.Similarly, the corresponding input signal of other gate drive signal it
Between may be used without identical way.
Owing to, in above embodiment, being to disclose scanning sequency from top to bottom, being properly termed as positive scan pattern.Just
In scan pattern, it is the rising edge of alignment previous stage gate drive signal corresponding to the rising edge of input signal at different levels.Certainly,
The present invention can also be applied under counter-scanning pattern by those skilled in the art, scanning sequency the most from down to up.?
Under counter-scanning pattern, it is the rising edge of alignment rear stage gate drive signal corresponding to the rising edge of input signal at different levels.
Fig. 8 is shown as the steps flow chart of the control method of a kind of display device of the preferred embodiment according to the present invention
Figure.Refer to Fig. 8, the control method provided of the present embodiment, as described in step S802, first produces multiple the most independent defeated
Enter signal to the multiple shift registers in display device, so that the grid that shift register at different levels can produce correspondence respectively drives
Dynamic signal is to multiple pixel columns of display device.Then, as described in step S804, when gate drive signal, one of them is disabled
Time, then close the input signal of correspondence.Certainly, in this control method, may also include the forbidden energy time making each input signal
Lag behind the forbidden energy time of the gate drive signal of correspondence, and produce a forbidden energy time difference；And by each gate drive signal with
The corresponding forbidden energy time difference between input signal is adjusted to identical.
Claims (3)
1. a shift register module, it is characterised in that including:
One first shift register, has:
One first on-off circuit, receives one first input signal, and initiates signal deciding by defeated for this first input signal according to one
Go out；
One first output circuit, couples this first on-off circuit, to receive this first input signal, when this first input signal
When level is switched to first level, this first output circuit is by defeated from this first shift register of a first frequency signal
Go out end output, to produce one first driving signal；And
One first forbidden energy circuit, couples this first on-off circuit, determines with the state according to the outfan of this first on-off circuit
Determine this first driving signal of forbidden energy；
One second shift register, has:
One second switch circuit, receives one second input signal independent of this first input signal, and according to this first driving
Signal and determine by this second input signal export；
One second output circuit, couples this second switch circuit, to receive this second input signal, when this second input signal
When level is switched to this first level, this second output circuit is by defeated from this second shift register of a second frequency signal
Going out end output, to produce a two driving signal, and this second frequency signal is the most anti-phase with this first frequency signal；And
One second forbidden energy circuit, couples this second switch circuit, determines with the state according to the outfan of this second switch circuit
Determine this two driving signal of forbidden energy；
One the 3rd shift register, has:
One the 3rd on-off circuit, receives one the 3rd input signal independent of this first input signal Yu this second input signal,
And determine the 3rd input signal output according to this two driving signal；
One the 3rd output circuit, couples the 3rd on-off circuit, to receive the 3rd input signal, when the 3rd input signal
When level is switched to this first level, the 3rd output circuit is by defeated from the 3rd shift register of this first frequency signal
Go out end output, to produce one the 3rd driving signal；And
One the 3rd forbidden energy circuit, couples the 3rd on-off circuit, determines with the state according to the outfan of the 3rd on-off circuit
Determine forbidden energy the 3rd and drive signal；And
One the 4th shift register, has:
One the 4th on-off circuit, receives independent of this first input signal, this second input signal and the 3rd input signal
One the 4th input signal, and drive signal to determine the 4th input signal output according to the 3rd；
One the 4th output circuit, couples the 4th on-off circuit, to receive the 4th input signal, when the 4th input signal
When level is switched to this first level, then the 4th output circuit by this second frequency signal from the 4th shift register
Outfan exports, to produce a fourth drive signal；And
One the 4th forbidden energy circuit, couples the 4th on-off circuit, determines with the state according to the outfan of the 4th on-off circuit
Determine this fourth drive signal of forbidden energy.
Shift register module the most according to claim 1, it is characterised in that the trailing edge of this first driving signal is at this
Before the trailing edge of the first input signal, and both to have a very first time poor, the trailing edge of this two driving signal this
Before the trailing edge of two input signals, and both have one second time difference, and wherein this second time difference is poor with this very first time
The most equal.
Shift register module the most according to claim 2, it is characterised in that this very first time difference and this second time difference
It is substantially equal to 0.
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| TW102121767 | 2013-06-19 | ||
| TW102121767A TWI550622B (en) | 2013-06-19 | 2013-06-19 | Display device control method and a shift register module adapted the method |
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| CN103745680B true CN103745680B (en) | 2016-08-17 |
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| TWI559276B (en) * | 2015-03-18 | 2016-11-21 | 友達光電股份有限公司 | Shift register circuit |
| TWI588699B (en) * | 2015-10-13 | 2017-06-21 | 友達光電股份有限公司 | Touch display apparatus and shift register thereof |
| CN105931601B (en) * | 2016-06-28 | 2018-07-20 | 华南理工大学 | A kind of drive circuit unit and its driving method and row grid-driving integrated circuit |
| CN113823213B (en) * | 2021-10-26 | 2024-01-26 | 京东方科技集团股份有限公司 | Gate driving circuit, display substrate and display device |
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|---|---|
| TW201501128A (en) | 2015-01-01 |
| CN103745680A (en) | 2014-04-23 |
| TWI550622B (en) | 2016-09-21 |
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