CN103745680A - Shift register module and control method thereof - Google Patents
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Abstract
The invention provides a shift register module and a control method thereof, and the shift register module comprises: a first shift register, a second shift register, a third shift register and a fourth shift register. The first shift register receives a first input signal to generate a first driving signal; the second shift register receives a second input signal independent of the first input signal and generates a second driving signal; the third shift register receives a third input signal independent of the first input signal and the second input signal and generates a third driving signal; the fourth shift register receives a fourth input signal independent of the first input signal, the second input signal, and the third input signal, and outputs a fourth driving signal. In addition, a control method corresponding to the shift register module is also provided.
Description
Technical field
The present invention relates to a kind of circuit of shift register, especially relate to a kind of circuit of the shift register for display device.
Background technology
Fig. 1 is depicted as the calcspar of existing grid electrode drive module.Please refer to Fig. 1, existing grid electrode drive module 100 goes for a display device, and it comprises multiple shift registers, and for example 102,104,106 and 108.In addition,, in Fig. 1, sign Vst is expressed as start signal, sign CK and XCK and is all expressed as frequency signal, indicates Bi
1and Bi
2all be expressed as input signal, and indicate G
n-1, G
n, G
n+1and G
n+2all be expressed as gate drive signal.In addition, each shift register all has three transistors, indicates respectively with M1, M2 and M3.With the example that is operating as of shift register 102, the gate terminal of its transistor M1 and M2 receives respectively start signal Vst and gate drive signal G
n, and whether determine by input signal Bi according to this
1be sent to the gate terminal of transistor M3, so that the gate terminal of transistor M3 is charged.Transistor M3 in shift register 102 determines whether frequency signal CK to be sent to the output terminal of shift register 102 according to the voltage swing of its gate terminal, to form gate drive signal G
n-1.As for the operation of shift register 104～108, this area have common knowledge personnel Ke Yi aforementioned shift register 102 mode of operation and push away, at this, just repeat no more.
From the grid electrode drive module 100 shown in Fig. 1, shift register 102 and 104 receives same input signal Bi
1, shift register 106 and 108 receives same input signal Bi
2.This means, same input signal provides to the shift register of continuous adjacent two-stage.But such way can make picture occur obvious band, illustrates with Fig. 2.Fig. 2 is depicted as the sequential chart of the main signal of the grid electrode drive module of Fig. 1.In Fig. 2, indicate the sign person who is same as in Fig. 1 and be expressed as same signal.In addition,, in Fig. 2, indicate G
n-1_ NODE1 represents the voltage swing of the gate terminal of the transistor M3 in shift register 102, and G
n_ NODE1 represents the voltage swing of the gate terminal of the transistor M3 in shift register 104.As shown in Figure 2, when the gate terminal of the transistor M3 in shift register 102 is charged to high levels (as indicate G
n-1shown in _ NODE1), shift register 102 can corresponding produce and export gate drive signal G
n-1, and when the gate terminal of the transistor M3 in shift register 104 is charged to high levels (as indicate G
nshown in _ NODE1), shift register 104 can corresponding produce and export gate drive signal G
n.When the gate terminal of the transistor M3 in shift register 102 and 104 is charged to high levels, corresponding transistor M1 and M2 just can be closed, but while being charged to high levels due to the gate terminal of the transistor M3 in shift register 102, input signal Bi
1present high levels, and the gate terminal of transistor M3 in shift register 104 is while being charged to high levels, input signal Bi
1present low level, thereby cause the gate terminal of the transistor M3 in shift register 104 to flow to input signal Bi
1leakage current, can flow to input signal Bi much larger than the gate terminal of the transistor M3 in shift register 102
1leakage current.Thus, will cause gate drive signal G
n-1with G
nthe two pulse has not coordination accurate fall time, and then makes to produce obvious band on the picture of display device.Similarly, shift register 106 also has identical situation with 108.
Summary of the invention
In view of this, the invention provides a kind of shift register module, can be applied to display device, to avoid the above-mentioned situation that band occurs in display device.
The present invention also provides a kind of display device, can avoid the above-mentioned situation that produces band on picture.
In addition, the present invention also provides a kind of control method of display device, can avoid above-mentioned band on the picture of display device.
Shift register module provided by the present invention, comprises one first shift register, one second shift register, one the 3rd shift register and one the 4th shift register, and this has respectively on-off circuit, output circuit and forbidden energy circuit.In the first shift register, on-off circuit can receive the first input signal, and according to an initial signal deciding, the first input signal is exported.Output circuit is to couple on-off circuit, to receive from the first input signal of on-off circuit output.When the position of the first input signal standard is switched to one first on time, output circuit can be exported first frequency signal from the output terminal of the first shift register, to produce one first, drives signal.In addition, forbidden energy circuit also can couple on-off circuit, with the state of the output terminal according to on-off circuit, determines that forbidden energy first drives signal.The framework of the second shift register is identical haply with the framework of the first shift register.Different, the on-off circuit in the second shift register can receive the second input signal that is independent of the first input signal, so that the second shift register output two driving signal.The framework of the 3rd shift register is identical haply with the framework of the first shift register and the second shift register.Different, the on-off circuit in the 3rd shift register can receive the 3rd input signal that is independent of the first input signal and the second input signal, so that the 3rd shift register output the 3rd drives signal.The framework of the 4th shift register is identical haply with the framework of the first shift register, the second shift register and the 3rd shift register.Different, the on-off circuit in the 4th shift register can receive the 4th signal that is independent of the first input signal, the second input signal and the 3rd input signal, so that the moving signal of the 4th shift register output 4 wheel driven.
From another viewpoint, display device provided by the present invention, comprises substrate, pel array, the first shift register, the second shift register, the 3rd shift register and the 4th shift register.Pel array is formed on substrate, and has multiple pixel columns.Similarly, the first shift register, the second shift register, the 3rd shift register and the 4th shift register are also all formed on substrate.Wherein, the first shift register produces corresponding gate drive signal according to corresponding input signal.The second shift register produces corresponding gate drive signal according to corresponding input signal.The 3rd shift register produces corresponding gate drive signal according to corresponding input signal.The 4th shift register produces corresponding gate drive signal according to corresponding input signal.Wherein, first, second, third and the 4th the input signal that receives of shift register independent separately.
From another viewpoint, the control method of display device provided by the present invention, comprise produce multiple separately independently input signal to the multiple shift registers in display device so that each shift register respectively corresponding produce multiple gate drive signals to the multiple pixel columns in display device one of them; And when when gate drive signal, one of them is disabled, input signal corresponding to forbidden energy.
The invention provides multiple mutual independently input signals uses to the shift register in shift register module, therefore as long as the sequential of these input signals is carried out to suitable design, just can make each shift register when producing and export gate drive signal, the received input signal of each shift register all can present high levels.Thus, just can avoid the situation that on the picture of display device, band produces.
Accompanying drawing explanation
Fig. 1 is depicted as the calcspar of existing grid electrode drive module;
Fig. 2 is depicted as the sequential chart of the main signal of the grid electrode drive module of Fig. 1;
Fig. 3 is depicted as a kind of Organization Chart of display device;
Fig. 4 is depicted as the calcspar according to a kind of grid electrode drive module of a preferred embodiment of the present invention;
Fig. 5 is depicted as the circuit diagram according to a kind of the 3rd shift register of a preferred embodiment of the present invention;
Fig. 6 is depicted as the circuit diagram according to a kind of the 4th shift register of a preferred embodiment of the present invention;
Fig. 7 is depicted as the sequential chart of the signal in Fig. 4;
Fig. 8 is depicted as the flow chart of steps according to the control method of a kind of display device of a preferred embodiment of the present invention.
Reference numeral
100,306: grid electrode drive module
102,104,106,108,402,404,406,408,410,412: shift register
300: display device 302: substrate
304: pel array 312: pixel column
502,602: on-off circuit 504,604: output circuit
506,604,606: forbidden energy circuit 512,514,612,614: switch
522,532,534,536,538,622,632,634,636,638, M1, M2, M3: transistor
524,540,624,640: electric capacity
Bi
1, Bi
2, B1, B2, B3, B4: input signal
CK, XCK: frequency signal
G
n-1, G
n, G
n+1, G
n+2, G
4n-1, G
4n, G
4n+1, G
4n+2, G
4n+3, G
4n+4, G
4n+5: gate drive signal
Vst: start signal
S802, S804: the steps flow chart of the control method of display device
2t1,2t2,7t1,7t2,7t3: time point
G
n-1_ NODE1, G
n_ NODE1: the voltage swing of the gate terminal of transistor M3
N1: node Vgl: low-voltage
Embodiment
Fig. 3 is depicted as a kind of Organization Chart of display device.Please refer to Fig. 3, the display device 300 that the present embodiment provides, comprises substrate 302, pel array 304 and grid electrode drive module 306.Pel array 304 is disposed on substrate 302, has multiple pixel columns 312, towards a preset direction, sequentially arranges.In addition, grid electrode drive module 306 is to be also configured on substrate 302, and is disposed at a side of pel array 304.In the present embodiment, display device 300 is the frameworks that adopt monolateral grid to drive, but the present invention is not as limit.Those skilled in the art can be applied in the present invention in the display device of framework of bilateral grid driving voluntarily, does not affect the main spirit of the present invention.
Fig. 4 is depicted as the calcspar according to a kind of grid electrode drive module of a preferred embodiment of the present invention, and it is shown with the shift register of continuous six grades in a grid electrode drive module.Please refer to Fig. 4, it is shown with the first shift register 402, the second shift register 404, the 3rd shift register 406, the 4th shift register 408, the 5th shift register 410 and the 6th shift register 412 in grid electrode drive module 306, and these six shift registers are in order to produce respectively gate drive signal G
4n, G
4n+1, G
4n+2, G
4n+3, G
4n+4with G
4n+5give 4n, 4n+1,4n+2,4n+3,4n+4, a 4n+5 pixel column.In addition, each shift register 402,404,406,408,410 and 412 also receives respectively the output of previous stage and rear one-level shift register.Specifically, input signal B1, B2, B3 and the B4 that each shift register receives is independent each other.
Fig. 5 is depicted as the circuit diagram according to a kind of the 3rd shift register of a preferred embodiment of the present invention.Shown in Fig. 5, be the circuit framework of the 3rd shift register 406 in Fig. 4, the personnel that this area has common knowledge are understanding after the mode of operation of the 3rd shift register 406, can be applied to voluntarily the shift register of other grade, because circuit framework and the mode of operation of the shift register of other grade are all similar with circuit framework and the mode of operation of the 3rd shift register 406, for simplicity, at this, as an example of the 3rd shift register 406 example, illustrate, person skilled in the art person can learn the mode of operation of the shift register of other grade whereby.Please merge with reference to Fig. 4 and Fig. 5, the 3rd shift register 406 has on-off circuit 502, output circuit 504 and forbidden energy circuit 506.
On-off circuit 502 has switch 512 and 514.In the present embodiment, switch 512 and 514 is to utilize nmos pass transistor to realize, but those skilled in the art can replace with according to actual conditions PMOS transistor, does not affect spirit of the present invention.
In the present embodiment, switch 512 and 514(are following represents with transistor 512 and 514) the first source/drain electrode end jointly couple corresponding input signal B3.Wherein, the gate terminal of transistor 512 couples the gate drive signal G that previous stage shift register is exported
4n+1be used as a start signal, the gate terminal of transistor 514 is to couple the gate drive signal G that rear one-level shift register is exported
4n+3be used as another start signal.In addition, the second source/drain electrode end of transistor 512 and 514 couples node N1.
506, forbidden energy circuit comprises that transistor 532,534,536 and 538(are for example nmos pass transistors) and electric capacity 540.The the first source/drain electrode end of transistor 532,534,536 and 538 couples low-voltage Vgl.Wherein, the gate terminal of transistor 532 couples node N1, and its second source/drain electrode end couples frequency signal CK by electric capacity 540.In addition, the gate terminal of transistor 534 and 536 is coupled to the second source/drain electrode end of transistor 532 jointly, and both the second source/drain electrode ends are coupled to respectively the output terminal of node N1 and the 3rd shift register 406.The the second source/drain electrode end of transistor 538 also couples the output terminal of the 3rd shift register 406, and gate terminal is coupled to frequency signal XCK.
Fig. 6 is depicted as the circuit diagram according to a kind of the 4th shift register of a preferred embodiment of the present invention.Shown in Fig. 6, be the circuit framework of the 4th shift register 408 in Fig. 4, those skilled in the art is understanding after the mode of operation of the 4th shift register 408, can push away voluntarily to obtain the framework of shift register of other grade.Please merge with reference to Fig. 4 and Fig. 6, similarly, the 4th shift register 408 also comprises on-off circuit 602, output circuit 604 and forbidden energy circuit 606.
On-off circuit 602 also comprises switch 612 and 614, and it couples relation can be to equaling the switch 512 and 514 in Fig. 5.In addition, output circuit 604 also comprises transistor 622 and electric capacity 624, and it couples relation can be to equaling transistor 522 and the electric capacity 524 in Fig. 5.Different, the first source/drain electrode end of transistor 622 is to couple frequency signal XCK.
Fig. 7 is depicted as the sequential chart of the signal in Fig. 4, and wherein frequency signal CK and XCK are inverting each other.Please merge with reference to Fig. 4, Fig. 5 and Fig. 7.When 7t1, frequency signal CK and XCK are arranged on respectively low level and high levels.In addition, input signal B3 is arranged on high levels.Now, the gate drive signal G of previous stage
4n+1for high levels, therefore, transistor 512 can be switched on, and the input signal B3 of high levels is sent to the node N1 of the 3rd shift register 406.Therefore, transistor 522 and 532 all can be switched on.Because transistor 532 is switched on, therefore low-voltage Vgl will be sent to the gate terminal of transistor 534 and 536, and is closed.On the other hand, transistor 538 can be that high levels is switched on because of frequency signal XCK, and then the output terminal of the 3rd shift register 406 is pulled down to low level.
Then, when 7t2, the gate drive signal G of previous stage
4n+1and frequency signal XCK pulled down to low level, frequency signal CK is pulled to high levels.Therefore, transistor 512 and 538 all can be closed, lasting conducting of transistor 522 and 532.Because frequency signal CK has been pulled to high levels, therefore the 3rd shift register 406 can be exported the gate drive signal G with high levels when 7t2
4n+2.When 7t3, frequency signal CK is pulled down to again low level, and frequency signal XCK is pulled to high levels, therefore gate drive signal G
4n+2just pulled down to low level.Now, input signal B3 can be pulled down to low level.Referring again to Fig. 4, Fig. 6 and Fig. 7, those skilled in the art can be according to above narration, pushes away to obtain the mode of operation of the 4th shift register 408, therefore repeats no more.
Sequential is as shown in Figure 7 known, when the gate terminal of the transistor 522 in the shift register of each odd level is charged to high levels and produces according to this and export corresponding gate drive signal, its the corresponding input signal receiving all present high levels, and be charged to high levels and when producing according to this and exporting corresponding gate drive signal when the gate terminal of the transistor 622 in the shift register of each even level, its corresponding input signal receiving also all present high levels.This expression, the gate terminal of the transistor 522 in the shift register of arbitrary odd level flows to the leakage current of corresponding input signal, and the gate terminal that can equal the transistor 622 in the shift register of arbitrary even level flows to the leakage current of corresponding input signal.Thus, just can avoid occurring on the picture of display device the situation of band.
It is worth mentioning that, in order to ensure each shift register when producing and export gate drive signal, its corresponding input signal receiving all presents high levels, therefore the negative edge of each gate drive signal can be set at the negative edge of corresponding input signal before.Take signal shown in Fig. 7 as example, gate drive signal G
4n+2negative edge can be set at the negative edge of input signal B3 before, make gate drive signal G
4n+2negative edge and the negative edge of input signal B3 between to have a very first time poor.Similarly, gate drive signal G
4n+3negative edge can be also set at the negative edge of input signal B4 before, make gate drive signal G
4n+3negative edge and the negative edge of input signal B4 between there is for one second mistiming.In the present embodiment, this second mistiming equates haply with above-mentioned very first time difference.In situation preferably, poor and the second mistiming above-mentioned very first time can equal 0.Similarly, other gate drive signal and its corresponding input signal between also can adopt identical way.
Due in above embodiment, be the scanning sequency disclosing from top to bottom, can be called positive scan pattern.In positive scan pattern, it corresponding to the rising edge of input signal at different levels, is the rising edge of alignment previous stage gate drive signal.Certainly, those skilled in the art also can be applied in the present invention under counter-scanning pattern, namely scanning sequency from down to up.Under counter-scanning pattern, it corresponding to the rising edge of input signal at different levels, is the rising edge of the rear one-level gate drive signal of alignment.
Fig. 8 is depicted as the flow chart of steps according to the control method of a kind of display device of a preferred embodiment of the present invention.Please refer to Fig. 8, the control method providing of the present embodiment is as described in step S802, first produce multiple separately independently input signal to the multiple shift registers in display device, so that shift register at different levels can produce respectively the multiple pixel columns of corresponding gate drive signal to display device.Then,, as described in step S804, when one of them is disabled when gate drive signal, close corresponding input signal.Certainly, in this control method, also can comprise that the forbidden energy time-lag that makes each input signal is in the forbidden energy time of corresponding gate drive signal, and produce a forbidden energy mistiming; And the forbidden energy mistiming between each gate drive signal and corresponding input signal is adjusted into identical.
Claims (7)
1. a shift register module, is characterized in that, comprising:
One first shift register, has:
One first on-off circuit, receives one first input signal, and according to an initial signal deciding, this first input signal is exported;
One first output circuit, couple this first on-off circuit, to receive this first input signal, when the position of this first input signal standard is switched to one first on time, this first output circuit is the output terminal output from this first shift register by a first frequency signal, to produce one first, drives signal; And
One first forbidden energy circuit, couples this first on-off circuit, determines this first driving signal of forbidden energy with the state of the output terminal according to this first on-off circuit;
One second shift register, has:
One second switch circuit, receives one second input signal that is independent of this first input signal, and determines this second input signal output according to this first driving signal;
One second output circuit, couple this second switch circuit, to receive this second input signal, when the position of this second input signal standard is switched to this first on time, this second output circuit is the output terminal output from this second shift register by a second frequency signal, to produce a two driving signal, and this second frequency signal and this first frequency signal are anti-phase each other; And
One second forbidden energy circuit, couples this second switch circuit, with the state of the output terminal according to this second switch circuit, determines this two driving signal of forbidden energy;
One the 3rd shift register, has:
One the 3rd on-off circuit, receives and is independent of one the 3rd input signal of this first input signal and this second input signal, and according to this two driving signal, determines the 3rd input signal output;
One the 3rd output circuit, couple the 3rd on-off circuit, to receive the 3rd input signal, when the position standard of the 3rd input signal is switched to this first on time, the 3rd output circuit is the output terminal output from the 3rd shift register by this first frequency signal, to produce one the 3rd, drives signal; And
One the 3rd forbidden energy circuit, couples the 3rd on-off circuit, determines that forbidden energy the 3rd drives signal with the state of the output terminal according to the 3rd on-off circuit; And
One the 4th shift register, has:
One the 4th on-off circuit, receives one the 4th input signal that is independent of this first input signal, this second input signal and the 3rd input signal, and determines the 4th input signal output according to the 3rd driving signal;
One the 4th output circuit, couple the 4th on-off circuit, to receive the 4th input signal, when the position standard of the 4th input signal is switched to this first on time, the 4th output circuit output terminal output from the 4th shift register by this second frequency signal, to produce the moving signal of a 4 wheel driven; And
One the 4th forbidden energy circuit, couples the 4th on-off circuit, with the state of the output terminal according to the 4th on-off circuit, determines that this 4 wheel driven of forbidden energy moves signal.
2. shift register module according to claim 1, it is characterized in that, the negative edge of this first driving signal is before the negative edge of this first input signal, and it is poor that both have a very first time, the negative edge of this two driving signal is before the negative edge of this second input signal, and both had for one second mistiming, wherein this second mistiming equates haply with this very first time difference.
3. shift register module according to claim 2, is characterized in that, this very first time difference and this second mistiming equal in fact 0.
4. a control method for display device, is characterized in that, this display device has multiple pixel columns sequentially arranges, and this control method comprises the following steps:
Produce multiple separately independently input signal to the multiple shift registers in this display device, so that respectively this shift register can produce multiple gate drive signals to each those pixel column according to received frequency signal; And
When those gate drive signals, one of them is disabled, input signal corresponding to forbidden energy.
5. the control method of display device according to claim 4, is characterized in that, also comprises:
Make the forbidden energy time-lag of each this input signal in the forbidden energy time of corresponding gate drive signal, and there is a forbidden energy mistiming; And
The forbidden energy mistiming between each those gate drive signal and corresponding input signal is adjusted into identical.
6. the control method of display device according to claim 4, is characterized in that, respectively the rising edge of this input signal rising edge of previous gate drive signal that aligns respectively.
7. the control method of display device according to claim 4, is characterized in that, respectively the rising edge of this input signal rising edge of next gate drive signal that aligns respectively.
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|---|---|---|---|
| TW102121767 | 2013-06-19 | ||
| TW102121767A TWI550622B (en) | 2013-06-19 | 2013-06-19 | Display device control method and a shift register module adapted the method |
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| CN103745680B CN103745680B (en) | 2016-08-17 |
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Also Published As
| Publication number | Publication date |
|---|---|
| TW201501128A (en) | 2015-01-01 |
| CN103745680B (en) | 2016-08-17 |
| TWI550622B (en) | 2016-09-21 |
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