CN101620334B - Display and shift register device thereof - Google Patents
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- CN101620334B CN101620334B CN2009101605617A CN200910160561A CN101620334B CN 101620334 B CN101620334 B CN 101620334B CN 2009101605617 A CN2009101605617 A CN 2009101605617A CN 200910160561 A CN200910160561 A CN 200910160561A CN 101620334 B CN101620334 B CN 101620334B
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Abstract
The invention relates to a display and a shift register device thereof. The display comprises a display panel, a first shift register device and a second shift register device, wherein the display panel is provided with a plurality of pixels aligned by matrixes, and the first shift register device and the second shift register device are directly arranged on a glass basal plate of the display panel; only one of the first shift register device and the second shift register device normally works in a moment; a sequence outputs a scanning signal when the first shift register device normally works so that the pixels are started from the first column to the last column one by one; and the sequence outputs the scanning signal when the second shift register device normally works so that the pixels are started from the last column to the first column one by one.
Description
[technical field]
The invention relates to a kind of plane display technique, and particularly relevant for a kind of LCD and shift register device thereof.
[background technology]
In recent years, along with semiconductor science and technology is flourish, portable type electronic product and flat-panel screens product also with rise.And in the middle of the type of numerous flat-panel screens, (LiquidCrystal Display LCD) based on advantage such as its low voltage operating, radiationless line scattering, in light weight and volume be little, has become the main flow of each display product to LCD immediately.Also, ordering about each tame manufacturer invariably and will hang down the cost of manufacture development towards more microminiaturized reaching to the development technique of LCD also because of so.
In order to reduce the cost of manufacture of LCD; Existing partly manufacturer develops at display panels and adopts amorphous silicon (amorphous silicon; A-Si) under the condition of processing procedure, offset buffer (shiftregister) transfer that can the employed turntable driving IC of the scan-side that originally was disposed at display panels is inner directly is configured on the glass substrate (glass substrate) of display panels.Therefore, the employed turntable driving IC of scan-side that originally was disposed at display panels can omit, and uses the purpose that reaches the cost of manufacture that reduces LCD.
Yet; Directly be configured in the multistage offset buffer on the glass substrate of display panels; Only can be opened into last row pixel with the first row pixel by output one scan signal from top to bottom, and can't be opened into the first row pixel with last row pixel by output one scan signal from the bottom to top by display panels by display panels.In other words, the multistage offset buffer on the existing glass substrate that directly is configured in display panels only has the forward function (forward scan function) of scanning, and does not have the function (reverse scan function) of reverse scanning.
[summary of the invention]
In view of this, the present invention provides a kind of display, and it comprises display panel and first and second shift register device.Display panel has a plurality of pixels with arranged, and first and second shift register device both all directly be configured on the glass substrate of display panel.Wherein, First and second shift register device only has normal operations in the same time; And when the first shift register device normal operation; Sequence output one scan signal is being opened into last row pixel from the first row pixel one by one, and when the second shift register device normal operation, sequence is exported said sweep signal to be opened into the first row pixel one by one from last row pixel.
The present invention provides a kind of shift register device in addition, and it comprises the offset buffer that the multi-level pmultistage circuit framework is identical in fact and be serially connected each other.Wherein, i level offset buffer comprises first to the 5th transistor, electric capacity, and drop-down unit, and i is a positive integer.The grid of the first transistor is coupled in drain electrode, to receive an activation signal.The grid of transistor seconds couples the source electrode of the first transistor, and the drain electrode of transistor seconds is in order to receive first clock signal or gate pole shutdown signal, and the source electrode of transistor seconds is then in order to export said sweep signal.Electric capacity is coupled between the grid and source electrode of transistor seconds.
Drop-down unit couples first and second transistorized source electrode; Differ from first and second clock signal of 180 degree or receive said grid shutdown signal simultaneously in order to receiving phase respectively; And when i level offset buffer is not exported said sweep signal, the source electrode of transistor seconds is coupled to a reference voltage.The 3rd transistorized grid is in order to receive the output of (i+1) level offset buffer, and the 3rd transistor drain couples the source electrode of transistor seconds, and the 3rd transistorized source electrode then is coupled to said reference voltage.
The 4th transistorized grid couples the 3rd transistorized grid, and the 4th transistor drain couples the grid of transistor seconds, and the 4th transistorized source electrode then is coupled to said reference voltage.The 5th transistorized grid is in order to receive a grid start signal or said grid shutdown signal, and the 5th transistor drain couples the grid of transistor seconds, and the 5th transistorized source electrode then is coupled to said reference voltage.
The present invention provides a kind of shift register device again, and it comprises the offset buffer that the multi-level pmultistage circuit framework is identical in fact and be serially connected each other.Wherein, i level offset buffer comprises first to the 8th transistor, electric capacity, and drop-down unit.The grid of the first transistor is coupled in to receive an activation signal with drain electrode.The grid of transistor seconds couples the source electrode of the first transistor, and the drain electrode of transistor seconds is in order to receive first clock signal or gate pole shutdown signal, and the source electrode of transistor seconds is then in order to export said sweep signal.Electric capacity is coupled between the grid and source electrode of transistor seconds.
Drop-down unit couples first and second transistorized source electrode; Differ from first and second clock signal of 180 degree or receive said grid shutdown signal simultaneously in order to receiving phase respectively; And when i level offset buffer is not exported said sweep signal, the source electrode of transistor seconds is coupled to a reference voltage.The 3rd transistorized grid is in order to receive the output of (i+1) level offset buffer, and the 3rd transistor drain couples the source electrode of transistor seconds, and the 3rd transistorized source electrode then is coupled to said reference voltage.The 4th transistorized grid couples the 3rd transistorized grid, and the 4th transistor drain couples the grid of transistor seconds, and the 4th transistorized source electrode then is coupled to said reference voltage.
The 5th transistorized grid is coupled in to receive said grid shutdown signal with drain electrode, perhaps during every N picture of said display, receives the one of which of said grid start signal and grid shutdown signal.The 6th transistorized grid couples the 5th transistorized source electrode, and the 6th transistor drain couples the grid of transistor seconds, and the 6th transistorized source electrode then is coupled to said reference voltage.The 7th transistorized grid is coupled in to receive said grid shutdown signal with drain electrode, perhaps during every N picture of said display, receives another of said grid start signal and grid shutdown signal.The 8th transistorized grid couples the 7th transistorized source electrode, and the 8th transistor drain couples the grid of transistor seconds, and the 8th transistorized source electrode then is coupled to said reference voltage.I, N are positive integer.
Will be appreciated that above-mentioned general description and following embodiment are merely exemplary and illustrative, it can not limit the scope that institute of the present invention desire is advocated.
[description of drawings]
Fig. 1 illustrates the system block diagrams into the LCD 100 of the present invention's one example embodiment.
Fig. 2 A and Fig. 2 B illustrate respectively and are the shift register device SRD1 of the present invention's one example embodiment and the calcspar of SRD2.
Fig. 3 illustrates the offset buffer SR into the present invention's one example embodiment
i/ SR '
iCircuit diagram.
Fig. 4 illustrates the offset buffer SR into another example embodiment of the present invention
i/ SR '
iCircuit diagram.
[primary clustering symbol description]
100: LCD
101: display panel
103: source electrode driver
105: timing control unit
107: backlight module
301: drop-down unit
AA: viewing area
SRD1, SRD2: shift register device
T1 ~ T5: transistor
C: electric capacity
STV: start signal
AS: initiating signal
CK, XCK: clock signal
V
GH: the grid start signal
V
GL: the grid shutdown signal
SR
1~ SR
N, SR '
1~ SR '
N: offset buffer
SS
1~ SS
N, SS '
1~ SS '
N: sweep signal
[embodiment]
Existing with detailed reference example embodiment of the present invention, the instance of said example embodiment will be described in the accompanying drawings.In addition, all possible locating, the identical or similar portions of assembly/member/symbology of use same numeral in graphic and embodiment.
Fig. 1 illustrates the system block diagrams into the LCD 100 of the present invention's one example embodiment.Please with reference to Fig. 1, LCD 100 comprises display panel 101, source electrode driver 103, timing control unit 105, and in order to the backlight module 107 of the required backlight of display panel 101 to be provided.Have a plurality of pixels (representing with M*N among the figure that for example 1024*768, and M and N are all positive integer) in the viewing area AA of display panel 101 with arranged.In addition, the left and right sides on the glass substrate of display panel 101 (not illustrating) directly disposes shift register device SRD1 and SRD2 more respectively, and the running of these two shift register device SRD1 and SRD2 system is controlled by timing control unit 105.
In this example embodiment, shift register device SRD1 and SRD2 only have normal operations in the same time, and when shift register device SRD1 normal operation, sequence output one scan signal SS
1~ SS
NThe first row pixel with in the AA of viewing area is opened into last row pixel one by one, and when shift register device SRD2 often operates, sequence output one scan signal SS '
1~ SS '
NLast row pixel with in the AA of viewing area is opened into the first row pixel one by one.In other words, shift register device SRD1 has the forward function (forward scan function) of scanning, and shift register device SRD2 has the function (reverse scan function) of reverse scanning.
Clearer, Fig. 2 A and Fig. 2 B illustrate respectively and are the shift register device SRD1 of the present invention's one example embodiment and the calcspar of SRD2.Please merge with reference to Fig. 1, Fig. 2 A and Fig. 2 B, shift register device SRD1 comprises the offset buffer SR that N level circuit framework is identical in fact and be serially connected each other
1~ SR
N, and shift register device SRD2 comprises the offset buffer SR ' that N level circuit framework is identical in fact and be serially connected each other equally
1~ SR '
NIn this example embodiment, because offset buffer SR
1~ SR
NWith SR '
1~ SR '
NCircuit framework identical in fact, so at this only to i offset buffer SR
i/ SR '
iDo explanation as follows.
Fig. 3 illustrates the offset buffer SR into the present invention's one example embodiment
i/ SR '
iCircuit diagram.Please merge with reference to Fig. 1 ~ Fig. 3 offset buffer SR
i/ SR '
i Comprise transistor T 1 ~ T5, capacitor C, and drop-down unit 301.Wherein, the grid of transistor T 1 is coupled in drain electrode, in order to receive activation signal AS.In this example embodiment, except the 1st grade of offset buffer SR
1/ SR '
1In the activation signal AS that grid received of transistor T 1 be outside the start signal STV that exported of timing control unit 105, all the other offset buffer SR
i/ SR '
i(the activation signal AS that grid received of the transistor T 1 among the i=2 ~ N) is upper level offset buffer SR
I-1/ SR '
I-1The sweep signal SS that is exported
I-1/ SS '
I-1
For instance, offset buffer SR
2/ SR '
2In the activation signal AS that grid received of transistor T 1 be offset buffer SR
1/ SR '
1The sweep signal SS that is exported
1/ SS '
1, and offset buffer SR
3/ SR '
3In the activation signal AS that grid received of transistor T 1 be offset buffer SR
2/ SR '
2The sweep signal SS that is exported
2/ SS '
2, please the rest may be inferred to offset buffer SR
N/ SR '
NIn the activation signal AS that grid received of transistor T 1 be offset buffer SR
N-1/ SR '
N-1The sweep signal SS that is exported
N-1/ SS '
N-1
Please continue with reference to Fig. 3, the grid of transistor T 2 couples the source electrode of transistor T 1, and the drain electrode of transistor T 2 is in order to receive clock signal CK or the gate pole shutdown signal V that timing control unit 105 is provided
GL(for example be-10V, but be not restricted to this), the source electrode of transistor T 2 are then in order to output scanning signal SS
i/ SS '
iCapacitor C is coupled between the grid and source electrode of transistor T 2.Drop-down unit 301 couples the source electrode of transistor T 1 and T2, perhaps receives the grid shutdown signal V that is provided by timing control unit 105 simultaneously in order to clock signal CK and the XCK that receives phase differential 180 degree that provided by timing control unit 105 respectively
GLDrop-down unit 301 can be in offset buffer SR
i/ SR '
iShould not output scanning signal SS
i/ SS '
iThe time, the source electrode of transistor T 2 is coupled to reference voltage VSS (for example be earthing potential, but be not restricted to this).
The grid of transistor T 3 is in order to receive offset buffer SR
I+1/ SR '
I+1The sweep signal SS that is exported
I+1/ SS '
I+1, the drain electrode of transistor T 3 couples the source electrode of transistor T 2, and the source electrode of transistor T 3 then is coupled to reference voltage VSS.The grid of transistor T 4 couples the grid of transistor T 3, and the drain electrode of transistor T 4 couples the grid of transistor T 2, and the source electrode of transistor T 4 then is coupled to reference voltage VSS.The grid of transistor T 5 is in order to receive the grid start signal V that is provided by timing control unit 105
GH(for example being 25V) or gate pole shutdown signal V
GL, the drain electrode of transistor T 5 couples the grid of transistor T 2, and the source electrode of transistor T 5 then is coupled to reference voltage VSS.
In this example embodiment, when the grid of transistor T 5 receives the grid shutdown signal V that is provided by timing control unit 105
GLThe time, the drain electrode of transistor T 2 can receive clock signal CK, and drop-down unit 301 respectively receiving phase differ from the clock signal CK and the XCK of 180 degree.But, when the grid of transistor T 5 receives grid start signal V
GHThe time, the drain electrode of transistor T 2 can receive grid shutdown signal V
GL, and drop-down unit 301 can while receiving grid utmost point shutdown signal V
GL
Based on above-mentioned, when sequential control module 105 provides grid shutdown signal V
GLGive each grade offset buffer SR in the shift register device SRD1
1~ SR
NThe grid of transistor T 5 time, expression timing control unit 105 desires control shift register device SRD1 running.Therefore, timing control unit 105 can provide start signal STV to the 1st grade of offset buffer SR
1The grid and the drain electrode of transistor T 1, and provide clock signal CK to all offset buffer SR
1~ SR
NThe drain electrode of transistor T 2, and clock signal CK and XCK that phase differential 180 degree are provided simultaneously are to all offset buffer SR
1~ SR
NDrop-down unit 301.
Also also because of so, all offset buffer SR in the shift register device SRD1
1~ SR
NCan sequence output scanning signal SS
1~ SS
N, be opened into last row pixel one by one with the first row pixel in the AA of viewing area, and source electrode driver 103 can provide the video data of correspondence to being shifted the row pixel that apparatus for temporary storage SRD1 is opened.Thus, add the backlight that backlight module 107 is provided, then display panel 101 promptly can the show image picture.
Yet, when running, do not receive the influence of shift register device SRD2 owing to hope shift register device SRD1.Therefore, timing control unit 105 can provide grid start signal V when control shift register device SRD1 running
GHGive each grade offset buffer SR ' in the shift register device SRD2
1~ SR '
NThe grid of transistor T 5, and grid shutdown signal V is provided
GLGive all offset buffer SR '
1~ SR '
NThe drain electrode of transistor T 2, and grid shutdown signal V is provided simultaneously
GLGive all offset buffer SR '
1~ SR '
NDrop-down unit 301.Thus, shift register device SRD2 promptly can decommission, thereby can not have influence on the running of shift register device SRD1.
On the other hand, grid shutdown signal V is provided when sequential control module 105
GLGive each grade offset buffer SR ' in the shift register device SRD2
1~ SR '
NThe grid of transistor T 5 time, expression timing control unit 105 desires control shift register device SRD2 running.Therefore, timing control unit 105 can provide start signal STV to the 1st grade of offset buffer SR '
1The grid and the drain electrode of transistor T 1, and provide clock signal CK to all offset buffer SR '
1~ SR '
NThe drain electrode of transistor T 2, and clock signal CK and XCK that phase differential 180 degree are provided simultaneously are to all offset buffer SR '
1~ SR '
NDrop-down unit 301.
Also also because of so, all offset buffer SR ' in the shift register device SRD2
1~ SR '
NCan sequence output scanning signal SS '
1~ SS '
N, be opened into the first row pixel one by one with last row pixel in the AA of viewing area, and source electrode driver 103 also can provide the video data of correspondence to being shifted the row pixel that apparatus for temporary storage SRD2 is opened.Thus, add the backlight that backlight module 107 is provided, then display panel 101 promptly can the show image picture.
Yet, when running, do not receive the influence of shift register device SRD1 owing to hope shift register device SRD2.Therefore, timing control unit 105 can provide grid start signal V when control shift register device SRD2 running
GHGive each grade offset buffer SR in the shift register device SRD1
1~ SR
NThe grid of transistor T 5, and grid shutdown signal V is provided
GLGive all offset buffer SR
1~ SR
NThe drain electrode of transistor T 2, and grid shutdown signal V is provided simultaneously
GLGive all offset buffer SR
1~ SR
NDrop-down unit 301.Thus, shift register device SRD1 promptly can decommission, thereby can not have influence on the running of shift register device SRD2.
Except that this, Fig. 4 illustrates the offset buffer SR into another example embodiment of the present invention
i/ SR '
iCircuit diagram.Please merge with reference to Fig. 3 and Fig. 4, can know from Fig. 4 and find out, transistor T 5 ' ~ T8 ' can replace transistor T 5, uses the not enough problem of fiduciary level of improving transistor T 5.The grid of transistor T 5 ' can be coupled in to receive grid shutdown signal V with drain electrode
GL, perhaps (N is a positive integer, and during for example being per 100 pictures, but is not restricted to this) receives grid start signal V during every N picture of LCD 100
GHWith grid shutdown signal V
GLOne of which.The grid of transistor T 6 ' couples the source electrode of transistor T 5 ', and the drain electrode of transistor T 6 ' couples the grid of transistor T 2, and the source electrode of transistor T 6 ' then is coupled to reference voltage VSS.
The grid of transistor T 7 ' can be coupled in to receive grid shutdown signal V with drain electrode
GL, perhaps during every N picture of LCD 100, receive grid start signal V
GHWith grid shutdown signal V
GLAnother.The grid of transistor T 8 ' couples the source electrode of transistor T 7 ', and the drain electrode of transistor T 8 ' couples the grid of transistor T 2, and the source electrode of transistor T 8 ' then is coupled to reference voltage VSS.
In present embodiment, when the grid of transistor T 5 ' and T7 ' receives the grid shutdown signal V that is provided by timing control unit 105 simultaneously
GLThe time, the drain electrode of transistor T 2 can receive clock signal CK, and drop-down unit 301 respectively receiving phase differ from the clock signal CK and the XCK of 180 degree.But, when the grid of transistor T 5 ' and T7 ' alternately receives grid start signal V during every N picture of LCD 100
GHWith grid shutdown signal V
GLThe time, then the drain electrode of transistor T 2 can receive grid shutdown signal V
GL, and drop-down unit 100 can while receiving grid utmost point shutdown signal V
GL
Based on above-mentioned, when sequential control module 105 provides grid shutdown signal V simultaneously
GLGive each grade offset buffer SR in the shift register device SRD1
1~ SR
NThe grid of transistor T 5 ' and T7 ' time, expression timing control unit 105 desires control shift register device SRD1 running.Therefore, timing control unit 105 can provide start signal STV to the 1st grade of offset buffer SR
1The grid and the drain electrode of transistor T 1, and provide clock signal CK to all offset buffer SR
1~ SR
NThe drain electrode of transistor T 2, and clock signal CK and XCK that phase differential 180 degree are provided simultaneously are to all offset buffer SR
1~ SR
NDrop-down unit 301.
Also also because of so, all offset buffer SR in the shift register device SRD1
1~ SR
NCan sequence output scanning signal SS
1~ SS
N, be opened into last row pixel one by one with the first row pixel in the AA of viewing area, and source electrode driver 103 can provide the video data of correspondence to being shifted the row pixel that apparatus for temporary storage SRD1 is opened.Thus, add the backlight that backlight module 107 is provided, then display panel 101 promptly can the show image picture.
Yet, when running, do not receive the influence of shift register device SRD2 owing to hope shift register device SRD1.Therefore, timing control unit 105 can be in control shift register device SRD1 running, and during every N picture of LCD 100 time, grid start signal V is provided alternately
GHWith grid shutdown signal V
GLGive each grade offset buffer SR ' in the shift register device SRD2
1~ SR '
NTransistor T 5 ' and the grid of T7 ', and grid shutdown signal V is provided
GLGive all offset buffer SR '
1~ SR '
NThe drain electrode of transistor T 2, and grid shutdown signal V is provided simultaneously
GLGive all offset buffer SR '
1~ SR '
NDrop-down unit 301.Thus, shift register device SRD2 promptly can decommission, thereby can not have influence on the running of shift register device SRD1.
On the other hand, grid shutdown signal V is provided simultaneously when sequential control module 105
GLGive each grade offset buffer SR ' in the shift register device SRD2
1~ SR '
NThe grid of transistor T 5 ' and T7 ' time, expression timing control unit 105 desires control shift register device SRD2 running.Therefore, timing control unit 105 can provide start signal STV to the 1st grade of offset buffer SR '
1The grid and the drain electrode of transistor T 1, and provide clock signal CK to all offset buffer SR '
1~ SR '
NThe drain electrode of transistor T 2, and clock signal CK and XCK that phase differential 180 degree are provided simultaneously are to all offset buffer SR '
1~ SR '
NDrop-down unit 301.
Also also because of so, all offset buffer SR ' in the shift register device SRD2
1~ SR '
NCan sequence output scanning signal SS '
1~ SS '
N, be opened into the first row pixel one by one with last row pixel in the AA of viewing area, and source electrode driver 103 also can provide the video data of correspondence to being shifted the row pixel that apparatus for temporary storage SRD2 is opened.Thus, add the backlight that backlight module 107 is provided, then display panel 101 promptly can the show image picture.
Yet, when running, do not receive the influence of shift register device SRD1 owing to hope shift register device SRD2.Therefore, timing control unit 105 can be in control shift register device SRD2 running, and during every N picture of LCD 100 time, grid start signal V is provided alternately
GHGive each grade offset buffer SR in the shift register device SRD1
1~ SR
NTransistor T 5 ' and the grid of T7 ', and grid shutdown signal V is provided
GLGive all offset buffer SR
1~ SR
NThe drain electrode of transistor T 2, and grid shutdown signal V is provided simultaneously
GLGive all offset buffer SR
1~ SR
NDrop-down unit 301.Thus, shift register device SRD1 promptly can decommission, thereby can not have influence on the running of shift register device SRD2.
In sum; The present invention mainly be with two independently shift register device directly be configured in the left and right sides of the glass substrate of display panel respectively; And control the running of these two shift register devices through timing control unit, to let these two shift register devices one normal operations only arranged in the same time.In addition; Because the one of which of these two shift register devices can sequence be exported the one scan signal; The first row pixel with from display panel is opened into last row pixel one by one, and another then can be opened into the first row pixel with last row pixel from display panel by sequence output one scan signal one by one.Therefore, these two shift register devices can forward scan or reverse scanning display panel, thereby improve the awkward situation that multistage offset buffer on the existing glass substrate that directly is configured in display panel does not have the function of reverse scanning.
Though the present invention discloses as above with above-mentioned example embodiment; Right its is not in order to limit the present invention; Has common knowledge the knowledgeable in the technical field under any; Do not breaking away from the spirit and scope of the present invention, when doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (22)
1. display comprises:
One display panel has a plurality of pixels with arranged; And
One first and one second shift register device, both all directly are configured on the glass substrate of this display panel,
Wherein, This first with this second shift register device in the same time one normal operations are only arranged; And when this first shift register device normal operation; Sequence output one scan signal is being opened into last row pixel from the first row pixel one by one, and when this second shift register device normal operation, sequence is exported this sweep signal to be opened into the first row pixel one by one from last row pixel;
Wherein, this first shift register device comprises first offset buffer that the multi-level pmultistage circuit framework is identical and be serially connected each other, and wherein i level first offset buffer comprises:
One the first transistor, its grid is coupled in to receive an activation signal with its drain electrode;
One transistor seconds, its grid couples the source electrode of this first transistor, and it drains in order to receive one first clock signal or a grid shutdown signal, and its source electrode is then in order to export this sweep signal;
One electric capacity is coupled between the grid and source electrode of this transistor seconds;
One drop-down unit; Couple this first with the source electrode of this transistor seconds; Differ from this first and 1 second clock signal of 180 degree or receive this grid shutdown signal simultaneously in order to receiving phase respectively; And when i level first offset buffer is not exported this sweep signal, the source electrode of this transistor seconds is coupled to a reference voltage;
One the 3rd transistor, its grid is in order to receive the output of i+1 level first offset buffer, and its drain electrode couples the source electrode of this transistor seconds, and its source electrode then is coupled to this reference voltage; And
One the 4th transistor, its grid couple the 3rd transistorized grid, and its drain electrode couples the grid of this transistor seconds, and its source electrode then is coupled to this reference voltage,
Wherein, i is a positive integer.
2. display according to claim 1 is characterized in that, i level first offset buffer more comprises:
One the 5th transistor, its grid is in order to receive a grid start signal or this grid shutdown signal, and its drain electrode couples the grid of this transistor seconds, and its source electrode then is coupled to this reference voltage.
3. display according to claim 2; It is characterized in that; When the 5th transistorized grid receives this grid shutdown signal; The drain electrode of this transistor seconds is in order to receiving this first clock signal, this drop-down unit then in order to receiving phase respectively differ from 180 degree this first with this second clock signal.
4. display according to claim 2; It is characterized in that; When the 5th transistorized grid received this grid start signal, the drain electrode of this transistor seconds was in order to receive this grid shutdown signal, and this drop-down unit is then in order to receive this grid shutdown signal simultaneously.
5. display according to claim 1 is characterized in that, i level first offset buffer more comprises:
One the 5th transistor, its grid is coupled in to receive this grid shutdown signal with its drain electrode, perhaps during every N picture of this display, receives the one of which of a grid start signal and this grid shutdown signal;
One the 6th transistor, its grid couple the 5th transistorized source electrode, and its drain electrode couples the grid of this transistor seconds, and its source electrode then is coupled to this reference voltage;
One the 7th transistor, its grid is coupled in to receive this grid shutdown signal with its drain electrode, perhaps during every N picture of this display, receives another of this grid start signal and this grid shutdown signal; And
One the 8th transistor, its grid couple the 7th transistorized source electrode, and its drain electrode couples the grid of this transistor seconds, and its source electrode then is coupled to this reference voltage,
Wherein, N is a positive integer.
6. display according to claim 5; It is characterized in that; When the 5th transistor AND gate the 7th transistorized grid receives this grid shutdown signal simultaneously; Then the drain electrode of this transistor seconds is in order to receiving this first clock signal, and this drop-down unit in order to receiving phase respectively differ from 180 degree this first with this second clock signal.
7. display according to claim 5; It is characterized in that; When the 5th transistor AND gate the 7th transistorized grid alternately receives this grid start signal and this grid shutdown signal during every N picture of this display; Then the drain electrode of this transistor seconds is in order to receiving this grid shutdown signal, and this drop-down unit is in order to receive this grid shutdown signal simultaneously.
8. display according to claim 1 is characterized in that, this second shift register device comprises second offset buffer that the multi-level pmultistage circuit framework is identical and be serially connected each other, and wherein i level second offset buffer comprises:
One the first transistor, its grid is coupled in to receive an activation signal with its drain electrode;
One transistor seconds, its grid couples the source electrode of this first transistor, and it drains in order to receive one first clock signal or a grid shutdown signal, and its source electrode is then in order to export this sweep signal;
One electric capacity is coupled between the grid and source electrode of this transistor seconds;
One drop-down unit; Couple this first with the source electrode of this transistor seconds; Differ from this first and 1 second clock signal of 180 degree or receive this grid shutdown signal simultaneously in order to receiving phase respectively; And when i level second offset buffer is not exported this sweep signal, the source electrode of this transistor seconds is coupled to a reference voltage;
One the 3rd transistor, its grid is in order to receive the output of i+1 level second offset buffer, and its drain electrode couples the source electrode of this transistor seconds, and its source electrode then is coupled to this reference voltage; And
One the 4th transistor, its grid couple the 3rd transistorized grid, and its drain electrode couples the grid of this transistor seconds, and its source electrode then is coupled to this reference voltage,
Wherein, i is a positive integer.
9. display according to claim 8 is characterized in that, i level second offset buffer more comprises:
One the 5th transistor, its grid is in order to receive a grid start signal or this grid shutdown signal, and its drain electrode couples the grid of this transistor seconds, and its source electrode then is coupled to this reference voltage.
10. display according to claim 9; It is characterized in that; When the 5th transistorized grid receives this grid shutdown signal; The drain electrode of this transistor seconds is in order to receiving this first clock signal, this drop-down unit then in order to receiving phase respectively differ from 180 degree this first with this second clock signal.
11. display according to claim 9; It is characterized in that; When the 5th transistorized grid received this grid start signal, the drain electrode of this transistor seconds was in order to receive this grid shutdown signal, and this drop-down unit is then in order to receive this grid shutdown signal simultaneously.
12. display according to claim 8 is characterized in that, i level second offset buffer more comprises:
One the 5th transistor, its grid is coupled in to receive this grid shutdown signal with its drain electrode, perhaps during every N picture of this display, receives the one of which of a grid start signal and this grid shutdown signal;
One the 6th transistor, its grid couple the 5th transistorized source electrode, and its drain electrode couples the grid of this transistor seconds, and its source electrode then is coupled to this reference voltage;
One the 7th transistor, its grid is coupled in to receive this grid shutdown signal with its drain electrode, perhaps during every N picture of this display, receives another of this grid start signal and this grid shutdown signal; And
One the 8th transistor, its grid couple the 7th transistorized source electrode, and its drain electrode couples the grid of this transistor seconds, and its source electrode then is coupled to this reference voltage,
Wherein, N is a positive integer.
13. display according to claim 12; It is characterized in that; When the 5th transistor AND gate the 7th transistorized grid receives this grid shutdown signal simultaneously; Then the drain electrode of this transistor seconds is in order to receiving this first clock signal, and this drop-down unit in order to receiving phase respectively differ from 180 degree this first with this second clock signal.
14. display according to claim 12; It is characterized in that; When the 5th transistor AND gate the 7th transistorized grid alternately receives this grid start signal and this grid shutdown signal during every N picture of this display; Then the drain electrode of this transistor seconds is in order to receiving this grid shutdown signal, and this drop-down unit is in order to receive this grid shutdown signal simultaneously.
15. display according to claim 1 is characterized in that, more comprises a sequential control module, couple and control this first with the running of this second shift register device.
16. display according to claim 1 is characterized in that, this display is a LCD.
17. a shift register device comprises:
Identical and the offset buffer that is serially connected each other of multi-level pmultistage circuit framework, wherein i level offset buffer comprises:
One the first transistor, its grid is coupled in to receive an activation signal with its drain electrode;
One transistor seconds, its grid couples the source electrode of this first transistor, and its drain electrode is in order to receive one first clock signal or a grid shutdown signal, and its source electrode is then in order to output one scan signal;
One electric capacity is coupled between the grid and source electrode of this transistor seconds;
One drop-down unit; Couple this first with the source electrode of this transistor seconds; Differ from this first and 1 second clock signal of 180 degree or receive this grid shutdown signal simultaneously in order to receiving phase respectively; And when i level first offset buffer is not exported this sweep signal, the source electrode of this transistor seconds is coupled to a reference voltage;
One the 3rd transistor, its grid is in order to receive the output of i+1 level first offset buffer, and its drain electrode couples the source electrode of this transistor seconds, and its source electrode then is coupled to this reference voltage;
One the 4th transistor, its grid couple the 3rd transistorized grid, and its drain electrode couples the grid of this transistor seconds, and its source electrode then is coupled to this reference voltage; And
One the 5th transistor, its grid is in order to receive a grid start signal or this grid shutdown signal, and its drain electrode couples the grid of this transistor seconds, and its source electrode then is coupled to this reference voltage,
Wherein, i is a positive integer.
18. shift register device according to claim 17; It is characterized in that; When the 5th transistorized grid receives this grid shutdown signal; The drain electrode of this transistor seconds is in order to receiving this first clock signal, this drop-down unit then in order to receiving phase respectively differ from 180 degree this first with this second clock signal.
19. shift register device according to claim 18; It is characterized in that; When the 5th transistorized grid received this grid start signal, the drain electrode of this transistor seconds was in order to receive this grid shutdown signal, and this drop-down unit is then in order to receive this grid shutdown signal simultaneously.
20. a shift register device comprises:
Identical and the offset buffer that is serially connected each other of multi-level pmultistage circuit framework, wherein i level offset buffer comprises:
One the first transistor, its grid is coupled in to receive an activation signal with its drain electrode;
One transistor seconds, its grid couples the source electrode of this first transistor, and its drain electrode is in order to receive one first clock signal or a grid shutdown signal, and its source electrode is then in order to output one scan signal;
One electric capacity is coupled between the grid and source electrode of this transistor seconds;
One drop-down unit; Couple this first with the source electrode of this transistor seconds; Differ from this first and 1 second clock signal of 180 degree or receive this grid shutdown signal simultaneously in order to receiving phase respectively; And when i level first offset buffer is not exported this sweep signal, the source electrode of this transistor seconds is coupled to a reference voltage;
One the 3rd transistor, its grid is in order to receive the output of i+1 level first offset buffer, and its drain electrode couples the source electrode of this transistor seconds, and its source electrode then is coupled to this reference voltage;
One the 4th transistor, its grid couple the 3rd transistorized grid, and its drain electrode couples the grid of this transistor seconds, and its source electrode then is coupled to this reference voltage;
One the 5th transistor, its grid is coupled in to receive this grid shutdown signal with its drain electrode, perhaps during every N picture of a display, receives the one of which of a grid start signal and this grid shutdown signal;
One the 6th transistor, its grid couple the 5th transistorized source electrode, and its drain electrode couples the grid of this transistor seconds, and its source electrode then is coupled to this reference voltage;
One the 7th transistor, its grid is coupled in to receive this grid shutdown signal with its drain electrode, perhaps during every N picture of this display, receives another of this grid start signal and this grid shutdown signal; And
One the 8th transistor, its grid couple the 7th transistorized source electrode, and its drain electrode couples the grid of this transistor seconds, and its source electrode then is coupled to this reference voltage,
Wherein, i, N are positive integer.
21. shift register device according to claim 20; It is characterized in that; When the 5th transistor AND gate the 7th transistorized grid receives this grid shutdown signal simultaneously; Then the drain electrode of this transistor seconds is in order to receiving this first clock signal, and this drop-down unit in order to receiving phase respectively differ from 180 degree this first with this second clock signal.
22. shift register device according to claim 20; It is characterized in that; When the 5th transistor AND gate the 7th transistorized grid alternately receives this grid start signal and this grid shutdown signal during every N picture of this display; Then the drain electrode of this transistor seconds is in order to receiving this grid shutdown signal, and this drop-down unit is in order to receive this grid shutdown signal simultaneously.
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| CN101620334B true CN101620334B (en) | 2012-06-27 |
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