CN103731237A - Biphase-space-code-oriented decoding method, device, equipment and communication system - Google Patents
Biphase-space-code-oriented decoding method, device, equipment and communication system Download PDFInfo
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Abstract
The invention discloses a biphase-space-code-oriented decoding method, device, equipment and communication system. The method comprises the steps that according to digital signal hard decision results after code stream processing, a data clock is extracted, based on the FM0 coding principle, two adjacent rising edges of the data clock are used as integration domains, the digital signals with plus-minus signs are subjected to area integration, integration operation results with plus-minus signs are subjected to soft decision, the two adjacent integration domains, namely the soft decision results of two code elements are subjected to preset operation, and then decoding of a data bit is completed. According to the decoding realizing mode, interference on decision results from glitches or the duty ratio or bit speed changing can be avoided, and accordingly decoding accuracy is improved.
Description
Technical field
The present invention relates to radio communication decoding technique field, more particularly, relate to a kind of coding/decoding method towards two-phase space code, device, equipment and communication system.
Background technology
Electronic charging system without parking ETC is that vehicular traffic need not stop while passing through road junction, can realize the Fare Collection System of automatic charging.Described ETC system comprises board units OBU and roadside unit RSU, by the coding of two-phase space code FM0 in OBU, and realizes communication in RSU decoding.
Existing FM0 coding principle is to adopt level to change presentation logic, as shown in Figure 1a, and at data bit section start upset presentation logic " 1 ", at presentation logic " 0 " of data bit intermediate flipped.In existing FM0 coding/decoding method, as shown in Figure 1 b, method is to utilize phase-locked loop clock recovered clock from received coded data comparatively accurately, and adjudicates according to default decision threshold at the trailing edge (selected judgement moment) of data clock, thereby obtains decode results.
But, existing FM0 interpretation method causes encoded signal quality variation facing outside noise impact, while namely there is the situations such as burr, change in duty cycle or bit rate variation when coded data, adjudicate according to selected judgement moment and default decision threshold, will occur the problem of decode results poor accuracy.
Summary of the invention
In view of this, the invention provides a kind of coding/decoding method towards two-phase space code, device, equipment and communication system, to realize the encoded signal quality variation in the situation that, the technique effect that decode results accuracy improves.
Towards a coding/decoding method for two-phase space code, comprising:
Sampling two-phase space code FM0 code stream, and described code stream is carried out to analog-to-digital conversion and preliminary treatment, obtain the digital signal with sign symbol;
The described digital signal with sign symbol is carried out to hard decision, and extract data clock from hard decision result;
Take two adjacent rising edges of described data clock as integral domain, the described digital signal with sign is carried out to area integral computing;
According to default decision threshold, described integral operation result is adjudicated, obtain soft-decision result;
Soft-decision result to adjacent two integral domains is preset computing, output decode results.
Alternatively, from hard decision result, extracting data clock comprises:
Adopt all-digital phase-locked loop to extract data clock from hard decision result.
Alternatively, according to default decision threshold, described integral operation result is adjudicated and is comprised:
Obtain integral operation result;
Judge whether integral operation result is greater than 0, if be greater than 0, the soft-decision result of this integral domain is 1, otherwise the soft-decision result of this integral domain is 0.
Alternatively, the soft-decision result of adjacent two integral domains being preset to computing comprises:
Soft-decision result to adjacent two integral domains is carried out XNOR computing.
Towards a decoding device for two-phase space code, comprising:
Sampling and pretreatment module, for the two-phase space code FM0 code stream of sampling, and carry out analog-to-digital conversion and preliminary treatment to described code stream, obtains the digital signal with sign symbol;
Hard decision module, for carrying out hard decision to the described digital signal with sign symbol;
Clock Extraction module, for extracting data clock from hard decision result;
Area integral computing module, for take two adjacent rising edges of described data clock as integral domain, carries out area integral computing to the described digital signal with sign;
Soft-decision module, for according to default decision threshold, described integral operation result being adjudicated, obtains soft-decision result;
Decoding output module, presets computing for the soft-decision result to adjacent two integral domains, output decode results.
Alternatively, described soft-decision module specific implementation:
Obtain integral operation result;
Judge whether integral operation result is greater than 0, if be greater than 0, the soft-decision result of this integral domain is 1, otherwise the soft-decision result of this integral domain is 0.
Alternatively, described decoding output module specific implementation: the soft-decision result to adjacent two integral domains is carried out XNOR computing, and exports decode results.
Towards a decoding device for two-phase space code, comprising:
Sampling and pretreatment unit, comprising: AD conversion unit and pretreatment unit;
Described sampling and pretreatment unit are realized sampling two-phase space code FM0 code stream, and described code stream is carried out to analog-to-digital conversion and preliminary treatment, obtain the digital signal with sign symbol;
And decode controller, comprising: decoding chip and storage chip, wherein;
Described decoding chip is carried out the instruction in described storage chip, and described decoding chip is provided with the corresponding circuits of carrying out instruction in described storage chip;
The instruction of described storage chip comprises:
The described digital signal with sign symbol is carried out to hard decision, and extract data clock from hard decision result;
Take two adjacent rising edges of described data clock as integral domain, the described digital signal with sign is carried out to area integral computing;
According to default decision threshold, described integral operation result is adjudicated, obtain soft-decision result;
Soft-decision result to adjacent two integral domains is preset computing, output decode results.
Alternatively, from hard decision result, to extract the circuit of data clock instruction be all-digital phase-locked loop to the set execution of decoding chip.
Alternatively, the instruction that the default decision threshold of described basis is adjudicated described integral operation result comprises:
Obtain integral operation result;
Judge whether integral operation result is greater than 0, if be greater than 0, the soft-decision result of this integral domain is 1, otherwise the soft-decision result of this integral domain is 0.
Alternatively, the instruction of the soft-decision result of adjacent two integral domains being preset to computing comprises:
Soft-decision result to adjacent two integral domains is carried out XNOR computing.
Towards a communication system for two-phase space code, comprising:
Board units and roadside unit, described roadside unit comprises:
The above-mentioned decoding device towards two-phase space code.
From above-mentioned technical scheme, can find out, the embodiment of the present invention extracts data clock according to the pretreated digital signal hard decision of code stream result, with reference to FM0 coding principle, take two adjacent rising edges of described data clock as integral domain, the described digital signal with sign is carried out to area integral, and the integral operation result with sign is carried out to soft-decision, to adjacent two integral domains, namely the soft-decision result of two code elements is preset the decoding that completes a data bit after computing.This kind of decoding way of realization can be got rid of burr, duty ratio or bit rate and change the interference to court verdict, thereby improved the accuracy of decoding.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 a is existing FM0 coding principle schematic diagram disclosed by the invention;
Fig. 1 b is existing FM0 decoding principle schematic disclosed by the invention;
Fig. 2 is the disclosed a kind of coding/decoding method flow chart towards two-phase space code of the embodiment of the present invention;
Fig. 3 is the disclosed a kind of decoding device structural representation towards two-phase space code of the embodiment of the present invention;
Fig. 4 is the disclosed a kind of decoding device structural representation towards two-phase space code of the embodiment of the present invention;
Fig. 5 is the disclosed a kind of communication system structural representation towards two-phase space code of the embodiment of the present invention.
Embodiment
For quote and know for the purpose of, the technical term that hereinafter uses, write a Chinese character in simplified form or abridge and be summarized as follows:
ETC:Electronic Toll Collection electronic charging system without parking;
OBU:On board Unit, is used for and the mobile unit of the roadside RSU communication of setting up;
RSU:Rate-Sensor Unit rate sensor device, i.e. roadside device;
FM0:Bi-Phase Space, two-phase space code coding.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The existing coding/decoding method towards two-phase space code, according to FM0 coding principle, utilizes phase-locked loop clock recovered clock from received coded data, and adjudicates according to default decision threshold at the trailing edge (selected judgement moment) of data clock.
Referring to Fig. 1 b, after being calculated, two adjacent court verdicts obtain decoded result, described decision threshold is exactly the decision threshold in hard decision, generally be chosen to be 0, namely in the trailing edge coded data of data clock, be greater than zero and be designated as 1, be less than zero and be designated as 0, when coded data is subject to noise effect and occurs the situation of encoded signal quality variation, as there is the situation of burr in coded data, this burr appears at the trailing edge of data clock just, this data clock be originally designated as 0 and because burr occur occurring being designated as 1 court verdict, thereby final decode results also there will be deviation, and situation about changing for change in duty cycle and bit rate, to there is similar result in above-mentioned coding/decoding method, thereby the coding/decoding method of encoding towards FM0 in prior art, when burr appears in coded data, during the situations such as change in duty cycle or bit rate variation, adjudicate according to selected judgement moment and default decision threshold, the problem of decode results poor accuracy will be there is.
Through the research of inventor to prior art, the coding/decoding method towards two-phase space code, device, equipment and the communication system of the embodiment of the present invention disclosed, to realize the encoded signal quality variation in the situation that, the technique effect that decode results accuracy improves.
Fig. 2 shows a kind of coding/decoding method towards two-phase space code, comprising:
S21: sampling two-phase space code FM0 code stream, and described code stream is carried out to analog-to-digital conversion and preliminary treatment, obtain the digital signal with sign symbol;
FM0 code stream is the analog signal after coding with sign symbol, needs to carry out analog-to-digital conversion, and carry out the preliminary treatment of Noise and Interference filtering before decoding, is reduced to the digital signal with sign symbol, for decoding is prepared.
S22: the described digital signal with sign symbol is carried out to hard decision, and extract data clock from hard decision result;
Utilize the sign of Contemporary Digital signal to carry out hard decision, the data decision higher than 0 is 1, otherwise judgement is 0, utilizes the result of hard decision can reduce the clock of described code stream, in the area integral computing of described clock in S13, uses.
S23: take two adjacent rising edges of described data clock as integral domain, the described digital signal with sign is carried out to area integral computing;
After analog-to-digital conversion and preliminary treatment, described digital signal is still with sign, take digital signal as Integrating, take two adjacent rising edges of data clock as integral domain, described two adjacent rising edges namely form the code element of a data bit, the court verdict obtaining with two integral domains is decoded, and is the judgement mode drawing according to FM0 coding rule.
Object using integral domain area as soft-decision, when occurring that burr, change in duty cycle and bit rate change, may there is contrary court verdict in the selected judgement moment in existing decision method, but adopt the mode of this embodiment, generally, the appearance of this burr does not affect the positive and negative of integral area, thereby will be more reliable as soft-decision object.
S24: according to default decision threshold, described integral operation result is adjudicated, obtain soft-decision result;
Described integral operation result is with sign, and according to the size of area, integral operation result value can be variant, as preferably, decision threshold is set to 0, judges whether integral operation result is greater than 0, if be greater than 0, the soft-decision result of this integral domain is 1, otherwise the soft-decision result of this integral domain is 0.The corresponding soft-decision result of each integral domain.
S25: the soft-decision result to adjacent two integral domains is preset computing, output decode results.
Two integral domains are that two code elements have formed complete data bit, thereby according to two soft-decision results default operation result, the i.e. former FM0 coded data of decodable code.
At the present embodiment, described default computing is specially: the soft-decision result to adjacent two integral domains is carried out XNOR computing.Described XNOR computing is comparatively simple implementation, but does not limit to.
Above-described embodiment is with reference to FM0 coding principle, take two adjacent rising edges of described data clock as integral domain, the described digital signal with sign is carried out to area integral, and the integral operation result with sign is carried out to soft-decision, to adjacent two integral domains, namely the soft-decision result of two code elements is preset the decoding that completes a data bit after computing.This kind of decoding way of realization can be got rid of burr, duty ratio or bit rate and change the interference to court verdict, thereby improved the accuracy of decoding.
Fig. 3 shows a kind of decoding device structure towards two-phase space code, comprising:
Sampling and pretreatment module 31, for the two-phase space code FM0 code stream of sampling, and carry out analog-to-digital conversion and preliminary treatment to described code stream, obtains the digital signal with sign symbol;
Clock Extraction module 33, for extracting data clock from hard decision result;
Area integral computing module 34, for take two adjacent rising edges of described data clock as integral domain, carries out area integral computing to the described digital signal with sign;
Soft-decision module 35, for according to default decision threshold, described integral operation result being adjudicated, obtains soft-decision result;
Described soft-decision module 35 specific implementations:
Obtain integral operation result;
Judge whether integral operation result is greater than 0, if be greater than 0, the soft-decision result of this integral domain is 1, otherwise the soft-decision result of this integral domain is 0.
Described decoding output module 36 specific implementations: the soft-decision result to adjacent two integral domains is carried out XNOR computing, and exports decode results.
Said apparatus, for the corresponding consistent functional module of each step of method in Fig. 2 diagram and embodiment, the device being limited by such functional module is the functional module construction of realizing technical solution of the present invention.
Fig. 4 shows a kind of decoding device towards two-phase space code, comprising:
Sampling and pretreatment unit 41, comprising: AD conversion unit 411 and pretreatment unit 412;
Described sampling and pretreatment unit 41 are realized sampling two-phase space code FM0 code stream, and described code stream is carried out to analog-to-digital conversion and preliminary treatment, obtain the digital signal with sign symbol;
And decode controller 42, comprising: decoding chip 421 and storage chip 422, wherein;
Described decoding chip 421 is carried out the instruction in described storage chip 422, and described decoding chip 421 is provided with the corresponding circuits of carrying out instruction in described storage chip 422;
The instruction of described storage chip 422 comprises:
The described digital signal with sign symbol is carried out to hard decision, and extract data clock from hard decision result;
As preferably, the corresponding circuits that data clock instruction is extracted in the set execution of decoding chip is digital phase-locked loop.
Take two adjacent rising edges of described data clock as integral domain, the described digital signal with sign is carried out to area integral computing;
According to default decision threshold, described integral operation result is adjudicated, obtain soft-decision result;
Above-mentioned instruction, as preferably, can be:
Obtain integral operation result;
Judge whether integral operation result is greater than 0, if be greater than 0, the soft-decision result of this integral domain is 1, otherwise the soft-decision result of this integral domain is 0.
Soft-decision result to adjacent two integral domains is preset computing, output decode results.
Described decoding chip 421 reads the instruction in described storage chip 422 and carries out, for the model of decoding chip, and the type of storage chip do not limit to, instruction can be placed in the storage medium of any other form known in random storage chip (RAM), internal memory, read-only storage chip (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or the technical field coordinating with decoding chip.
Described decoding device can be interpreted as RSU, except necessary sensing apparatus and hardware frock, also comprise above-mentioned sampling and pretreatment unit 41 and decode controller 42, decoding chip in described sampling and pretreatment unit 41 and decode controller 42 can be realized by FPGA, described RSU also comprises master cpu, and described CPU realizes the function of controlling other parts of RSU; Described decoding device also may be interpreted as independent decoding instrument, realizes decoding function, and roadside unit function can cooperate with the miscellaneous part in described roadside unit 52.
Fig. 5 shows a kind of communication system towards two-phase space code, comprising:
The decoding device towards two-phase space code of Fig. 4 diagram and corresponding explanation thereof.In the present embodiment, described decoding device may be interpreted as the independent decoding instrument arranging in roadside unit 52, realizes decoding function, and the roadside unit function that cooperated with the miscellaneous part in described roadside unit 52.
In sum:
The embodiment of the present invention extracts data clock according to the pretreated digital signal hard decision of code stream result, with reference to FM0 coding principle, take two adjacent rising edges of described data clock as integral domain, the described digital signal with sign is carried out to area integral, and the integral operation result with sign is carried out to soft-decision, to adjacent two integral domains, namely the soft-decision result of two code elements is preset the decoding that completes a data bit after computing.This kind of decoding way of realization can be got rid of burr, duty ratio or bit rate and change the interference to court verdict, thereby improved the accuracy of decoding.
In this specification, each embodiment adopts the mode of going forward one by one to describe, and each embodiment stresses is and the difference of other embodiment, between each embodiment identical similar part mutually referring to.Composition and the step of each example have been described according to function in the above description in general manner.These functions are carried out with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel can realize described function with distinct methods to each specifically should being used for, but this realization should not thought and exceeds scope of the present invention.
For controller and system embodiment, because it is substantially corresponding to embodiment of the method, so describe fairly simplely, relevant part is referring to the part explanation of embodiment of the method.Device embodiment described above is only schematic, the wherein said unit as separating component explanation can or can not be also physically to separate, the parts that show as unit can be or can not be also physical locations, can be positioned at a place, or also can be distributed in multiple network element.Can select according to the actual needs some or all of module wherein to realize the object of the present embodiment scheme.Those of ordinary skills, in the situation that not paying creative work, are appreciated that and implement.
To the above-mentioned explanation of the disclosed embodiments, make professional and technical personnel in the field can realize or use the present invention.To the multiple modification of these embodiment, will be apparent for those skilled in the art, General Principle as defined herein can, in the case of not departing from the spirit or scope of the embodiment of the present invention, realize in other embodiments.Therefore, the embodiment of the present invention will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (12)
1. towards a coding/decoding method for two-phase space code, it is characterized in that, comprising:
Sampling two-phase space code FM0 code stream, and described code stream is carried out to analog-to-digital conversion and preliminary treatment, obtain the digital signal with sign symbol;
The described digital signal with sign symbol is carried out to hard decision, and extract data clock from hard decision result;
Take two adjacent rising edges of described data clock as integral domain, the described digital signal with sign is carried out to area integral computing;
According to default decision threshold, described integral operation result is adjudicated, obtain soft-decision result;
Soft-decision result to adjacent two integral domains is preset computing, output decode results.
2. as claimed in claim 1 towards the coding/decoding method of two-phase space code, it is characterized in that, from hard decision result, extract data clock and comprise:
Adopt all-digital phase-locked loop to extract data clock from hard decision result.
3. as claimed in claim 1 towards the coding/decoding method of two-phase space code, it is characterized in that, according to default decision threshold, described integral operation result adjudicated and comprised:
Obtain integral operation result;
Judge whether integral operation result is greater than 0, if be greater than 0, the soft-decision result of this integral domain is 1, otherwise the soft-decision result of this integral domain is 0.
4. as claimed in claim 1 towards the coding/decoding method of two-phase space code, it is characterized in that, the soft-decision result of adjacent two integral domains preset to computing and comprise:
Soft-decision result to adjacent two integral domains is carried out XNOR computing.
5. towards a decoding device for two-phase space code, it is characterized in that, comprising:
Sampling and pretreatment module, for the two-phase space code FM0 code stream of sampling, and carry out analog-to-digital conversion and preliminary treatment to described code stream, obtains the digital signal with sign symbol;
Hard decision module, for carrying out hard decision to the described digital signal with sign symbol;
Clock Extraction module, for extracting data clock from hard decision result;
Area integral computing module, for take two adjacent rising edges of described data clock as integral domain, carries out area integral computing to the described digital signal with sign;
Soft-decision module, for according to default decision threshold, described integral operation result being adjudicated, obtains soft-decision result;
Decoding output module, presets computing for the soft-decision result to adjacent two integral domains, output decode results.
6. the decoding device towards two-phase space code as claimed in claim 5, is characterized in that, described soft-decision module specific implementation:
Obtain integral operation result;
Judge whether integral operation result is greater than 0, if be greater than 0, the soft-decision result of this integral domain is 1, otherwise the soft-decision result of this integral domain is 0.
7. the decoding device towards two-phase space code as claimed in claim 5, is characterized in that, described decoding output module specific implementation: the soft-decision result to adjacent two integral domains is carried out XNOR computing, and exports decode results.
8. towards a decoding device for two-phase space code, it is characterized in that, comprising:
Sampling and pretreatment unit, comprising: AD conversion unit and pretreatment unit;
Described sampling and pretreatment unit are realized sampling two-phase space code FM0 code stream, and described code stream is carried out to analog-to-digital conversion and preliminary treatment, obtain the digital signal with sign symbol;
And decode controller, comprising: decoding chip and storage chip, wherein;
Described decoding chip is carried out the instruction in described storage chip, and described decoding chip is provided with the corresponding circuits of carrying out instruction in described storage chip;
The instruction of described storage chip comprises:
The described digital signal with sign symbol is carried out to hard decision, and extract data clock from hard decision result;
Take two adjacent rising edges of described data clock as integral domain, the described digital signal with sign is carried out to area integral computing;
According to default decision threshold, described integral operation result is adjudicated, obtain soft-decision result;
Soft-decision result to adjacent two integral domains is preset computing, output decode results.
9. as claimed in claim 8 towards the decoding device of two-phase space code, it is characterized in that,
The circuit that data clock instruction is extracted in the set execution of decoding chip from hard decision result is all-digital phase-locked loop.
10. as claimed in claim 8 towards the decoding device of two-phase space code, it is characterized in that,
The instruction that the default decision threshold of described basis is adjudicated described integral operation result comprises:
Obtain integral operation result;
Judge whether integral operation result is greater than 0, if be greater than 0, the soft-decision result of this integral domain is 1, otherwise the soft-decision result of this integral domain is 0.
11. as claimed in claim 8 towards the decoding device of two-phase space code, it is characterized in that,
The instruction of the soft-decision result of adjacent two integral domains being preset to computing comprises:
Soft-decision result to adjacent two integral domains is carried out XNOR computing.
12. 1 kinds of communication systems towards two-phase space code, is characterized in that, comprising:
Board units and roadside unit, described roadside unit comprises:
The decoding device towards two-phase space code described in claim 8-11.
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