CN103731237B - Coding/decoding method, device, equipment and communication system towards two-phase space code - Google Patents
Coding/decoding method, device, equipment and communication system towards two-phase space code Download PDFInfo
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Abstract
The embodiment of the invention discloses a kind of coding/decoding method towards two-phase space code, device, equipment and communication system, wherein method includes：The embodiment of the present invention extracts data clock according to the pretreated digital signal hard decision result of code stream, with reference to FM0 coding principles, with two adjacent rising edges of the data clock as integral domain, area integral is carried out to the digital signal with sign, and soft-decision is carried out to the integral operation result with sign, to two neighboring integral domain, that is, the decoding for completing a data bit after the soft-decision result of two code elements carries out default computing.This kind of decoding way of realization can exclude interference of burr, the dutycycle or bit rate change to court verdict, so as to improve the accuracy of decoding.
Description
Technical Field
The present invention relates to the field of wireless communication decoding technologies, and in particular, to a biphase interval code-oriented decoding method, apparatus, device, and communication system.
Background
The electronic toll collection system ETC is a toll collection system which can realize automatic toll collection without stopping when passing vehicles pass through a road junction. The ETC system comprises an on-board unit (OBU) and a Road Side Unit (RSU), and the communication is realized through encoding biphase interval codes FM0 in the OBU and decoding the RSU.
The conventional FM0 encoding principle uses level change to represent logic, as shown in fig. 1a, where a flip at the beginning of a data bit represents a logic "1" and a flip in the middle of a data bit represents a logic "0". In the existing FM0 decoding method, as shown in fig. 1b, one more accurate method is to recover a clock from received encoded data by using a phase-locked loop clock, and perform a decision on a falling edge (a selected decision time) of the data clock according to a preset decision threshold, so as to obtain a decoding result.
However, when the existing FM0 decoding method is affected by external noise and the quality of the encoded signal is deteriorated, that is, when the encoded data has a condition of glitch, duty ratio change or bit rate change, etc., the decision is made according to the selected decision time and the preset decision threshold, which results in a problem of poor accuracy of the decoding result.
Disclosure of Invention
In view of this, the present invention provides a decoding method, apparatus, device and communication system for biphase interval codes, so as to achieve the technical effect of improving the accuracy of the decoding result under the condition of the degradation of the quality of the coded signal.
A bi-phase space code oriented decoding method, comprising:
sampling a biphase interval code FM0 code stream, and performing analog-to-digital conversion and pretreatment on the code stream to obtain a digital signal with positive and negative symbols;
carrying out hard decision on the digital signal with the positive and negative symbols, and extracting a data clock from a hard decision result;
taking two adjacent rising edges of the data clock as integration areas, and carrying out area integration operation on the digital signals with signs;
judging the integral operation result according to a preset judgment threshold to obtain a soft judgment result;
and performing preset operation on the soft decision results of two adjacent integral areas, and outputting a decoding result.
Optionally, extracting the data clock from the hard decision result comprises:
and extracting a data clock from the hard decision result by adopting an all-digital phase-locked loop.
Optionally, the determining the integral operation result according to a preset determination threshold includes:
acquiring an integral operation result;
and judging whether the integral operation result is greater than 0, if so, the soft decision result of the integral area is 1, otherwise, the soft decision result of the integral area is 0.
Optionally, the performing a preset operation on the soft decision result of two adjacent integration regions includes:
and carrying out exclusive OR operation on the soft decision results of two adjacent integration areas.
A bi-phase space code-oriented decoding apparatus, comprising:
the sampling and preprocessing module is used for sampling a biphase interval code FM0 code stream, and performing analog-to-digital conversion and preprocessing on the code stream to obtain a digital signal with positive and negative symbols;
the hard decision module is used for carrying out hard decision on the digital signal with the positive and negative symbols;
the clock extraction module is used for extracting a data clock from the hard decision result;
the area integral calculation module is used for taking two adjacent rising edges of the data clock as an integral area and carrying out area integral operation on the digital signal with the sign;
the soft decision module is used for deciding the integral operation result according to a preset decision threshold to obtain a soft decision result;
and the decoding output module is used for carrying out preset operation on the soft decision results of the two adjacent integral areas and outputting a decoding result.
Optionally, the soft decision module specifically implements:
acquiring an integral operation result;
and judging whether the integral operation result is greater than 0, if so, the soft decision result of the integral area is 1, otherwise, the soft decision result of the integral area is 0.
Optionally, the decoding output module specifically implements: and performing exclusive OR operation on the soft decision results of two adjacent integral areas and outputting a decoding result.
A bi-phase space code-oriented decoding apparatus comprising:
sampling and preprocessing apparatus comprising: the device comprises an analog-digital conversion unit and a preprocessing unit;
the sampling and preprocessing device is used for sampling a biphase interval code FM0 code stream, and performing analog-to-digital conversion and preprocessing on the code stream to obtain a digital signal with positive and negative symbols;
and, a decoding controller comprising: a decoding chip and a memory chip, wherein;
the decoding chip executes the instructions in the storage chip and is provided with a corresponding circuit for executing the instructions in the storage chip;
the instructions of the memory chip include:
carrying out hard decision on the digital signal with the positive and negative symbols, and extracting a data clock from a hard decision result;
taking two adjacent rising edges of the data clock as integration areas, and carrying out area integration operation on the digital signals with signs;
judging the integral operation result according to a preset judgment threshold to obtain a soft judgment result;
and performing preset operation on the soft decision results of two adjacent integral areas, and outputting a decoding result.
Optionally, the circuit configured to execute the data clock instruction extracted from the hard decision result by the decoding chip is an all-digital phase-locked loop.
Optionally, the instruction for deciding the integral operation result according to a preset decision threshold includes:
acquiring an integral operation result;
and judging whether the integral operation result is greater than 0, if so, the soft decision result of the integral area is 1, otherwise, the soft decision result of the integral area is 0.
Optionally, the instruction for performing the preset operation on the soft decision results of two adjacent integration regions includes:
and carrying out exclusive OR operation on the soft decision results of two adjacent integration areas.
A biphase-spaced code oriented communication system comprising:
on-vehicle unit and road side unit, the road side unit includes:
the decoding device for biphase interval codes is described above.
It can be seen from the foregoing technical solutions that, in the embodiments of the present invention, a data clock is extracted according to a hard decision result of a digital signal after code stream preprocessing, and with reference to an FM0 encoding principle, two adjacent rising edges of the data clock are taken as integration regions, area integration is performed on the digital signal with a sign, soft decision is performed on the integration operation result with a sign, and decoding of one data bit is completed after preset operation is performed on the soft decision results of two adjacent integration regions, that is, two code elements. The decoding implementation form can eliminate the interference of burrs, duty ratio or bit rate change on the judgment result, thereby improving the accuracy of decoding.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1a is a schematic diagram of a conventional FM0 encoding principle disclosed in the present invention;
FIG. 1b is a schematic diagram of a prior art FM0 decoding principle disclosed in the present invention;
FIG. 2 is a flowchart of a biphase interval code-oriented decoding method according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a biphase interval code-oriented decoding apparatus according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a biphase interval code-oriented decoding device according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a biphase interval code-oriented communication system according to an embodiment of the present invention.
Detailed Description
For reference and clarity, the terms, abbreviations or abbreviations used hereinafter are summarized as follows:
ETC: electronic Toll Collection system;
an OBU: the On board Unit is used for communicating with the roadside-mounted RSU vehicle-mounted equipment;
RSU: a Rate-Sensor Unit Rate Sensor device, namely roadside equipment;
FM0 Bi-Phase Space, biphase Space code encoding.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The existing decoding method for biphase interval codes recovers a clock from received coded data by using a phase-locked loop clock according to an FM0 coding principle, and judges according to a preset judgment threshold at a falling edge (selected judgment time) of the data clock.
Referring to fig. 1b, after two adjacent decision results are calculated, a decoding result is obtained, where the decision threshold is a decision threshold in hard decision, and is generally selected to be 0, that is, when the encoded data is greater than zero and is recorded as 1 at a falling edge of a data clock and is less than zero and is recorded as 0, when the encoded data is affected by noise and the quality of an encoded signal is degraded, if a glitch occurs in the encoded data, the glitch happens to occur at the falling edge of the data clock, the data clock is originally recorded as 0 and a decision result recorded as 1 occurs because of the glitch, so that a final decoding result may also be biased, and for a duty ratio change and a bit rate change, the decoding method described above will have similar results, so that in the decoding method facing FM0 encoding in the prior art, when the encoded data has glitch, duty ratio change or bit rate change, and the like, and judging according to the selected judgment time and a preset judgment threshold, and solving the problem of poor accuracy of a decoding result.
Through the research of the inventor on the prior art, the invention discloses a biphase interval code-oriented decoding method, a biphase interval code-oriented decoding device, biphase interval code-oriented decoding equipment and a communication system, so as to achieve the technical effect of improving the accuracy of a decoding result under the condition that the quality of an encoded signal is deteriorated.
Fig. 2 shows a bi-phase space code-oriented decoding method, including:
s21: sampling a biphase interval code FM0 code stream, and performing analog-to-digital conversion and pretreatment on the code stream to obtain a digital signal with positive and negative symbols;
the FM0 code stream is an analog signal with positive and negative symbols after being encoded, and needs to be analog-to-digital converted before decoding, and is preprocessed by noise and interference filtering, and is restored into a digital signal with positive and negative symbols to prepare for decoding.
S22: carrying out hard decision on the digital signal with the positive and negative symbols, and extracting a data clock from a hard decision result;
and carrying out hard decision by using the sign of the current digital signal, wherein the data higher than 0 is decided as 1, otherwise, the decision is 0, and the clock of the code stream can be restored by using the result of the hard decision, and is used in the area integration operation in S13.
S23: taking two adjacent rising edges of the data clock as integration areas, and carrying out area integration operation on the digital signals with signs;
after analog-to-digital conversion and preprocessing, the digital signal still has a sign, the digital signal is taken as an integration object, two adjacent rising edges of a data clock are taken as integration areas, the two adjacent rising edges are the code elements forming a data bit, and the decoding is carried out by using the judgment results obtained by the two integration areas, namely, the judgment mode obtained according to the FM0 coding rule.
The area of an integral area is used as a soft decision object, when burrs, duty ratio changes and bit rate changes occur, the existing decision method may have opposite decision results at the selected decision time, but by adopting the mode of the embodiment, the appearance of the burrs does not influence the positive and negative of the integral area generally, so that the soft decision object is more reliable.
S24: judging the integral operation result according to a preset judgment threshold to obtain a soft judgment result;
the integral operation result has a sign, and the numerical value of the integral operation result has a difference according to the size of the area, as an optimization, the judgment threshold is set to 0, whether the integral operation result is greater than 0 is judged, if so, the soft judgment result of the integral area is 1, otherwise, the soft judgment result of the integral area is 0. Each integration region corresponds to a soft decision result.
S25: and performing preset operation on the soft decision results of two adjacent integral areas, and outputting a decoding result.
Two integral regions, namely two code elements, form a complete data bit, so that the original FM0 coded data can be decoded according to the preset operation result of two soft decision results.
In this embodiment, the preset operation specifically includes: and carrying out exclusive OR operation on the soft decision results of two adjacent integration areas. The XOR operation is a simpler implementation but is not limited.
In the above embodiment, referring to the FM0 encoding principle, two adjacent rising edges of the data clock are used as integration regions, area integration is performed on the digital signal with the sign, soft decision is performed on the integration operation result with the sign, and decoding of one data bit is completed after preset operation is performed on the soft decision results of two adjacent integration regions, that is, two code elements. The decoding implementation form can eliminate the interference of burrs, duty ratio or bit rate change on the judgment result, thereby improving the accuracy of decoding.
Fig. 3 shows a bi-phase space code-oriented decoding device structure, including:
the sampling and preprocessing module 31 is configured to sample a biphase interval code FM0 code stream, and perform analog-to-digital conversion and preprocessing on the code stream to obtain a digital signal with positive and negative symbols;
a hard decision module 32, configured to perform hard decision on the digital signal with positive and negative symbols;
a clock extraction module 33, configured to extract a data clock from the hard decision result;
the area integral calculation module 34 is configured to perform an area integral operation on the signed digital signal by using two adjacent rising edges of the data clock as an integral region;
a soft decision module 35, configured to decide the integral operation result according to a preset decision threshold to obtain a soft decision result;
the soft decision module 35 is specifically implemented:
acquiring an integral operation result;
and judging whether the integral operation result is greater than 0, if so, the soft decision result of the integral area is 1, otherwise, the soft decision result of the integral area is 0.
And the decoding output module 36 is configured to perform preset operation on the soft decision results of two adjacent integration areas, and output a decoding result.
The decoding output module 36 specifically implements: and performing exclusive OR operation on the soft decision results of two adjacent integral areas and outputting a decoding result.
The above-mentioned apparatus is a functional module corresponding to each step of the method in the embodiment and the diagram of fig. 2, and the apparatus defined by such functional module is a functional module framework for implementing the technical solution of the present invention.
Fig. 4 shows a bi-phase space code-oriented decoding apparatus, including:
the sampling and preprocessing device 41 comprises: an analog-to-digital conversion unit 411 and a preprocessing unit 412;
the sampling and preprocessing device 41 samples the biphase interval code FM0 code stream, and performs analog-to-digital conversion and preprocessing on the code stream to obtain a digital signal with positive and negative symbols;
and, a decoding controller 42 including: a decoding chip 421 and a memory chip 422, wherein;
the decoding chip 421 executes the instructions in the memory chip 422, and the decoding chip 421 is provided with a corresponding circuit for executing the instructions in the memory chip 422;
the instructions of the memory chip 422 include:
carrying out hard decision on the digital signal with the positive and negative symbols, and extracting a data clock from a hard decision result;
preferably, the corresponding circuit provided by the decoding chip for executing the instruction of extracting the data clock is a digital phase-locked loop.
Taking two adjacent rising edges of the data clock as integration areas, and carrying out area integration operation on the digital signals with signs;
judging the integral operation result according to a preset judgment threshold to obtain a soft judgment result;
the above command may preferably be:
acquiring an integral operation result;
and judging whether the integral operation result is greater than 0, if so, the soft decision result of the integral area is 1, otherwise, the soft decision result of the integral area is 0.
And performing preset operation on the soft decision results of two adjacent integral areas, and outputting a decoding result.
The decoding chip 421 reads and executes the instructions in the storage chip 422, and the type of the decoding chip and the type of the storage chip are not limited, and the instructions may be placed in a Random Access Memory (RAM), a memory, a Read Only Memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The decoding device can be interpreted as an RSU, and includes the above sampling and preprocessing device 41 and the decoding controller 42, in addition to necessary sensing devices and hardware tools, decoding chips in the sampling and preprocessing device 41 and the decoding controller 42 can be realized by an FPGA, the RSU further includes a main control CPU, and the CPU realizes functions of controlling other components of the RSU; the decoding device may also be interpreted as an independent decoding tool, implementing a decoding function, and may cooperate with other components in the rsu 52 to implement the rsu function.
Fig. 5 shows a biphase-space-code oriented communication system comprising:
an on-board unit 51 and a roadside unit 52, the roadside unit 52 comprising:
fig. 4 illustrates a bi-phase space code oriented decoding device and its corresponding description. In this embodiment, the decoding device may be interpreted as an independent decoding tool provided in the rsu 52, implementing the decoding function, and cooperating with other components in the rsu 52 to complete the rsu function.
In summary, the following steps:
according to the embodiment of the invention, a data clock is extracted according to a hard decision result of a digital signal after code stream preprocessing, and by taking two adjacent rising edges of the data clock as integration regions according to an FM0 coding principle, area integration is carried out on the digital signal with the sign, soft decision is carried out on the integration operation result with the sign, and decoding of one data bit is completed after preset operation is carried out on the soft decision results of two adjacent integration regions, namely two code elements. The decoding implementation form can eliminate the interference of burrs, duty ratio or bit rate change on the judgment result, thereby improving the accuracy of decoding.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. In the foregoing specification, components and steps of various examples have been described generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
For the controller and system embodiments, since they substantially correspond to the method embodiments, they are described relatively simply, and reference may be made to some of the descriptions of the method embodiments for relevant points. The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the embodiments. Thus, the present embodiments are not intended to be limited to the embodiments shown herein but are to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A bi-phase space code-oriented decoding method, comprising:
sampling a biphase interval code FM0 code stream, and performing analog-to-digital conversion and pretreatment on the code stream to obtain a digital signal with positive and negative symbols;
carrying out hard decision on the digital signal with the positive and negative symbols, and extracting a data clock from a hard decision result;
taking two adjacent rising edges of the data clock as an integration area, and carrying out area integration operation on the digital signal with the positive sign and the negative sign;
judging the integral operation result according to a preset judgment threshold to obtain a soft judgment result;
performing preset operation on the soft decision results of two adjacent integral areas, and outputting a decoding result;
wherein, the judging the integral operation result according to a preset judgment threshold comprises:
acquiring an integral operation result;
and judging whether the integral operation result is greater than 0, if so, the soft decision result of the integral area is 1, otherwise, the soft decision result of the integral area is 0.
2. The bi-phase space code-oriented decoding method of claim 1, wherein extracting the data clock from the hard decision result comprises:
and extracting a data clock from the hard decision result by adopting an all-digital phase-locked loop.
3. The bi-phase space code-oriented decoding method of claim 1, wherein the pre-determining operation on the soft decision results of two adjacent integration regions comprises:
and carrying out exclusive OR operation on the soft decision results of two adjacent integration areas.
4. A bi-phase space code-oriented decoding apparatus, comprising:
the sampling and preprocessing module is used for sampling a biphase interval code FM0 code stream, and performing analog-to-digital conversion and preprocessing on the code stream to obtain a digital signal with positive and negative symbols;
the hard decision module is used for carrying out hard decision on the digital signal with the positive and negative symbols;
the clock extraction module is used for extracting a data clock from the hard decision result;
the area integral calculation module is used for taking two adjacent rising edges of the data clock as an integral area and carrying out area integral operation on the digital signal with the positive sign and the negative sign;
the soft decision module is used for deciding the integral operation result according to a preset decision threshold to obtain a soft decision result;
the decoding output module is used for carrying out preset operation on the soft decision results of two adjacent integral areas and outputting a decoding result;
wherein,
the soft decision module is specifically implemented as follows:
acquiring an integral operation result;
and judging whether the integral operation result is greater than 0, if so, the soft decision result of the integral area is 1, otherwise, the soft decision result of the integral area is 0.
5. The bi-phase space code-oriented decoding device as claimed in claim 4, wherein the decoding output module is further configured to: and performing exclusive OR operation on the soft decision results of two adjacent integral areas and outputting a decoding result.
6. A bi-phase space code-oriented decoding device, comprising:
sampling and preprocessing apparatus comprising: the device comprises an analog-digital conversion unit and a preprocessing unit;
the sampling and preprocessing device is used for sampling a biphase interval code FM0 code stream, and performing analog-to-digital conversion and preprocessing on the code stream to obtain a digital signal with positive and negative symbols;
and, a decoding controller comprising: a decoding chip and a memory chip, wherein;
the decoding chip executes the instructions in the storage chip and is provided with a corresponding circuit for executing the instructions in the storage chip;
the instructions of the memory chip include:
carrying out hard decision on the digital signal with the positive and negative symbols, and extracting a data clock from a hard decision result;
taking two adjacent rising edges of the data clock as an integration area, and carrying out area integration operation on the digital signal with the positive sign and the negative sign;
judging the integral operation result according to a preset judgment threshold to obtain a soft judgment result;
performing preset operation on the soft decision results of two adjacent integral areas, and outputting a decoding result;
wherein the instruction for deciding the integral operation result according to a preset decision threshold comprises:
acquiring an integral operation result;
and judging whether the integral operation result is greater than 0, if so, the soft decision result of the integral area is 1, otherwise, the soft decision result of the integral area is 0.
7. The biphase-spaced code-oriented decoding apparatus of claim 6,
the circuit which is arranged by the decoding chip and used for extracting the data clock instruction from the hard decision result is an all-digital phase-locked loop.
8. The biphase-spaced code-oriented decoding apparatus of claim 6,
the instruction for performing preset operation on the soft decision results of two adjacent integration areas comprises the following steps:
and carrying out exclusive OR operation on the soft decision results of two adjacent integration areas.
9. A biphase-spaced code oriented communication system, comprising:
on-vehicle unit and road side unit, the road side unit includes:
the bi-phase space code oriented decoding apparatus of claims 6-8.
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| CN111262652B (en) * | 2019-12-17 | 2023-01-10 | 航天信息股份有限公司 | Method and system for decoding FM0 code based on edge detection |
| CN112184934B (en) * | 2020-09-30 | 2022-06-03 | 广州市埃特斯通讯设备有限公司 | Method and system for decoding FM0 coded data of ETC |
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