CN103681777B - Junction field effect pipe - Google Patents
Junction field effect pipe Download PDFInfo
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- CN103681777B CN103681777B CN201210320108.XA CN201210320108A CN103681777B CN 103681777 B CN103681777 B CN 103681777B CN 201210320108 A CN201210320108 A CN 201210320108A CN 103681777 B CN103681777 B CN 103681777B
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- 230000005669 field effect Effects 0.000 title claims abstract description 58
- 238000002347 injection Methods 0.000 claims description 35
- 239000007924 injection Substances 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 25
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 23
- 229910052760 oxygen Inorganic materials 0.000 claims description 23
- 239000001301 oxygen Substances 0.000 claims description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 239000000945 filler Substances 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 7
- 238000000605 extraction Methods 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of junction field effect pipe, it is to be integrated with a LDMOS in junction field effect pipe.Device pinch-off voltage can be injected by the grid single or multiple of junction field effect pipe and adjust, and electric current density can adjust by controlling channel width.Meanwhile, integrated LDMOS improves the voltage endurance of junction field effect pipe.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to a kind of junction field effect pipe.
Background technology
The most conventional JFET (junction field effect pipe) is divided by pinch off mode horizontal pinch off and longitudinal pinch off two kinds.Horizontal
To pinch off JFET as it is shown in figure 1, the raceway groove N-type trap doping 402 of JFET device is formed in P type substrate 401, table
Face has an oxygen 405 to isolate, and is injected with p-type trap doping 403 outside n-type doping 402, and both sides use p-type active area respectively
404 draw and form grids 410, and channel length L4 is exactly the width of N-type trap, in pinch off works, owing to being to utilize N
Pinch off is exhausted between type trap 402 and p-type trap 403, so the width of N-type trap and concentration under the pinch-off voltage needed
Distribution is immutable, and therefore the JFET of horizontal pinch off mode cannot offer width can in the case of keeping pinch-off voltage
The device become.And longitudinal type JFET is as in figure 2 it is shown, the raceway groove n-type doping 502 of JFET device is formed at P type substrate
On 501, surface is injected with p-type doping 503, is formed with p-type active area 504a, and and N-type in p-type doping 503
P-type active area 504b outside trap connects together, and forms grid 510, has an oxygen 505 between active area 504a and 504b
Isolation, channel length L3 of longitudinal type JFET is i.e. N-type trap 502 and the depth difference of p-type trap 503, and not by N-type
Trap width limits, and so under the pinch-off voltage needed, can obtain difference by the width W3 of change N-type trap 502
The device of size of current.But in some process conditions, N-type trap can be pushed into the deepest, deep when N-type trap and p-type trap
After degree difference reaches necessarily, JFET will be unable to pinch off, and therefore the application of longitudinal type JFET is also by a definite limitation.
The most current used junction field effect pipe, pressure is by knot itself, improves pressure mode and relies primarily on fall
The concentration of low knot, but knot concentration does the light pressure pressure requirement of the superelevation (more than 300V) that is also unable to reach, and tie and be made too
Light also can cause that device current is the least, the problem of poor stability.
Summary of the invention
The technical problem to be solved is to provide a kind of junction field effect pipe, and it is adjustable that it has electric current density, and
It is provided simultaneously with the characteristic that superelevation is pressure.
For solving the problems referred to above, a kind of junction field effect pipe of the present invention, comprise a junction field effect pipe and
One LDMOS being integrated in junction field effect pipe (LDMOS:Laterally Diffused Metal Oxide
Semiconductor):
Having N-type injection region in P-type silicon substrate, in horizontal direction, N-type injection region is divided into source region drift region, ditch
Road district and drift region, drain region；
The drain region of described junction field effect pipe, is the first heavily doped N-type district of the side of drift region, drain region, and first is heavily doped
Contact hole and the first heavily doped N-type district in miscellaneous N-type region with filler metal are connected, by the drain region of junction field effect pipe
Draw, and the first heavily doped N-type district also serves as the drain region of integrated LDMOS simultaneously；
The source region of described junction field effect pipe, is the second heavily doped N-type district in source region drift region, described source region drift region
It is positioned in the N-type injection region of drift region, drain region opposite side, the second heavily doped N-type district has the contact being filled with metal
Hole is connected with the second heavily doped N-type district, the source region of junction field effect pipe is drawn；
The grid of described junction field effect pipe, for heavily doped P-type district, is positioned in the p-type injection region above channel region,
Described channel region, between source region drift region and drift region, drain region, has in the p-type injection region above channel region and mutually supports
It is abutted against tactile heavily doped P-type district and the 3rd heavily doped N-type district, described heavily doped P-type district has the contact of filler metal
Hole is attached thereto extraction, and the contact hole that described 3rd heavily doped N-type district has filler metal contacts extraction, heavily doped
Silicon face between miscellaneous p type island region and the second heavily doped N-type district has the oxygen isolation of source region field, and the source region of described LDMOS is by weight
Doped p-type district and the 3rd heavily doped N-type district collectively form, and described p-type injection region is as the channel region of LDMOS；
Silicon face between described first heavily doped N-type district and the 3rd heavily doped N-type district has field, drain region oxygen isolates and one section
Oxide-film, has one layer of p-type doped region in the N-type injection region below the oxygen of field, drain region；
Described oxide-film silicon face between the 3rd heavily doped N-type district and field, drain region oxygen, on oxide-film and near oxidation
Covering one layer of polysilicon on field, the drain region oxygen of film, polysilicon is drawn by the contact hole that polysilicon has filler metal, is formed
The grid of described LDMOS；
Field, drain region oxygen covers one section of polysilicon on the region in the first heavily doped N-type district and forms drain region field plate, and by filling out
The contact hole filling metal is drawn；
Whole device surface deposit inter-level dielectric, each region is drawn by described contact hole whole break-through inter-level dielectric；
Have metal to form each electrode of whole device respectively at inter-level dielectric surface deposition, wherein heavily doped P-type district,
Three heavily doped N-type districts and near the 3rd heavily doped N-type district polysilicon by contact hole connect same metal, first
The contact hole in heavily doped N-type district is connected to another nugget genus with the contact hole of drain region field plate.
Further, described p-type injection region is once to inject formation, or repeatedly injects formation, to form difference
The junction field effect pipe of pinch-off voltage.
Further, in top plan view, the drain region and the grid that are integrated with the junction field effect pipe of LDMOS are circular knots
Structure.
Further, described circular configuration be drain region in inner side, grid is in outside.
Further, the grid in the outside of described circular configuration is extended with the N-type injection region of rectangle, forms junction type field, face effect
Should the source region of pipe.
Further, changing described each injection region is that counter ion injects type, i.e. forms p-type junction field effect pipe.
Junction field effect pipe of the present invention, utilize the p-type injection region of grid single or repeatedly inject regulate
Pinch-off voltage, forms longitudinal pinch off so that electric current density can adjust according to channel width, imitates in junction type field, face meanwhile
The drain region of pipe should be integrated with LDMOS so that junction field effect pipe has the characteristic that superelevation is pressure.
Accompanying drawing explanation
Fig. 1 is tradition laterally junction field effect pipe profile；
Fig. 2 is tradition longitudinal surface technotron profile；
Fig. 3 is the profile of junction field effect pipe of the present invention；
Fig. 4 is the top plan view of junction field effect pipe of the present invention.
Description of reference numerals
401,501,101 is P type substrate, and 402,502 is N-type trap, and 403,503 is p-type trap, 404,504a,
504b is heavily doped P-type district, and 405,505 is an oxygen, and 410,510 is grid, and L3, L4 are channel lengths, W3
Being N trap width, 102 is N-type injection region, and 103 is p-type injection region, and 104 is p-type doped region, and 105 is an oxygen,
106 is the 3rd heavily doped N-type district, and 107 is the first heavily doped N-type district, and 108 is heavily doped P-type district, 109,110,
201 is polysilicon, and 111,112 is metal, and 114 is the second heavily doped N-type district, and 202 is LDMOS source region, 203
Being oxide-film, 204 is source region drift region, and 301 is drain region, and 302 is source region, and 303 is grid, and 304 is junction type field, face
Effect pipe channel region, 308 is inter-level dielectric, and Ls, Ld are distances.
Detailed description of the invention
The cross-section structure of junction field effect pipe of the present invention is as it is shown on figure 3, it comprises a junction field effect pipe
With a LDMOS being integrated in junction field effect pipe.
Having N-type injection region 102 in P-type silicon substrate 101, in horizontal direction, N-type injection region 102 is divided into source
Drift region, district 204, channel region 304 and drift region, drain region 208.
There is the first heavily doped N-type district 107, the first heavily doped N-type district 107 in the surface, side of drift region, drain region 208
On there is the contact hole of filler metal and the first heavily doped N-type district 107 is connected, by the drain region 301 of junction field effect pipe
Draw.
Source region drift region 204 is positioned in the N-type injection region 102 of drift region, drain region 208 opposite side, source region drift region 204
In there is the second heavily doped N-type district 114, the second heavily doped N-type district 114 has the contact hole and being filled with metal
Two heavily doped N-type districts 114 connect, and the source region 302 of junction field effect pipe are drawn.
Described channel region 304, between source region drift region 204 and drift region, drain region 208, has above channel region 304
P-type injection region 103, has the heavily doped P-type district 108 and the 3rd abutting contact in described p-type injection region 103
Heavily doped N-type district 106, the contact hole that described heavily doped P-type district 108 has filler metal is attached thereto extraction, shape
Become the grid 303 of junction field effect pipe, described 3rd heavily doped N-type district 106 has the contact hole of filler metal with
Contact draw, the silicon face between heavily doped P-type district 108 and the second heavily doped N-type district 114 has source region field oxygen 105
Isolation.Distance Ls between p-type injection region 103 and the second heavily doped N-type district 114 > 2 μm.
Silicon face between described first heavily doped N-type district 107 and the 3rd heavily doped N-type district 106 have field, drain region oxygen every
From 105 and one section of thin oxide film 203, the N-type injection region 102 below field, drain region oxygen 105 has one layer of p-type doped region
104, length Ld of field, drain region oxygen 105 > 20 μm, when drain region 301 adds high pressure, it is provided that hole ion is more prone to consumption
District is to improve the pressure of drain region to the greatest extent.
The described oxide-film 203 silicon face between the 3rd heavily doped N-type district 106 and field, drain region oxygen 105, oxide-film
Cover one layer of polysilicon 201 on 203 and on field, the drain region oxygen 105 of oxide-film 203, polysilicon 201 has and fills out
Polysilicon 201 is drawn by the contact hole filling metal.
Field, drain region oxygen 105 covers one section of polysilicon 110 on the region in the first heavily doped N-type district 107 and forms field, drain region
Plate, and drawn by the contact hole of filler metal.
Whole device surface deposit inter-level dielectric 308, each region is drawn by described contact hole whole break-through inter-level dielectric 308
Go out.
Metal is had to form each electrode of whole device, wherein heavily doped P-type district respectively at inter-level dielectric 308 surface deposition
108, the 3rd heavily doped N-type district 106 and the polysilicon 201 near the 3rd heavily doped N-type district 106 pass through contact hole
Connecting same metal 111, the contact hole in the first heavily doped N-type district 107 is connected same with the contact hole of drain region field plate 110
One nugget genus 112.
Above-mentioned junction field effect pipe, drain region 301 is the shared drain region as junction field effect pipe and LDMOS, weight
Doped p-type district 108 is as the grid of junction field effect pipe, meanwhile, and heavily doped P-type district and the 3rd heavily doped N-type district
Constituting the source region of LDMOS, p-type injection region 103 is as the channel region of LDMOS.
As shown in Figure 4, being the top plan view of junction field effect pipe of the present invention, whole device is rounded.
In figure, the source region 202 of high pressure field effect transistor, the namely grid 303 of junction field effect pipe, whole drain region 301
Surrounding circular structure, the grid 303 outside circular configuration is extended with the N-type injection region 204 of rectangle (i.e. in Fig. 3
Drift region, drain region 204), form effective channel region of junction field effect pipe, channel width Wjfet>2μm。
By above-mentioned device architecture, the drain region of junction field effect pipe is integrated with a LDMOS, improves junction type field, face
The pressure performance of effect pipe, the region between p-type injection region 103 and substrate 101 forms longitudinal pinch off raceway groove so that face
The pinch-off voltage of technotron is more stable, controlled.P-type injection region 103 can divide single or multiple to inject, to be formed
The junction field effect pipe of different pinch-off voltages.Meanwhile, changing described each injection region is that counter ion injects type, can
Form p-type junction field effect pipe.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For a person skilled in the art,
The present invention can have various modifications and variations.All within the spirit and principles in the present invention, any amendment of being made, equivalent
Replacement, improvement etc., should be included within the scope of the present invention.
Claims (6)
1. a junction field effect pipe, it is characterised in that: comprise a junction field effect pipe and one be integrated in face
LDMOS in technotron:
Having N-type injection region in P-type silicon substrate, in horizontal direction, N-type injection region is divided into source region drift region, ditch
Road district and drift region, drain region；
The drain region of described junction field effect pipe, is the first heavily doped N-type district of the side of drift region, drain region, and first is heavily doped
Contact hole and the first heavily doped N-type district in miscellaneous N-type region with filler metal are connected, by the drain region of junction field effect pipe
Draw, and the first heavily doped N-type district also serves as the drain region of integrated LDMOS simultaneously；
The source region of described junction field effect pipe, is the second heavily doped N-type district in source region drift region, described source region drift region
It is positioned in the N-type injection region of drift region, drain region opposite side, the second heavily doped N-type district has the contact being filled with metal
Hole is connected with the second heavily doped N-type district, the source region of junction field effect pipe is drawn；
The grid of described junction field effect pipe, for heavily doped P-type district, is positioned in the p-type injection region above channel region,
Described channel region, between source region drift region and drift region, drain region, has in the p-type injection region above channel region and mutually supports
It is abutted against tactile heavily doped P-type district and the 3rd heavily doped N-type district, described heavily doped P-type district has the contact of filler metal
Hole is attached thereto extraction, and the contact hole that described 3rd heavily doped N-type district has filler metal contacts extraction, heavily doped
Silicon face between miscellaneous p type island region and the second heavily doped N-type district has the oxygen isolation of source region field, and the source region of described LDMOS is by weight
Doped p-type district and the 3rd heavily doped N-type district collectively form, and described p-type injection region is as the channel region of LDMOS；
Silicon face between described first heavily doped N-type district and the 3rd heavily doped N-type district has field, drain region oxygen isolates and one section
Oxide-film, has one layer of p-type doped region in the N-type injection region below the oxygen of field, drain region；
Described oxide-film silicon face between the 3rd heavily doped N-type district and field, drain region oxygen, on oxide-film and near oxidation
Covering one layer of polysilicon on field, the drain region oxygen of film, polysilicon is drawn by the contact hole that polysilicon has filler metal, is formed
The grid of described LDMOS；
Field, drain region oxygen covers one section of polysilicon on the region in the first heavily doped N-type district and forms drain region field plate, and by filling out
The contact hole filling metal is drawn；
Whole device surface deposit inter-level dielectric, each region is drawn by described contact hole whole break-through inter-level dielectric；
Have metal to form each electrode of whole device respectively at inter-level dielectric surface deposition, wherein heavily doped P-type district,
Three heavily doped N-type districts and near the 3rd heavily doped N-type district polysilicon by contact hole connect same metal, first
The contact hole in heavily doped N-type district is connected to another nugget genus with the contact hole of drain region field plate.
2. junction field effect pipe as claimed in claim 1, it is characterised in that: described p-type injection region is once
Inject and formed, or repeatedly inject formation, to form the junction field effect pipe of different pinch-off voltage.
3. junction field effect pipe as claimed in claim 1, it is characterised in that: in top plan view, it is integrated with LDMOS
The drain region of junction field effect pipe and grid be circular configuration.
4. junction field effect pipe as claimed in claim 3, it is characterised in that: described circular configuration is including drain region
Side, grid is in outside.
5. junction field effect pipe as claimed in claim 4, it is characterised in that: the grid in the outside of described circular configuration
Pole is extended with the N-type injection region of rectangle, forms the source region of junction field effect pipe.
6. junction field effect pipe as claimed in claim 1, it is characterised in that: it is contrary for changing described each injection region
Ion implanting type, i.e. forms p-type junction field effect pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210320108.XA CN103681777B (en) | 2012-08-31 | 2012-08-31 | Junction field effect pipe |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210320108.XA CN103681777B (en) | 2012-08-31 | 2012-08-31 | Junction field effect pipe |
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| CN103681777A CN103681777A (en) | 2014-03-26 |
| CN103681777B true CN103681777B (en) | 2016-11-02 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104518034B (en) * | 2014-06-17 | 2020-11-24 | 上海华虹宏力半导体制造有限公司 | JFET device and manufacturing method thereof |
| CN105702678B (en) * | 2016-01-29 | 2018-08-21 | 上海华虹宏力半导体制造有限公司 | The integrated morphology and its manufacturing method of LDMOS and JFET |
| CN105810680B (en) * | 2016-03-15 | 2019-06-11 | 上海华虹宏力半导体制造有限公司 | JFET and its manufacturing method |
| CN105679820B (en) * | 2016-03-16 | 2018-08-21 | 上海华虹宏力半导体制造有限公司 | JFET and its manufacturing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6475870B1 (en) * | 2001-07-23 | 2002-11-05 | Taiwan Semiconductor Manufacturing Company | P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture |
| CN1849710A (en) * | 2004-02-24 | 2006-10-18 | 崇贸科技股份有限公司 | High voltage ldmos transistor having an isolated structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3749191B2 (en) * | 2001-03-22 | 2006-02-22 | 松下電器産業株式会社 | High voltage semiconductor device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6475870B1 (en) * | 2001-07-23 | 2002-11-05 | Taiwan Semiconductor Manufacturing Company | P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture |
| CN1849710A (en) * | 2004-02-24 | 2006-10-18 | 崇贸科技股份有限公司 | High voltage ldmos transistor having an isolated structure |
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