CN203690304U - Vertical super junction metal-oxide -semiconductor field effect transistor - Google Patents
Vertical super junction metal-oxide -semiconductor field effect transistor Download PDFInfo
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- CN203690304U CN203690304U CN201320854677.2U CN201320854677U CN203690304U CN 203690304 U CN203690304 U CN 203690304U CN 201320854677 U CN201320854677 U CN 201320854677U CN 203690304 U CN203690304 U CN 203690304U
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- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 36
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 36
- 230000005669 field effect Effects 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims description 42
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 230000007704 transition Effects 0.000 claims description 4
- 230000009466 transformation Effects 0.000 claims description 3
- 238000009826 distribution Methods 0.000 abstract description 7
- 230000005684 electric field Effects 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000002547 anomalous effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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Abstract
The utility model provides a vertical super junction metal-oxide -semiconductor field effect transistor (MOSFET), comprising an N type doped semiconductor substrate and an N type doped epitaxial layer successively arranged from down to top. The N type doped epitaxial layer, from inside to outside, is internally provided with first P type filling well regions and second P type filling well regions which have a same structure; the upper sides of the first P type filling well regions are provided with first P type doped regions; the upper sides of the second P type filling well regions are provided with second P type doped regions and P type doped equipotential rings from inside to outside, and the three commonly form a terminal overpressure resistant structure area T. The second P type doped regions correspond with a plurality of the second P type filling well regions; the widths of the P type doped equipotential rings are greater than the widths of the second P type filling well regions; the P type doped equipotential rings at intervals are correspondingly arranged parallelly just above the second P type filling well regions in the length direction of a transistor; the P type doped regions are internally provided with the N type doped regions and form a primitive cell source area C with the first P type filling well regions; surface electromotive force distribution is optimized.
Description
Technical field
The utility model belongs to semiconductor power device technology field, relates to a kind of high voltage power device, concrete a kind of longitudinally super-junction metal oxide field effect transistor.
Background technology
Conventional high-tension power metal oxide semiconductor field-effect transistor device is made voltage support layer with low-doped extension drift layer, and its conducting resistance is exactly mainly drift layer resistance.The voltage endurance capability of drift layer is determined by its thickness and doping content.So, in order to improve puncture voltage, must increase drift layer thickness simultaneously and reduce its doping content.This just makes the resistance of drift layer constantly increase, and in the time of conducting state when high pressure (especially), drift layer resistance accounts for the overwhelming majority of conducting resistance.
Super-junction metal oxide field effect transistor is the new device that a kind of insulated gate structure advantage with metal oxide semiconductor transistor has high current density low on-resistance advantage simultaneously, and it is a kind of power semiconductor that can be used for the conduction loss that effectively reduces traditional power metal oxide semiconductor field-effect transistor.It is the charge compensation type device based on charge balance concept.
The basic characteristics of super-junction metal oxide field effect transistor are that its drift region being made up of the region of interval n-and p-doping is realized withstand voltage.Conventional high-tension power metal oxide semiconductor field-effect transistor device in the time bearing high back voltage, its mainly rely on PN junction longitudinally exhaust realize withstand voltagely, at the pn of whole device knot, place there will be electric field strength peak value.And super-junction metal oxide field effect transistor is owing to having introduced charge compensation mechanism, its inside is exhausting when withstand voltage, Electric Field Distribution is more even, with the triangle peak value Electric Field Distribution of conventional high-tension power metal oxide semiconductor field-effect transistor device, the device inside electric field of super-junction metal oxide field effect transistor is distributed rectangular in longitudinal withstand voltage direction.Rectangle electric-field intensity distribution, makes its whole device exhausting in withstand voltage process, does not occur anomalous electric field peak value.Owing to making p type island region in vertical direction, can compensate excessive current lead-through electric charge.Add reverse bias voltage at drift layer, electric field will produce cross stream component, and pn knot is exhausted.In the time that voltage reaches certain value, drift layer exhausts completely, will play the effect of voltage support layer.Therefore the impurity doping content of its voltage support layer can improve an order of magnitude nearly, and due to the significantly raising of doping content, under identical puncture voltage, conducting resistance can reduce greatly.Therefore pass through continuous Improvement and perfection, the new construction of super-junction metal oxide field effect transistor device constantly occurs.
Also be the focus that researcher pays close attention to for the design of super-junction metal oxide field effect transistor terminal structure always.Super-junction metal oxide field effect transistor terminal structure is different from conventional high-tension power metal oxide semiconductor field-effect transistor device, and the design of its structure can combine with inner super-junction structure.In correlation technique, there is designer to propose to change the width ratio in pn region, also there is designer to propose cycle of dwindling by multiplying power PN doped region etc.These methods are all better withstand voltage in order to realize super-junction metal oxide field effect transistor terminal structure.But in prior art, the terminal structure of super-junction metal oxide effect transistor is due to surface potential skewness, and surface leakage phenomenon easily occurs on the surface of its terminal pressure-resistance structure, can cause the gathering of mobile ion simultaneously, makes the withstand voltage decline of device.
Utility model content
The problem that the utility model solves is to provide a kind of longitudinally super-junction metal oxide field effect transistor, has optimized surface potential distribution, has reduced surface field, prevents surface leakage.
The utility model is to be achieved through the following technical solutions:
The longitudinal super-junction metal oxide field effect transistor of the utility model, comprises the N-type dope semiconductor substrates and the N-type doped epitaxial layer that set gradually from top to bottom; N-type doped epitaxial layer inside is provided with from inside to outside the P type that structure is identical and fills well region and the 2nd P type filling well region, and the upside that a P type is filled well region is provided with a P type doped region; The 2nd P type is filled well region upside from interior to being outwards provided with the 2nd P type doped region and P type doping equipotential ring, and three forms terminal pressure-resistance structure region T jointly; Corresponding multiple the 2nd P types in the 2nd P type doped region are filled well region setting; The width of P type doping equipotential ring is greater than the 2nd P type fills the width of well region, be spaced apart P type doping equipotential ring on transistorized length direction, be set in parallel in one to one respectively the 2nd P type fill well region directly over; In described P type doped region, be provided with N-type doped region, and jointly form primitive unit cell source region C with a P type filling well region; The terminal pressure-resistance structure region T that upper surface outermost is provided with N-type doped source contact zone is arranged in the periphery of primitive unit cell source region C.
Preferably, primitive unit cell source region C and terminal pressure-resistance structure region T top are provided with gate oxide, dielectric layer and upper metal level successively, in the dielectric layer of part gate oxide top, polysilicon are set; Upper metal level is connected to the part formation source metal electrode of a P type doped region, the 2nd P type doped region and top, N-type doped source contact zone through gate oxide and dielectric layer correspondence; The lower metal layer that is arranged on N-type dope semiconductor substrates below forms drain metal electrode; The part of the corresponding primitive unit cell source region C of polysilicon forms gate electrode, and the part of polysilicon counterpart terminal structural region T forms polysilicon field plate structure, and polysilicon field plate structure is connected with corresponding source metal electrode respectively.
Preferably, primitive unit cell source region C is formed by a P type filling well region and N-type doped epitaxial layer alternative arrangement on transistorized length direction; Terminal structure region T fills well region by the 2nd P type on transistorized length direction and N-type doped epitaxial layer alternative arrangement forms.
Further, P type doping equipotential ring on transistorized Width, be vertically installed in the 2nd P type fill well region directly over, in the time of direction transformation, adopt arc transition.
Further again, upper metal level is connected to the part formation Metal field plate structure of P type doping equipotential ring top through gate oxide and dielectric layer correspondence; Between Metal field plate structure and and source metal electrode between be separated from each other, Metal field plate structure extends to the upper outer of P type doping equipotential ring, and ends at the centre position of adjacent P type doping equipotential ring.
Preferably, in the outside of N-type doped epitaxial layer, be also provided with the 2nd P type being directly connected with gate oxide and fill well region.
Further, the doping content of P type doping equipotential ring is greater than the doping content of the 2nd P type filling well region, and the concentration of the 2nd P type filling well region is greater than the doping content of N-type doped epitaxial layer.
Preferably, a P type doped region is filled well region with a P type and is corresponding setting one by one, and the width of a P type doped region is greater than the width of a P type filling well region.
Compared with prior art, the utlity model has following useful technique effect:
(1), in the utility model terminal pressure-resistance structure region, fill well region top in the 2nd P type the 2nd P type doped region and P type doping equipotential ring are set.Reverse when withstand voltage when device, width is greater than the 2nd P type and fills well region and spaced apart at its surperficial P type doping equipotential ring, and making on the one hand the 2nd P type fill well region end can have larger PN junction contact-making surface ratio; Can coordinate on the one hand corresponding multiple the 2nd P types to fill the 2nd P type doped region of well region, form step configuration along withstand voltage direction, form corresponding with surperficial Potential Distributing, thereby the distribution that can realize region electromotive force is unified, optimize surface potential distribution, reduce surface and gathered electric field, terminal pressure-resistance structure has been punctured and there will not be surface leakage.
(2) the utility model, by the structure setting of P type doping equipotential ring, is ensureing, under the prerequisite of withstand voltage properties, can not increase device fabrication step, and it uses the well structure identical with the one P type doped region, primitive unit cell source area.
Further, utilize spaced in the longitudinal direction P type to fill well region and N-type doped epitaxial region, increase it horizontal withstand voltage, improved the reliability of its use; Configure simultaneously by arc transition and on Width vertically disposed P type doping equipotential ring, form the loop of charge movement on its surface, thereby it is more uniform and stable that surface potential is distributed, improve voltage endurance capability and job stability.
Further, utilize the Metal field plate structure that separates setting to realize blocking characteristics, the location layout of Metal field plate structure extends the electromotive force that has with it overlapping P type to fill well region after P type doping equipotential ring homogenizing again to the withstand voltage direction of terminal structure, do not have influence on again another adjacent with it P type and fill well region simultaneously, thereby the reduction surface field intensity relaxing, thereby increase the laterally withstand voltage of device.Meanwhile, Metal field plate has cut off the mobile route of mobile ion at dielectric layer after being directly connected with P type equipotential ring, has avoided the gathering of mobile ion to cause withstand voltage decline, has improved the withstand voltage reliability at high temperature or continuous firing adstante febre of transistor.
Further, utilize and be arranged on the 2nd P type filling well region that outside is directly connected with gate oxide, on the basis of the 2nd P type doped region and P type doping equipotential ring, the structure that its notch cuttype is arranged more steadily relaxes, and has ensured the equally distributed effect of electromotive force; And by the restriction of doping content, in ensureing charge balance, in withstand voltage direction, carry out the processing that doping content progressively increases, and reduce conducting resistance, improve voltage withstand class.
Brief description of the drawings
Fig. 1 is the surperficial schematic top plan view of the utility model part terminal pressure-resistance structure.
Fig. 2 be described in the utility model embodiment structure A-A ' shown in Fig. 1 to profile.
Fig. 3 is that the B-B ' of structure shown in the utility model Fig. 1 is to profile.
Fig. 4 is longitudinally super-junction metal oxide field effect transistor surface potential figure contrast under equal conditions in the utility model and prior art.
In figure: N-type dope semiconductor substrates 1, N-type doped epitaxial layer 2, the one P types are filled well region 31, the 2nd P type is filled 41, the two P type doped regions 42, well region 32, the one P type doped region, P type doping equipotential ring 43, N-type doped region 51, N-type doped source contact zone 52, gate electrode 61, polysilicon field plate structure 62, dielectric layer 7, source metal electrode 8, Metal field plate structure 9, drain metal electrode 10.
Embodiment
Below in conjunction with specific embodiment, the utility model is described in further detail, described in be to explanation of the present utility model instead of restriction.
The longitudinal super-junction metal oxide field effect transistor of the utility model, as shown in Figure 2, it comprises the N-type dope semiconductor substrates 1 and the N-type doped epitaxial layer 2 that set gradually from top to bottom; N-type doped epitaxial layer 2 inside are provided with from inside to outside a P type that structure is identical and fill well region 31 and the 2nd P type and fill well region 32, the one P types and fill the upside of well regions 31 and be provided with a P type doped region 41; The 2nd P type is filled well region 32 upsides from interior to being outwards provided with the 2nd P type doped region 42 and P type doping equipotential ring 43, and the described longitudinal super-junction metal oxide field effect transistor terminal pressure-resistance structure region T of the common formation of three; The 2nd corresponding multiple the 2nd P types in P type doped region 42 are filled well region 32 and are arranged; The width of P type doping equipotential ring 43 is greater than the 2nd P type fills the width of well region 32, be spaced apart P type doping equipotential ring 43 on transistorized length direction, be set in parallel in one to one respectively the 2nd P type fill well region 32 directly over; In described P type doped region 41, be provided with N-type doped region 51, and fill the common described longitudinal super-junction metal oxide field effect transistor primitive unit cell source region C of formation of well region 31 with a P type; The terminal pressure-resistance structure region T that upper surface outermost is provided with N-type doped source contact zone 52 is arranged in the periphery of primitive unit cell source region C; Primitive unit cell source region C and terminal pressure-resistance structure region T top are provided with gate oxide, dielectric layer 7 and upper metal level successively, the interior polysilicon that arranges of part gate oxide top dielectric layer 7; Upper metal level is connected to the part formation source metal electrode 8 of a P type doped region 41, the 2nd P type doped region 42 and 52 tops, N-type doped source contact zone through gate oxide and dielectric layer 7 correspondences; The lower metal layer that is arranged on N-type dope semiconductor substrates 1 below forms described in described longitudinal super-junction metal oxide field effect transistor longitudinally super-junction metal oxide field effect transistor drain metal electrode 10; The part of the corresponding primitive unit cell source region C of polysilicon forms described longitudinal super-junction metal oxide field effect transistor gate electrode 61, the part of polysilicon counterpart terminal structural region T forms polysilicon field plate structure 62, and polysilicon field plate structure 62 is connected with corresponding source metal electrode 8 respectively.
This preferred embodiment, as shown in Figure 2, wherein left side is after analysing and observe along A-A ' direction, minimum repetitive in the C of primitive unit cell source region, its width determines by transistorized conducting resistance and requirement of withstand voltage, quantity is not limit; Primitive unit cell source region C fills well region 31 by a P type on transistorized length direction and N-type doped epitaxial layer 2 alternative arrangements form; Terminal structure region T fills well region 32 by the 2nd P type on transistorized length direction and N-type doped epitaxial layer 2 alternative arrangements form.As shown in Figures 2 and 3, P type doping equipotential ring 43 on transistorized Width, vertically arrange the 2nd P type fill well region 32 directly over, in the time of direction transformation, adopt arc transition, as shown in Figure 1.
Wherein, as shown in Figures 2 and 3, upper metal level is connected to the part formation Metal field plate structure 9 of P type doping equipotential ring 43 tops through gate oxide and dielectric layer 7 correspondences; Between Metal field plate structure 9 and and source metal electrode 8 between be separated from each other, Metal field plate structure 9 extends to the upper outer of P type doping equipotential ring 43, and ends at the centre position of adjacent P type doping equipotential ring 43.As shown in Figure 2, in the outside of N-type doped epitaxial layer 2, be also provided with the 2nd P type being directly connected with gate oxide and fill well region 32.
In this preferred embodiment, the doping content of P type doping equipotential ring 43 is greater than the doping content of the 2nd P type filling well region 32, and the concentration of the 2nd P type filling well region 32 is greater than the doping content of N-type doped epitaxial layer 2.As shown in Figure 2, a P type doped region 41 is filled well region 31 with a P type and is corresponding setting one by one, and the width of a P type doped region 41 is greater than the width of a P type filling well region 31.
The utility model is not increasing under the prerequisite of technology difficulty and cost, when can ensureing requirement of withstand voltage, can not increase extra technique manufacture process, can not lengthen the original size of terminal structure, and the surface potential that can better optimize terminal structure distributes, effectively reduce surperficial electric field strength, the path that blocking-up mobile ion moves, the reliability of raising device.Its result of the test as shown in Figure 4, can clearly show that transistorized surface potential described in the utility model distributes than transistorized surface potential in prior art more even, and electric field strength reduces, and there will not be and concentrates electric leakage; The transistorized voltage withstand class of the utility model will be higher than transistorized voltage withstand class in prior art simultaneously.
The utility model is adopted with the following method and is prepared:
1), get a N-type high-concentration dopant silicon chip as N-type dope semiconductor substrates 1, epitaxial growth N-type doped epitaxial layer 2;
2), adopt deep groove etching and silicon backfilling process, flattening surface to process a P type filling well region 31 and the 2nd P type that rear formation structure is identical and fill well region 32;
3), adopt Implantation and follow-up annealing process to form a P type doped region 41, the 2nd P type doped region 42 and the P type doping equipotential ring 43 that well structure is identical;
3), then generate gate oxide through overheated growth, then depositing polysilicon, and carry out etching and form grid 61 and polysilicon field plate structure 62, then form N-type doped region 51 and N-type doped source contact area 52 through Implantation;
4), through deposit and etching technics, form source metal electrode 8 as transistorized source electrode, Metal field plate structure 9 is as transistor field plate, drain metal electrode 10 is as transistorized drain electrode.Finally carry out follow-up Passivation Treatment.
Claims (8)
1. longitudinal super-junction metal oxide field effect transistor, is characterized in that, comprises the N-type dope semiconductor substrates (1) and the N-type doped epitaxial layer (2) that set gradually from top to bottom; N-type doped epitaxial layer (2) inside is provided with from inside to outside the P type that structure is identical and fills well region (31) and the 2nd P type filling well region (32), and the upside that a P type is filled well region (31) is provided with a P type doped region (41); The 2nd P type is filled well region (32) upside from interior to being outwards provided with the 2nd P type doped region (42) and P type doping equipotential ring (43), and three forms terminal pressure-resistance structure region T jointly; Corresponding multiple the 2nd P types in the 2nd P type doped region (42) are filled well region (32) setting; The width of P type doping equipotential ring (43) is greater than the 2nd P type fills the width of well region (32), be spaced apart P type doping equipotential ring (43) on transistorized length direction, be set in parallel in one to one respectively the 2nd P type fill well region (32) directly over; In described P type doped region (41), be provided with N-type doped region (51), and jointly form primitive unit cell source region C with a P type filling well region (31); The terminal pressure-resistance structure region T that upper surface outermost is provided with N-type doped source contact zone (52) is arranged in the periphery of primitive unit cell source region C.
2. longitudinal super-junction metal oxide field effect transistor according to claim 1, it is characterized in that, described primitive unit cell source region C and terminal pressure-resistance structure region T top are provided with gate oxide, dielectric layer (7) and upper metal level successively, in part gate oxide top dielectric layer (7), polysilicon are set; Upper metal level is connected to the part formation source metal electrode (8) of a P type doped region (41), the 2nd P type doped region (42) and top, N-type doped source contact zone (52) through gate oxide and dielectric layer (7) correspondence; The lower metal layer that is arranged on N-type dope semiconductor substrates (1) below forms drain metal electrode (10); The part of the corresponding primitive unit cell source region C of polysilicon forms gate electrode (61), and the part of polysilicon counterpart terminal structural region T forms polysilicon field plate structure (62), and polysilicon field plate structure (62) is connected with corresponding source metal electrode (8) respectively.
3. longitudinal super-junction metal oxide field effect transistor according to claim 2, is characterized in that, described primitive unit cell source region C fills well region (31) by a P type on transistorized length direction and N-type doped epitaxial layer (2) alternative arrangement forms; Terminal structure region T fills well region (32) by the 2nd P type on transistorized length direction and N-type doped epitaxial layer (2) alternative arrangement forms.
4. longitudinal super-junction metal oxide field effect transistor according to claim 3, it is characterized in that, described P type doping equipotential ring (43) on transistorized Width, be vertically installed in the 2nd P type fill well region (32) directly over, in the time of direction transformation, adopt arc transition.
5. according to the longitudinal super-junction metal oxide field effect transistor described in claim 2 or 4, it is characterized in that, described upper metal level is connected to the part formation Metal field plate structure (9) of P type doping equipotential ring (43) top through gate oxide and dielectric layer (7) correspondence; Between Metal field plate structure (9) and and source metal electrode (8) between be separated from each other, Metal field plate structure (9) extends to the upper outer of P type doping equipotential ring (43), and ends at the centre position of adjacent P type doping equipotential ring (43).
6. longitudinal super-junction metal oxide field effect transistor according to claim 2, is characterized in that, is also provided with the 2nd P type being directly connected with gate oxide and fills well region (32) in the outside of described N-type doped epitaxial layer (2).
7. according to the longitudinal super-junction metal oxide field effect transistor described in claim 1 or 4 or 6, it is characterized in that, the doping content of described P type doping equipotential ring (43) is greater than the doping content of the 2nd P type filling well region (32), and the concentration of the 2nd P type filling well region (32) is greater than the doping content of N-type doped epitaxial layer (2).
8. longitudinal super-junction metal oxide field effect transistor according to claim 1, it is characterized in that, a described P type doped region (41) is filled well region (31) with a P type and is corresponding setting one by one, and the width of a P type doped region (41) is greater than the width of a P type filling well region (31).
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103700697A (en) * | 2013-12-20 | 2014-04-02 | 西安芯派电子科技有限公司 | Longitudinal super junction metal oxide field effect transistor |
| CN105304687A (en) * | 2014-07-28 | 2016-02-03 | 万国半导体股份有限公司 | End connection device for nanotube MOSFET |
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2013
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103700697A (en) * | 2013-12-20 | 2014-04-02 | 西安芯派电子科技有限公司 | Longitudinal super junction metal oxide field effect transistor |
| CN103700697B (en) * | 2013-12-20 | 2016-05-25 | 西安芯派电子科技有限公司 | Longitudinally super-junction metal oxide field effect transistor |
| CN105304687A (en) * | 2014-07-28 | 2016-02-03 | 万国半导体股份有限公司 | End connection device for nanotube MOSFET |
| CN105304687B (en) * | 2014-07-28 | 2019-01-11 | 万国半导体股份有限公司 | Termination design for nanotube MOSFET |
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Denomination of utility model: Longitudinal hyperjunction metal oxide field effect transistor device and production method thereof Effective date of registration: 20141128 Granted publication date: 20140702 Pledgee: Xi'an innovation financing Company limited by guarantee Pledgor: XI'AN SEMIPOWER ELECTRONIC TECHNOLOGY Co.,Ltd. Registration number: 2014990001014 |
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Date of cancellation: 20160301 Granted publication date: 20140702 Pledgee: Xi'an innovation financing Company limited by guarantee Pledgor: XI'AN SEMIPOWER ELECTRONIC TECHNOLOGY Co.,Ltd. Registration number: 2014990001014 |
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Denomination of utility model: Longitudinal hyperjunction metal oxide field effect transistor device and production method thereof Effective date of registration: 20160301 Granted publication date: 20140702 Pledgee: Xi'an innovation financing Company limited by guarantee Pledgor: XI'AN SEMIPOWER ELECTRONIC TECHNOLOGY Co.,Ltd. Registration number: 2016990000147 |
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