CN103647918B - Video synchronization method and device - Google Patents
Video synchronization method and device Download PDFInfo
- Publication number
- CN103647918B CN103647918B CN201310707676.XA CN201310707676A CN103647918B CN 103647918 B CN103647918 B CN 103647918B CN 201310707676 A CN201310707676 A CN 201310707676A CN 103647918 B CN103647918 B CN 103647918B
- Authority
- CN
- China
- Prior art keywords
- video
- field
- synchronization
- row
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000000872 buffer Substances 0.000 claims abstract description 31
- 238000005538 encapsulation Methods 0.000 claims abstract description 5
- 238000001514 detection method Methods 0.000 claims description 8
- 230000001360 synchronised effect Effects 0.000 claims description 8
- 230000001186 cumulative effect Effects 0.000 claims description 6
- 238000004364 calculation method Methods 0.000 abstract description 2
- 230000005055 memory storage Effects 0.000 description 5
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012536 storage buffer Substances 0.000 description 1
Landscapes
- Controls And Circuits For Display Device (AREA)
- Television Systems (AREA)
Abstract
The invention discloses a video synchronization method and device. The video synchronization method comprises detecting line timing and field timing parameters of input video signals, storing effective video pixel data into a BUFFER; calculating new timing parameters through calculation and utilization of a proportional relation of pixel clocks of input and output videos; delaying field-synchronizing signals of the input videos N-line time to serve as the field-synchronizing signals of input signals; generating BUFFER read enable signals which are used for reading pixel data from the BUFFER; aligning line synchronizing signals, the field-synchronizing signals and data effective signals with the pixel data and outputting post-encapsulation video streaming. The video synchronization method and device can achieve video synchronization without an external memory and reduce costs; can support synchronization processing of video signals of any resolution, enables the frame rate of the output video to be in accordance with the input video, and can maintain line and field timing formats of VESA (Video Electronics Standards Association) standards.
Description
Technical field
The present invention relates to video signal processing field, more particularly, to a kind of method and device of video synchronization.
Background technology
Show the form of vision signal by pixel clock, line synchronising signal, field sync signal, data valid signal and pixel
Data are constituted.Sequential format is as shown in Figure 2.
The pixel clock of the video of different resolution ratio is different, for video signal collective chip, internal process
All it is to carry out under unified clock, this is accomplished by that the video pixel data of input is synchronized on the process clock of inside.It is logical
Normal way has in the following manner：
First, frame buffer, one kind of the patent application publication of Application No. 201010578864.3 are done using external memory storage
The transmission method of picture signal, device and formatting method, device.Its disclosed method is by the video pixel data of input
All it is stored in external memory storage, then reuses the process clock of inside by digital independent out, realizes synchronizing.It is this
Method needs external memory storage, PCB surface product is occupied, while also increasing cost.And can only be less than for input resolution ratio
The video of 2160x1250, having exceeded this resolution ratio then cannot support.In addition no matter the frame per second of the video flowing of input is how many,
It is fixed frame per second to synchronize later frame per second, it is impossible to the characteristic of real reflection input video stream, defeated for holding is needed
The application scenario for entering the frame per second of video flowing script will be unable to support.
2nd, using an internal BUFFER, data are first cached in this BUFFER, as long as then this BUFFER is non-
Sky, just digital independent out, such as the self-defining ST of FPGA vendor As ltera flows bus format.This mode adopts one
BUFFER can be achieved with that video pixel data is synchronized on the process clock of inside, but it is original to destroy vision signal
Row, field sequential.If the processing module of rear end needs to retain the sequential for meeting VESA standards, this mode is then infeasible.
The content of the invention
In order to overcome above-mentioned prior art not enough, present invention firstly provides a kind of method of video synchronization, using the party
Method can reduce PCB surface product, so as to reduces cost without the need for external memory storage.
A further object of the present invention is to propose a kind of device of video synchronization.
To achieve these goals, the technical scheme is that：
A kind of method of video synchronization, including：
Input video format detection, detects row, the field time sequence parameter of incoming video signal, and by effective video pixel count
According to being saved in caching BUFFER, wherein the row, field time sequence parameter are included after row synchronization width, row synchronization crop, row synchronization
Shoulder, row total time, field synchronization width, field synchronization crop, field synchronization back porch, field total time, row resolution ratio, field resolution ratio and pixel
Clock frequency；
Output video format is calculated, and is calculated using the proportionate relationship of input video pixel clock and output video pixel clock
Go out new time sequence parameter, wherein output video line total time=output video pixel clock frequency * input video lines total time/defeated
Enter video pixel clock frequency；Other specification keeps identical with the vision signal of input；
Field sync signal postpones, and the field sync signal of input video is postponed the N row times as the field synchronization of output signal
Signal, N >=1 and the depth by the caching BUFFER for arranging determine；
Output video sequential occurs, and produces the video clock signal of output video, including line synchronising signal, field sync signal
And data valid signal；Produce caching BUFFER simultaneously to read to enable signal, for pixel data to be read from caching BUFFER
Out；
Video frame formats are encapsulated, and line synchronising signal, field sync signal, data valid signal and pixel data are alignd, defeated
The video flowing gone out after encapsulation.
A kind of device of video synchronization, including
Input video format detection module, for detecting row, the field time sequence parameter of incoming video signal, and will effectively regard
Frequency pixel data be saved in caching BUFFER in, wherein the row, field time sequence parameter include row synchronization width, row synchronization crop,
Row synchronization back porch, row total time, field synchronization width, field synchronization crop, field synchronization back porch, field total time, row resolution ratio, field are differentiated
Rate and pixel clock frequency；
Output video format computing module, for using the ratio of input video pixel clock and output video pixel clock
Relation calculates new time sequence parameter, wherein output video line total time=output video pixel clock frequency * input video lines are total
Time/input video pixel clock frequency；Other specification keeps identical with the vision signal of input；
Field sync signal Postponement module, for the field sync signal of input video to be postponed the N row times as output signal
Field sync signal, the N >=1 and depth by the caching BUFFER for arranging determines；
Output video timing sequencer, for producing the video clock signal of output video, including line synchronising signal, field are same
Step signal and data valid signal；Produce caching BUFFER simultaneously to read to enable signal, for by pixel data from caching BUFFER
In read out；
Video frame formats package module, for by line synchronising signal, field sync signal, data valid signal and pixel data
Alignment, the video flowing after output encapsulation.
Compared with prior art, beneficial effects of the present invention are：
1）Using the present invention realize video synchronization without the need for external memory storage, it is only necessary to which internal capacity very little is deposited
Storage BUFFER can just complete the cross clock domain synchronization of video flowing, reduce the device cost of system, also reduce the difficulty of PCB design
Degree and cost；
2）Internal work clock can be configured according to the scope of the resolution ratio being input into during actually used one it is suitable
Clock.Arbitrary resolution in the supported scope of internal work clock can be synchronized to intra clock domain by the present invention, be fitted
It is wide with scope；
3）Present invention can ensure that the video of output meets the row field synchronization form of VESA standards, from external interface,
The video flowing of output is consistent on form with the video flowing of input, can meet the interface requirements of generic video processing module；
4）The frame per second of present invention output video is consistent with the frame per second of input video, can truly reflect input video
Characteristic.
Description of the drawings
Fig. 1 is the structured flowchart of the device of video synchronization.
Fig. 2 is the form schematic diagram of existing display video sequential.
Specific embodiment
Below in conjunction with the accompanying drawings the present invention will be further described, but embodiments of the present invention are not limited to this.
Such as Fig. 1, input video format detection：By counter I cumulative 1 under each input video timeticks, per a line
At the end of reset, counter I can count the letters such as the synchronous width of trip, row synchronization crop, row synchronization back porch, effective row resolution ratio
Breath；By counter II cumulative 1 after every row terminates, reset during a frame end, counter II can count field synchronization width, field
The information such as synchronous crop, field synchronization back porch, effective field resolution ratio.Using a reference clock, the clock interval of T milliseconds is produced,
The pulse number N of statistical pixel clock in each time interval, you can the pixel clock for obtaining input video is N*1000/T
（Unit is Hz）.
Output video format is calculated：Using input video pixel clock and the proportionate relationship of output video pixel clock, root
According to the row total time for being calculated output video the row total time of input video, it is ensured that the absolute time of output videoscanning a line
It is consistent with the absolute time of scanning a line of input video.Specific formula for calculation is as follows：
During output video line total time=output video pixel clock frequency * input video lines total time/input video pixel
Clock frequency.
Other specification keeps identical with input video.The synchronous sequence of output video is generated according to the parameter after calculating, can
To dynamically adjust the horizontal blanking sector width of output video, ensure that caching BUFFER enters abnormal empty or full shape with this
State, also can guarantee that the frame per second of input is consistent with the frame per second of output.
Field sync signal postpones：The N row times are postponed as the field of output signal by the field sync signal using input video
Synchronizing signal, N >=1 and determined by the caching BUFFER depth for arranging at least has housed N rows and has had in caching BUFFER
Effect data just start reads pixel data as the pixel data of output video, prevent from caching BUFFER by reading sky singularly, protect
The correctness of card output video pixel data.
Output video timing sequencer：Using two counters, the field synchronization exported after postponing through field sync signal
Start counting up when signal starts effective, often row resets once counter 1, each output pixel clock cumulative 1, and counter 2 is per frame
Reset once, cumulative 1 after the complete a line of output videoscanning.According to output video format calculate obtain parameter, counter 1,
When counter 2 reaches corresponding count value, field sync signal, line synchronising signal, data valid signal complete 0 to 1 or 1 to 0
Upset.Enable data valid signal as reading the digital independent in BUFFER out simultaneously.
Video frame formats are encapsulated, and are that line synchronising signal, field sync signal, data valid signal are postponed into a bat, with pixel
Alignment of data, the video flowing after then output is encapsulated.
The embodiment of invention described above, does not constitute limiting the scope of the present invention.It is any at this
Done modification, equivalent and improvement etc. within bright spiritual principles, should be included in the claim protection of the present invention
Within the scope of.
Claims (4)
1. a kind of method of video synchronization, it is characterised in that include：
Input video format detection, detects row, the field time sequence parameter of incoming video signal, and effective video pixel data is protected
It is stored to cache in BUFFER, wherein the row, field time sequence parameter include row synchronization width, row synchronization crop, row synchronization back porch, OK
Total time, field synchronization width, field synchronization crop, field synchronization back porch, field total time, row resolution ratio, field resolution ratio and pixel clock
Frequency；
Output video format is calculated, and is calculated newly using the proportionate relationship of input video pixel clock and output video pixel clock
Time sequence parameter, wherein output video line total time=output video pixel clock frequency * input video lines total time/input regard
Frequency pixel clock frequency；Other specification keeps identical with the vision signal of input；
Field sync signal postpones, and the field sync signal of input video is postponed the N row times as the field sync signal of output signal,
N >=1 and the depth by the caching BUFFER for arranging determines；
Output video sequential occurs, and produces the video clock signal of output video, including line synchronising signal, field sync signal sum
According to useful signal；Produce caching BUFFER simultaneously to read to enable signal, for pixel data to be read out from caching BUFFER；
Video frame formats are encapsulated, by the alignment of line synchronising signal, field sync signal, data valid signal and pixel data, output envelope
Video flowing after dress；
Using counter I and counter II in input video format detection,
Wherein by counter I cumulative 1 under each input video timeticks, reset at the end of every a line, counter I is used to unite
The synchronous width of meter trip, row synchronization crop, row synchronization back porch, effective row resolution ratio；
By counter II after every row terminates add up 1, during a frame end reset, counter II be used for count field synchronization width,
Field synchronization crop, field synchronization back porch, effective field resolution ratio.
2. the method for video synchronization according to claim 1, it is characterised in that in sync signal delay on the scene, at least
Storage N rows valid data are in caching BUFFER.
3. the method for video synchronization according to claim 2, it is characterised in that the write operation of the caching BUFFER and
Input video format detection is operated in input video clock zone；The output video format is calculated, field sync signal postpones, output
Video sequential occurs and video frame formats encapsulation work is in output video clock domain.
4. a kind of device of video synchronization, it is characterised in that include
Input video format detection module, for detecting row, the field time sequence parameter of incoming video signal, and by effective video picture
Prime number according to being saved in caching BUFFER, wherein the row, field time sequence parameter include that row synchronization width, row synchronization crop, row are same
Step back porch, row total time, field synchronization width, field synchronization crop, field synchronization back porch, field total time, row resolution ratio, field resolution ratio and
Pixel clock frequency；
Output video format computing module, for using the proportionate relationship of input video pixel clock and output video pixel clock
New time sequence parameter is calculated, wherein when output video line total time=output video pixel clock frequency * input video lines are total
Between/input video pixel clock frequency；Other specification keeps identical with the vision signal of input；
Field sync signal Postponement module, for the field sync signal of input video to be postponed the N row times as the field of output signal
Synchronizing signal, N >=1 and the depth by the caching BUFFER for arranging determine；
Output video timing sequencer, for producing the video clock signal of output video, including line synchronising signal, field synchronization letter
Number and data valid signal；Produce caching BUFFER simultaneously to read to enable signal, for pixel data to be read from caching BUFFER
Take out；
Video frame formats package module, for by line synchronising signal, field sync signal, data valid signal and pixel data pair
Together, the video flowing after output encapsulation；
Using counter I and counter II in input video format detection,
Wherein by counter I cumulative 1 under each input video timeticks, reset at the end of every a line, counter I is used to unite
The synchronous width of meter trip, row synchronization crop, row synchronization back porch, effective row resolution ratio；
By counter II after every row terminates add up 1, during a frame end reset, counter II be used for count field synchronization width,
Field synchronization crop, field synchronization back porch, effective field resolution ratio.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310707676.XA CN103647918B (en) | 2013-12-20 | 2013-12-20 | Video synchronization method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310707676.XA CN103647918B (en) | 2013-12-20 | 2013-12-20 | Video synchronization method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103647918A CN103647918A (en) | 2014-03-19 |
| CN103647918B true CN103647918B (en) | 2017-04-12 |
Family
ID=50253064
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310707676.XA Expired - Fee Related CN103647918B (en) | 2013-12-20 | 2013-12-20 | Video synchronization method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103647918B (en) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104469462B (en) * | 2014-12-03 | 2017-12-12 | 成都德芯数字科技股份有限公司 | A kind of digital video signal processing system and method |
| CN108616674B (en) * | 2016-12-12 | 2020-10-20 | 中国航空工业集团公司西安航空计算技术研究所 | Double-channel video signal time sequence generating circuit structure with external synchronization function |
| CN106791552A (en) * | 2016-12-23 | 2017-05-31 | 龙迅半导体（合肥）股份有限公司 | A kind of method and device of reconstructing video sequential |
| CN106934758B (en) * | 2017-03-01 | 2019-08-27 | 南京大学 | A kind of three-dimensional image video real time integrating method and system based on FPGA |
| CN106937157B (en) * | 2017-04-05 | 2020-02-14 | 上海弘矽半导体有限公司 | Device for automatically synchronizing cross-clock domain video and operation method thereof |
| CN107734386B (en) * | 2017-09-13 | 2019-12-17 | 东莞市爱协生智能科技有限公司 | MIPI (Mobile industry processor interface) protocol-based video image reduction method and system |
| CN107846587B (en) * | 2017-10-30 | 2019-07-12 | 威创集团股份有限公司 | Field synchronization checking method for width and system |
| CN111355914B (en) * | 2018-12-24 | 2021-09-21 | 珠海格力电器股份有限公司 | Video system signal generating device and method |
| CN112188137B (en) * | 2019-07-01 | 2022-07-08 | 北京华航无线电测量研究所 | Method for converting high frame frequency progressive image to standard definition PAL interlaced image based on FPGA |
| CN111327789B (en) * | 2020-03-05 | 2022-04-26 | 珠海亿智电子科技有限公司 | Display signal synchronous conversion device |
| US11763729B2 (en) | 2021-01-22 | 2023-09-19 | Boe Technology Group Co., Ltd. | Signal processing method and devices, and display apparatus |
| CN112954432B (en) * | 2021-01-28 | 2022-08-16 | 宏晶微电子科技股份有限公司 | Video data processing method, device and system and readable storage medium |
| CN113193931B (en) * | 2021-03-04 | 2022-09-20 | 中国航空工业集团公司西安航空计算技术研究所 | ARINC818 node time certainty transmission device and method |
| CN113596348B (en) * | 2021-04-29 | 2023-11-03 | 青岛信芯微电子科技股份有限公司 | Image processing method and device |
| CN113450245B (en) * | 2021-05-11 | 2024-02-06 | 中天恒星(上海)科技有限公司 | Image processing method, device, chip and equipment |
| CN114500986A (en) * | 2021-12-20 | 2022-05-13 | 北京镁伽科技有限公司 | Time sequence synchronization method and device based on FPGA and PG equipment |
| CN116030748B (en) * | 2023-03-30 | 2023-08-08 | 深圳曦华科技有限公司 | Method and device for dynamically adjusting chip clock frequency |
| CN117939225B (en) * | 2024-01-25 | 2024-07-05 | 京东方科技集团股份有限公司 | Frame rate adjusting method and related equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1960461A (en) * | 2005-10-31 | 2007-05-09 | 三星电子株式会社 | Video signal receiver including display synchronizing signal generation device and control method thereof |
| CN101404145A (en) * | 2008-04-17 | 2009-04-08 | 硅谷数模半导体（北京）有限公司 | LCD control system |
| CN101431693A (en) * | 2007-11-05 | 2009-05-13 | 深圳Tcl新技术有限公司 | Screen distribution apparatus of panel TV |
| CN102880442A (en) * | 2011-07-13 | 2013-01-16 | 瑞昱半导体股份有限公司 | First in-first out (FIFO) device and first in-first out method used for clock tree transformation |
| CN103024430A (en) * | 2012-12-07 | 2013-04-03 | 广东威创视讯科技股份有限公司 | Control display method and system for simulating red, green and blue (RGB) signal |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI287932B (en) * | 2004-12-14 | 2007-10-01 | Vxis Technology Corp | Image data synchronizer for image data scaling device |
-
2013
- 2013-12-20 CN CN201310707676.XA patent/CN103647918B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1960461A (en) * | 2005-10-31 | 2007-05-09 | 三星电子株式会社 | Video signal receiver including display synchronizing signal generation device and control method thereof |
| CN101431693A (en) * | 2007-11-05 | 2009-05-13 | 深圳Tcl新技术有限公司 | Screen distribution apparatus of panel TV |
| CN101404145A (en) * | 2008-04-17 | 2009-04-08 | 硅谷数模半导体（北京）有限公司 | LCD control system |
| CN102880442A (en) * | 2011-07-13 | 2013-01-16 | 瑞昱半导体股份有限公司 | First in-first out (FIFO) device and first in-first out method used for clock tree transformation |
| CN103024430A (en) * | 2012-12-07 | 2013-04-03 | 广东威创视讯科技股份有限公司 | Control display method and system for simulating red, green and blue (RGB) signal |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103647918A (en) | 2014-03-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103647918B (en) | Video synchronization method and device | |
| CN102905056B (en) | Method of video image processing and device | |
| CN103686314B (en) | Demultiplex device and method adopting HD (high definition) video channel to transmit SD (standard definition) videos | |
| CN106454319B (en) | Isochronous controller and related synchronization method for multisensor camera apparatus | |
| CN104917990B (en) | Video frame rate compensation is carried out by adjusting vertical blanking | |
| CN107249101A (en) | A kind of sample of high-resolution image and processing unit | |
| CN104168487B (en) | A kind of vision signal frame synchornization method and its device | |
| US20230362336A1 (en) | Method and apparatus for transmitting video signals, and display device | |
| CN110933333A (en) | Image acquisition, storage and display system based on FPGA | |
| CN102427543B (en) | Platform for processing frame synchronization 3D real-time video information and processing method thereof | |
| KR20140008415A (en) | Acquiring and displaying images in real-time | |
| CN106603953A (en) | Video display method and video display system of converting HDMI interface into MIPI interface | |
| CN107293255B (en) | Display device and its driving method | |
| TW201428675A (en) | Video generating system and related method thereof | |
| CN103248797A (en) | Video resolution enhancing method and module based on FPGA (field programmable gate array) | |
| CN103595924A (en) | Image fusion system based on Cameralink and image fusion method based on Cameralink | |
| KR20200007723A (en) | High definition analog video and control link for automotive applications | |
| CN201623760U (en) | 3G-SDI high-definition digital video frame synchronizer | |
| CN109299030B (en) | The method that cameralink based on ZYNQ turns PAL system | |
| CN108616674A (en) | Two-way video-signal timing sequence generating circuit structure with outer synchronizing function | |
| TW200832349A (en) | Apparatus and method for reducing output speed of video data | |
| JP5998579B2 (en) | Video display apparatus, method and program for multi-display system | |
| CN103581586B (en) | Apparatus and method for generating picture-in-picture (PIP) image | |
| CN105072387A (en) | Video recording method for video door bell and video door bell | |
| CN105430237A (en) | Frame missing image processing method and system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: Kezhu road high tech Industrial Development Zone, Guangzhou city of Guangdong Province, No. 233 510670 Patentee after: VTRON GROUP Co.,Ltd. Address before: 510663 No. 6, color road, hi tech Industrial Development Zone, Guangdong, Guangzhou, China Patentee before: VTRON TECHNOLOGIES Ltd. |
|
| CP03 | Change of name, title or address | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20140319 Assignee: Guangzhou Kaide Finance Leasing Co.,Ltd. Assignor: VTRON GROUP Co.,Ltd. Contract record no.: 2019990000222 Denomination of invention: Video synchronization method and device Granted publication date: 20170412 License type: Exclusive License Record date: 20190709 |
|
| EE01 | Entry into force of recordation of patent licensing contract | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Video synchronization method and device Effective date of registration: 20190807 Granted publication date: 20170412 Pledgee: Guangzhou Kaide Finance Leasing Co.,Ltd. Pledgor: VTRON GROUP Co.,Ltd. Registration number: Y2019990000036 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20200902 Granted publication date: 20170412 Pledgee: Guangzhou Kaide Finance Leasing Co.,Ltd. Pledgor: VTRON GROUP Co.,Ltd. Registration number: Y2019990000036 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170412 Termination date: 20211220 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |