CN103620772A - 具有堆叠的面朝下连接的裸片的多芯片模块 - Google Patents
具有堆叠的面朝下连接的裸片的多芯片模块 Download PDFInfo
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- CN103620772A CN103620772A CN201280030711.2A CN201280030711A CN103620772A CN 103620772 A CN103620772 A CN 103620772A CN 201280030711 A CN201280030711 A CN 201280030711A CN 103620772 A CN103620772 A CN 103620772A
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Abstract
本发明公开了一种微电子组件10,该微电子组件可包括具有第一表面21和第二表面22的基板20、覆盖在第一表面上的至少两个逻辑芯片30、以及具有正面45的存储器芯片40,其中所述正面45上具有触点44,所述存储器芯片的正面面对每个逻辑芯片的背面36。每个逻辑芯片30的信号触点34可通过基板20的导电结构62直接电连接到其他逻辑芯片30的信号触点34以用于在逻辑芯片之间传输信号。逻辑芯片30可适于同时执行进程的给定线程的一组指令。存储器芯片40的触点44可通过导电结构62直接电连接到逻辑芯片30中的至少一个的信号触点34。
Description
相关专利申请的交叉引用
本专利申请要求2011年4月22日提交的美国专利申请序列号13/092,376的权益,其公开内容据此以引用方式并入本文。
背景技术
本发明涉及堆叠的微电子组件和制备此类组件的方法,并涉及可用于此类组件中的元件。
半导体芯片通常作为单独的预封装的单元提供。标准芯片具有扁平的矩形主体,所述主体具有大的正面,该正面具有连接到芯片的内部电路的触点。每个单独的芯片通常安装在封装内,该封装继而安装在电路面板诸如印刷电路板上,并且将芯片的触点连接至电路面板的导体。在许多常规的设计中,芯片封装在电路面板上占据的面积显著大于芯片自身的面积。
如本公开中结合具有正面的扁平芯片所述,“芯片的面积”应被理解为是指正面的面积。在“倒装芯片”设计中,芯片的正面面对封装基板(即,芯片载体)的表面,并且芯片上的触点通过焊料球或其他连接元件直接结合至芯片载体的触点。继而,芯片载体可通过覆盖在芯片正面上的端子结合至电路面板。“倒装芯片”设计提供了相对紧凑的布置方式;每个芯片在电路面板上占据的面积等于或稍大于芯片正面的面积,例如,在共同转让的美国专利5,148,265、5,148,266和5,679,977的某些实施例中所公开的,所述专利的公开内容以引用方式并入本文。
某些创新安装技术提供了与常规的倒装芯片结合技术的紧凑性接近或相等的紧凑性。可在等于或稍大于芯片自身面积的电路面板区域中容纳单个芯片的封装通常称为“芯片级封装”。
除最小化微电子组件所占据的电路面板的平面面积以外,还期望制备整体高度低或垂直于电路面板平面的尺寸较小的芯片封装。此类薄型微电子封装允许将其中安装有封装的电路面板紧邻相邻结构放置,从而产生包含电路面板的产品的整体尺寸。
已提出了多种提案以在单个封装或模块中提供多个逻辑芯片和/或存储器芯片。在常规的“多芯片模块”中,所有逻辑芯片和/或存储器芯片都并排安装在单个封装基板上,该封装基板继而可被安装至电路面板。该方法只能有限地减小芯片所占据的电路面板的总面积。所述总面积仍大于模块中各单个芯片的总表面积。
还提出了以“堆叠”布置方式封装多个芯片,即,其中多个芯片彼此叠置地放置的布置方式。在堆叠布置方式中,可将若干个芯片安装在电路面板中小于芯片总面积的区域中。某些堆叠的芯片布置方式公开于例如上述美国专利5,679,977、5,148,265和美国专利5,347,159的某些实施例中,所述专利的公开内容以引用方式并入本文。也以引用方式并入本文的美国专利4,941,033公开了其中芯片彼此堆叠并通过与芯片相关联的所谓“布线膜”上的导体彼此互连的布置方式。
尽管已在多芯片封装方面取得了进展,仍需要进行改进以便最小化尺寸并改善此类封装的性能。本发明的这些属性通过构造如下文所述的微电子组件而实现。
发明内容
根据本发明的一个方面,微电子组件可包括具有第一表面和在竖直方向上远离第一表面的第二表面的互连基板、覆盖在基板的第一表面上的至少两个逻辑芯片、以及具有其上具有触点的正面的存储器芯片。互连基板上可具有导电结构。互连基板可具有在第二表面处暴露以用于与元件连接的端子。每个逻辑芯片可在其面对互连基板的第一表面的正面处具有多个信号触点。每个逻辑芯片的信号触点可通过基板的导电结构直接电连接到其他逻辑芯片的信号触点以用于在逻辑芯片之间传输信号。该信号可代表数据或指令中的至少一者。逻辑芯片可适于同时执行进程的给定线程的一组指令。每个逻辑芯片可具有与正面相对的背面。存储器芯片的正面可面对所述至少两个逻辑芯片中的每一个的背面。存储器芯片的触点可通过基板的导电结构直接电连接到所述至少两个逻辑芯片中的至少一个的信号触点。
在具体实施例中,微电子组件还可包括中间***体基板,其在垂直于竖直方向的水平方向上位于所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片之间。中间***体基板可具有至少一个在其相对的第一表面和第二表面之间延伸穿过的导电通孔。基板的导电结构可包括至少一个导电通孔。在一个实施例中,微电子组件还可包括至少一个焊料连接件,该焊料连接件在竖直方向上从存储器芯片的正面延伸并在垂直于竖直方向的水平方向上位于所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片之间。基板的导电结构可包括至少一个焊料连接件。
在示例性实施例中,微电子组件还可包括至少一个导电桩,该导电桩在竖直方向上从互连基板延伸并在垂直于竖直方向的水平方向上位于所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片之间。基板的导电结构可包括所述至少一个导电桩。每个导电桩可通过导电块电连接到在存储器芯片的正面处暴露的相应导电元件。在具体实施例中,微电子组件还可包括至少一个导电柱,该导电柱在竖直方向上从存储器芯片的正面延伸并在垂直于竖直方向的水平方向上位于所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片之间。基板的导电结构可包括所述至少一个导电柱。每个导电柱可通过导电块电连接到在第一表面处暴露的相应导电元件。
在一个实施例中,微电子组件还可包括在竖直方向上从互连基板延伸的至少一个导电桩和在竖直方向上从存储器芯片的正面延伸的至少一个导电柱。导电桩和导电柱中的每一个可在垂直于竖直方向的水平方向上位于所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片之间。基板的导电结构可包括导电桩和导电柱。每个导电桩可通过导电块电连接到相应的导电柱。在示例性实施例中,互连基板可包括沿竖直方向在第一表面上方延伸的至少一个凸起表面。所述至少一个凸起表面可在垂直于竖直方向的水平方向上位于所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片之间。基板的导电结构可包括所述至少一个凸起表面的至少一个导电触点。
在具体实施例中,所述至少一个凸起表面可包括覆盖在互连基板的第一表面上的多个堆叠电介质层。在一个实施例中,微电子组件还可包括具有基本上平坦的主表面的封装剂。封装剂可在垂直于竖直方向的水平方向上在所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片之间延伸。封装剂的主表面可与第一逻辑芯片和第二逻辑芯片中的每一个的背面基本上共平面。在示例性实施例中,封装剂可具有至少一个在主表面和与主表面相对的第二表面之间延伸穿过封装剂的导电通孔。基板的导电结构可包括至少一个导电通孔。
根据本发明的另一个方面,微电子组件可包括具有第一表面和在竖直方向上远离第一表面的第二表面的互连基板、覆盖在基板的第一表面上的至少两个逻辑芯片、以及具有正面(其上具有触点)和与正面相对的背面的存储器芯片。互连基板上可具有导电结构。互连基板可具有在第二表面处暴露以用于与元件连接的端子。逻辑芯片可具有间隔开不超过500微米的相邻平行边缘。每个逻辑芯片可在其面对互连基板的第一表面的正面处具有多个信号触点。每个逻辑芯片的信号触点可通过基板的导电结构直接电连接到其他逻辑芯片的信号触点以用于在逻辑芯片之间传输信号。该信号可代表数据或指令中的至少一者。逻辑芯片可适于同时执行进程的给定线程的一组指令。每个逻辑芯片可具有与正面相对的背面。存储器芯片的正面可面对所述至少两个逻辑芯片中的至少一个的背面。存储器芯片的触点可通过基板的导电结构直接电连接到所述至少两个逻辑芯片中的至少一个的信号触点。
在示例性实施例中,微电子组件还可包括从存储器芯片的正面延伸至互连基板的第一表面的至少一根接线键合。所述至少一根接线键合可在垂直于竖直方向的水平方向上位于所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片之间。基板的导电结构可包括所述至少一根接线键合。在一个实施例中,互连基板可具有小于10ppm/℃的有效热膨胀系数(“CTE”)。在具体实施例中,微电子组件还可包括第二基板,所述第二基板具有面向互连基板的第二表面的表面。第二基板可具有与互连基板的端子电连接的触点。第二基板可具有大于或等于10ppm/℃的有效热膨胀系数,并可在与面向互连基板的表面相对的表面上具有第二端子。
在一个实施例中,互连基板可具有小于7ppm/℃的有效热膨胀系数。在示例性实施例中,所述至少两个逻辑芯片可具有基本上相同的结构。在具体实施例中,基板的导电结构可包括在基本上平行于第一表面的方向上延伸的多条导电迹线。在一个实施例中,微电子组件还可包括至少部分地覆盖在逻辑芯片中的至少一个的背面上的散热器。在示例性实施例中,散热器可至少部分地覆盖在存储器芯片上。在具体实施例中,存储器芯片可具有在垂直于竖直方向的水平方向上的第一宽度,并且所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片可在水平方向上具有组合的第二宽度。第一宽度可小于第二宽度。
在具体实施例中,散热器可包括延伸超出其下表面的基座部分。基座部分可接触第一逻辑芯片和第二逻辑芯片中的至少一个的背面。在一个实施例中,存储器芯片可至少部分地覆盖在散热器的上表面上。在示例性实施例中,基板的导电结构可包括延伸穿过散热器中的开口的引线。在具体实施例中,微电子组件还可包括包含所述散热器在内的多个散热器。所述多个散热器中的每一个可至少部分地覆盖在逻辑芯片中的至少一个的背面上。基板的导电结构可包括在所述多个散热器的两个相邻散热器的边缘之间延伸的引线。
本发明的另外方面提供了包括根据本发明的上述方面的微电子结构、根据本发明的上述方面的复合芯片、或所述微电子结构及所述复合芯片二者与其他电子器件相结合的***。例如,该***可设置在单个外壳中,所述外壳可以是便携式外壳。根据本发明的该方面的优选实施例的***可比类似的常规***更加紧凑。
根据本发明的另一个方面,制造微电子组件的方法可包括提供互连基板,通过基板的导电结构使至少两个逻辑芯片的信号触点彼此电连接以便在逻辑芯片之间传输信号,以及通过基板的导电结构将在存储器芯片的正面处暴露的触点电连接到所述至少两个逻辑芯片中的至少一个的信号触点。互连基板可具有第一表面、在竖直方向上远离第一表面的第二表面,以及在第二表面处暴露以用于与元件连接的端子。信号可代表数据或指令中的至少一者。逻辑芯片可适于同时执行进程的给定线程的一组指令。每个逻辑芯片可具有面对互连基板的第一表面的正面。存储器芯片的正面可面对所述至少两个逻辑芯片中的每一个的背面。
在一个实施例中,该方法还可包括在垂直于竖直方向的水平方向上在所述至少两个逻辑芯片之间提供封装剂。在具体实施例中,电连接在存储器芯片正面处暴露的触点的步骤可包括:形成在封装剂的主表面与基板的第一表面之间在竖直方向上延伸穿过封装剂的开口、形成与基板的导电结构的触点接触并在开口内延伸的导电通孔、以及将存储器芯片的触点与导电通孔电连接。基板的导电结构的触点可暴露在开口内。开口可在水平方向上位于所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片之间。
在示例性实施例中,第一逻辑芯片和第二逻辑芯片每一个可都具有与其各自的正面相对的背面。提供封装剂的步骤可包括使封装剂的主表面平整化,使得所述主表面与第一逻辑芯片和第二逻辑芯片中的每一者的背面基本上共平面。在一个实施例中,所述平整化可通过对封装剂的主表面与第一逻辑芯片和第二逻辑芯片中的每一者的背面进行研磨而执行。
附图说明
图1为根据本发明的一个实施例的堆叠微电子组件的图解剖视图。
图2为图1的一部分的局部放大剖视图,示出了位于面朝上存储器芯片与互连基板之间的接线键合连接。
图3A为图1的一部分的局部放大剖视图,示出了位于面朝下存储器芯片与互连基板之间的电连接。
图3B-3E为图3A的替代实施例的局部放大剖视图。
图4为根据另一个实施例的堆叠微电子组件的图解剖视图,所述堆叠微电子组件具有位于存储器芯片与逻辑芯片之间的散热器。
图5A为图4的一部分的局部放大剖视图,示出了位于面朝下存储器芯片与互连基板之间的电连接。
图5B为图5A的替代实施例的局部放大剖视图。
图6为根据另一个实施例的堆叠微电子组件的图解剖视图,所述堆叠微电子组件具有在逻辑芯片之间延伸的平整化的封装剂。
图7A为图6的一部分的局部放大剖视图,示出了位于面朝下存储器芯片与互连基板之间的电连接。
图7B为图7A的替代实施例的局部放大剖视图。
图8为可对应于图1至7B中示出的微电子组件的俯视平面图。
图9为根据另一个实施例的具有第二基板的堆叠微电子组件的图解剖视图。
图10为根据本发明的一个实施例的***的示意图。
具体实施方式
参见图1,根据本发明的一个实施例的微电子组件10包括互连基板20、覆盖在基板20的第一表面21上的逻辑芯片30、存储器芯片40、以及覆盖在每个存储器芯片的表面上的至少一个散热器50,其中每个存储器芯片至少部分地覆盖在逻辑芯片中的至少一个的背面36上。
在图1中,平行于第一表面21的方向在本文中被称为“水平”或“横向”方向,而垂直于正面的方向在本文中被称为“向上”或“向下”方向,且在本文中还被称为“竖直”方向。在本文中提到的方向处于所提及结构的参照系中。因此,这些方向可在垂直或重力参照系中以任意取向设置。当述及一个特征设置在“一表面上方”比另一特征更大的高度处时,是指在相同垂直方向上所述一个特征与所述表面的距离大于所述另一个特征与所述表面的距离。相反,当述及一个特征设置在“一表面上方”比另一特征更小的高度处时,是指在相同垂直方向上所述一个特征与所述表面的距离小于所述另一个特征与所述表面的距离。
互连基板20在基本上垂直于第一表面的竖直方向V上可具有介于第一表面21与远离第一表面的第二表面22之间的厚度T。厚度T通常小于200μm,并且可显著更小,例如130μm、70μm或甚至更小。
互连基板20可具有从第二表面22延伸至中间表面25的***体部分24。***体部分24优选地具有小于10*10-6/℃(或ppm/℃)的热膨胀系数(“CTE”)。在具体实施例中,***体部分24可具有小于7*10-6/℃(或ppm/℃)的CTE。***体部分24优选地基本上由诸如半导体、玻璃或陶瓷的材料组成。
互连基板20可具有一个或多个能够覆盖在***体部分24的中间表面25上的电介质层60。电介质层60可从***体部分24的中间表面25延伸至互连基板20的第一表面21,使得电介质层60的暴露表面限定互连基板的第一表面。此类电介质层60可使互连基板20的导电元件彼此电绝缘且与***体部分24电绝缘。电介质层60可包括无机电介质材料或有机电介质材料或二者。在一个实例中,电介质层60可包括电沉积的共形涂层或其他电介质材料,例如可光成像的聚合材料,例如焊料掩膜材料。
在本文所述的实施例中,电介质层60可结合到***体部分24并可具有基本上小于***体部分的厚度的厚度,使得互连基板20具有的有效CTE可大致等于***体部分的CTE,即便电介质层的CTE显著高于***体部分的CTE。在一个实例中,互连基板20可具有小于10*10-6/℃(或ppm/℃)的有效CTE。在具体实例中,互连基板20可具有小于7*10-6/℃(或ppm/℃)的有效CTE。
电触点23在互连基板20的第一表面21处暴露。如本公开中所用,当述及导电元件“暴露在”某结构的表面处时,是指所述导电元件可用于与在垂直于所述表面的方向上从所述结构外部朝所述表面移动的理论点接触。因此,暴露在某结构的表面处的端子或其他导电元件可从该表面突出;可与该表面齐平;或可相对于该表面凹进并通过结构中的孔或凹陷暴露。
电端子26暴露在基板20的第二表面22处,用于与另一个元件诸如电路板互连。电端子26可通过导电块27电连接到另一个元件。
导电块27可包含具有相对低的熔融温度的易熔金属,如焊料、锡或包含多种金属在内的低共熔混合物。作为另外一种选择,导电块27可包含可润湿金属,如铜或其他贵金属或非贵金属,其熔融温度高于焊料或另一种易熔金属。此类可润湿金属可与对应的特征接合,如电路板的易熔金属特征,以将微电子组件10从外部互连至这样的电路板。在具体实施例中,导电块27可包含散布在介质中的导电材料,所述介质可以是例如导电膏,如金属填充膏、焊料填充膏或各向同性的导电粘合剂或各向异性的导电粘合剂。
多条导电迹线62可沿着各自的电介质层60的表面、沿着基板20的第一表面21、和/或在相邻的电介质层之间延伸。迹线62中的一些可电连接到触点23中的一个或多个。互连基板20的***体部分24包括在迹线62中的一者或多者与相应的电端子26之间延伸的导电通孔28。
逻辑芯片30包括第一逻辑芯片31、第二逻辑芯片32和第三逻辑芯片33。逻辑芯片30中的每一个可覆盖在互连基板20的第一表面21上。每个逻辑芯片30可在其面对互连基板20的第一表面21的正面35处具有多个导电触点34,使得每个逻辑芯片30相对于互连基板的第一表面呈面朝下取向。每个逻辑芯片30的触点34可暴露在覆盖在逻辑芯片的正面35上的电介质层(未示出)的表面处。此类电介质层中的一个或多个可被称为逻辑芯片30的“钝化层”。每个逻辑芯片30可具有与其正面35相对的背面36。
在具体实施例中,每个逻辑芯片30可以是安装至在互连基板20的第一表面21处暴露的触点23的倒装芯片。每个逻辑芯片30的触点34可通过导电块70电连接到触点23,所述导电块70例如为焊料球或上文结合导电块27所述的任何其他材料。
多个有源半导体装置(例如,晶体管、二极管等)可设置在位于正面35处和/或正面35下方的每个逻辑芯片30的有源半导体区域中。逻辑芯片30可通过迹线62彼此电连接。逻辑芯片30可具有基本上相同的结构,并且可适于用作单个处理器,例如多核处理器,和/或此类逻辑芯片可适于同时执行进程的给定线程的一组指令。如本文所用,被视为具有“基本上相同的结构”的逻辑芯片30可具有彼此相同的结构,或者此类逻辑芯片30可相对于彼此具有微小的变化。
在具体实施例中,逻辑芯片30中的每一个的触点34可以是信号触点。在此类实施例中,每个逻辑芯片30的信号触点34可通过基板的导电结构(如,多条导电迹线62、暴露在第一表面21处的电触点23等)直接电连接到其他逻辑芯片的信号触点以用于在逻辑芯片之间传输信号,所述信号代表数据或指令中的至少一者。
存储器芯片40可包括第一存储器芯片41和第二存储器芯片42。存储器芯片40中的每一个可至少部分地覆盖在逻辑芯片30中的至少一个的背面36上。每个存储器芯片40可在其正面45处具有多个导电触点44。每个存储器芯片40的触点44可布置成例如一行或两个平行的行。一行触点44可沿着正面45的边缘延伸,如在第一存储器芯片41中所示,或沿着正面45的中心延伸,如在第二存储器芯片42中所示。每个存储器芯片40可具有与其正面45相对的背面46。
第一存储器芯片41的背面46可面对第一逻辑芯片31的背面36,使得第一存储器芯片可相对于基板20的第一表面21呈面朝上取向。在图8中还可看到面朝上安装的覆盖在逻辑芯片30的背面36上的示例存储器芯片40。
第二存储器芯片42的正面45可面对第二逻辑芯片32及第三逻辑芯片33的背面36,使得第二存储器芯片相对于基板20的第一表面21可面朝下。在图8中还可看到面朝下以覆盖在两个相邻逻辑芯片30的背面36上的方式安装的示例存储器芯片40。在具体实施例中,如图8中所示,多个存储器芯片40可面朝下安装以覆盖在两个相邻逻辑芯片30的背面36上。在图8所示的一个实施例中,单个存储器芯片40'可面朝下安装以覆盖在四个相邻存储器芯片30的背面36上。
在一个实例中,第一存储器芯片41可通过在第一存储器芯片的背面46与第一逻辑芯片的背面36之间延伸的粘合剂层72附接到第一逻辑芯片31。
在具体实施例中,第二存储器芯片42可通过在第二存储器芯片的正面45与第二逻辑芯片和第三逻辑芯片的背面36之间延伸的粘合剂层72附接到第二逻辑芯片32和第三逻辑芯片33。在此类实施例中,粘合剂层72可沿着第二存储器芯片42的正面45在其横向边缘47附近延伸,使得粘合剂层不接触第二存储器芯片的触点44。
每个存储器芯片40的触点44可暴露在覆盖在存储器芯片的正面45上的电介质层(未示出)的表面处。此类电介质层中的一个或多个可被称为存储器芯片40的“钝化层”。每个存储器芯片40可通过多条导电迹线62电连接到逻辑芯片30中的至少一个。
存储器芯片40中的每一个可包括记忆存储组元件。如本文所用,“记忆存储元件”是指布置成阵列的大量存储单元,其与可用于存储并从中检索数据的电路一起例如用于通过电接口传输数据。
在一些实施例中,多条导电迹线62、暴露在互连基板20的第一表面21处的电触点23、导电块70、以及覆盖在互连基板20的第一表面21上或在互连基板内延伸的其他导电元件可被视为互连基板的导电结构。在此类实施例中,逻辑芯片30可通过基板的导电结构直接彼此电连接,并且存储器芯片40中的至少一个可通过基板的导电结构直接电连接到逻辑芯片30中的至少一个。
散热器50可例如由任何导热材料制成,包括金属,诸如钛、钨、铜或金。散热器50可在互连基板20的第一表面21的整个区域上散热,这可获得与没有此类散热器的微电子组件相比改善的热性能。散热器50可覆盖在互连基板20的第一表面21的大部分上。在本文所述的任何实施例中,可存在多个散热器50,所述多个散热器50可一起用于将热量分散在互连基板20的第一表面21的至少一部分的整个区域上。
散热器50可至少部分地覆盖在逻辑芯片30中至少一个的背面36上。散热器50可至少部分地覆盖在第一存储器芯片41的正面45和第二存储器芯片42的背面46上。如图1所示,散热器50可直接接触第一存储器芯片41的正面45和第二存储器芯片42的背面46。散热器50的下表面51可具有间隙或凹槽53,使得散热器不直接接触面朝上的第一存储器芯片41的触点44。
散热器50可覆盖在存储器芯片40和逻辑芯片30上,并且可与存储器芯片40和逻辑芯片30热量互通,或者直接地或者间接地与附加的导热材料诸如焊料、导热粘合剂、或设置在两者之间的导热油脂热连通。在散热器50与一个存储器芯片40(例如,第二存储器芯片42)和两个逻辑芯片30(例如,第二逻辑芯片32和第三逻辑芯片33)接触的示例实施例中,存储器芯片可在基本上平行于基板20的第一表面21的水平方向H上具有第一宽度W1,并且逻辑芯片可在水平方向上具有组合的第二宽度W2,所述第一宽度小于所述第二宽度。在这样的实施例中,具有小于宽度W2的宽度W1可使两个逻辑芯片30中的一者或两者的背面36的一些部分延伸超过存储器芯片40的横向边缘47,使得热量可从逻辑芯片的背面直接传输至延伸超过下表面51从而接触逻辑芯片的散热器50的一个或多个基座部分56,或者使得热量可通过设置在逻辑芯片的背面和散热器50的下表面51之间的导热粘合剂57而从逻辑芯片的背面间接地传输至散热器50的下表面51。在图8中还可看到在具有宽度W1的存储器芯片40与具有组合宽度W2的两个相邻逻辑芯片30之间的这种关系。
图2示出了图1所示的第一存储器芯片41的触点44与暴露在互连基板20的第一表面21处的触点23之间的电连接的进一步详情。触点44中的一些或全部可通过在触点44和触点23之间延伸的各自接线键合63电连接到触点23。此类接线键合63可在水平方向H上位于第一逻辑芯片31和第二逻辑芯片32的横向边缘37之间。第一存储器芯片41可通过接线键合63中的至少一根连接到所述多条导电迹线62。在存储器芯片41具有电连接到基板20的触点23的触点44(通过在触点23与触点44之间延伸的各自的接线键合63)的示例性实施例中,接线键合可在具有间隔开不超过500微米的相邻平行边缘37的相邻逻辑芯片31和32之间延伸。
在图8中还可看到在相邻逻辑芯片30的横向边缘37之间从存储器芯片40的一行触点44延伸至互连基板20的第一表面21的接线键合63的示例性实施例。在图8所示的具体实施例中,在多个存储器芯片40与互连基板20的第一表面21之间延伸的接线键合63可在两个相邻逻辑芯片30的横向边缘37之间延伸。
图3A示出了图1所示的第二存储器芯片42的触点44与暴露在互连基板20的第一表面21处的触点23之间的电连接的进一步详情。触点44中的一些或全部可通过在触点44和触点23之间延伸的各自导电柱64电连接到触点23。此类导电柱64可在水平方向H上位于第二逻辑芯片32和第三逻辑芯片33的横向边缘37之间。第二存储器芯片42可通过导电柱64中的至少一个连接到所述多条导电迹线62。
导电柱64(和本文所述的其他导电柱中的任何一个)可具有任何形状,包括截头圆锥形(如图3A所示)或圆柱形。在导电柱64具有截头圆锥形形状的实施例中,柱64的横截面直径可在触点44与触点23之间的任一方向上逐渐减小。
图3B示出了图1所示的第二存储器芯片42的触点44与暴露在互连基板20的第一表面21处的触点23之间的电连接的替代实施例。如图3B所示,图1的导电柱64中的一些或全部可被替换为延伸穿过至少一个中间***体基板80的相应导电通孔83和相应导电块74。
中间***体基板80可在竖直方向V上具有面对第二存储器芯片42的正面45的第一表面81以及与其相对的第二表面82,并且可在水平方向H上位于第二逻辑芯片32和第三逻辑芯片33的相对的横向边缘37之间。基板80可具有小于10*10-6/℃(或ppm/℃)的热膨胀系数(“CTE”)。基板80在竖直方向V上在第一表面81和第二表面82之间的厚度可与第二逻辑芯片32和第三逻辑芯片33的厚度基本上相同,该厚度为T'。
基板80可具有在第一表面81和第二表面82之间延伸的至少一个导电通孔83。每个通孔83可电连接到暴露在第一表面81处的相应触点84和暴露在第二表面82处的相应触点85。每个触点84可通过导电块75与第二存储器芯片42的相应触点44连接。每个触点85可通过导电块74与暴露在互连基板20的第一表面21处的相应触点23连接。导电块74和75可以是焊料球或上文结合导电块27所述的任何其他材料。
触点44与触点23中的一些或全部之间的电连接可包括导电通孔83中的相应部分。第二存储器芯片42可通过导电通孔83中的至少一个连接到所述多条导电迹线62。
图3C示出了图1所示的第二存储器芯片42的触点44与暴露在互连基板20的第一表面21处的触点23之间的电连接的另一个替代实施例。如图3C所示,图1的导电柱64中的一些或全部可被替换为相应的细长导电块76。细长导电块76可以是细长焊料连接件或上文结合导电块27所述的任何其他材料。
图3D示出了图1所示的第二存储器芯片42的触点44与暴露在互连基板20的第一表面21处的触点23之间的电连接的另一个替代实施例。如图3D所示,图1的导电柱64中的一些或全部可被替换为相应的导电柱86和导电桩87。导电柱86和导电桩87通常为实心金属凸块或突起,其通常基本上由铜、铜合金、镍、金、或它们的组合组成。在一个实例中,柱86、桩87、或柱和桩两者可通过镀覆到可移除的层(例如光致抗蚀剂掩膜)中的开口内而形成。在另一个实例中,柱86、桩87、或柱和桩两者可通过蚀刻覆盖在互连基板20的第一表面21和/或第二存储器芯片42的正面45上的一个或多个金属层来形成。
导电柱86中的每一个可在竖直方向V上从暴露在第二存储器芯片42的正面45处的相应导电触点44延伸,并且可在水平方向H上位于第二逻辑芯片32和第三逻辑芯片33的相对的横向边缘37之间。导电桩87中的每一个可在竖直方向V上从相应导电触点23(其从互连基板20的第一表面21延伸)延伸,并且可在水平方向H上位于第二逻辑芯片32和第三逻辑芯片33的相对的横向边缘37之间。
导电柱86和导电桩87中对应的一些可通过各自的导电块77彼此电连接。导电块77可以是细长焊料连接件或上文结合导电块27所述的任何其他材料。第二存储器芯片42可通过至少一个导电柱86和导电桩87连接到所述多条导电迹线62。
导电柱86和导电桩87可具有任何形状,包括截头圆锥形或圆柱形(如图3D所示)。在一些情况下,导电柱86可以和其所连接的导电桩87基本上相同。在导电柱86和导电桩87具有截头圆锥形形状的实施例中,柱和/或桩的横截面直径可在触点44与触点23之间的任一方向上逐渐减小。
在一个实施例中,第二存储器芯片42的触点44中的一些或全部可通过导电柱86和导电块(但不包括导电桩87)电连接到暴露在主表面61处的对应触点23。在这样的实施例中,每个导电柱86可通过导电块与对应的触点23直接连接。
在另一个实施例中,第二存储器芯片42的触点44中的一些或全部可通过导电桩87和导电块(但不包括导电柱86)电连接到暴露在互连基板20的第一表面21处的对应触点23。在这样的实施例中,每个导电桩87可通过导电块与第二存储器芯片42的对应触点44直接连接。
图3E示出了图1所示的第二存储器芯片42的触点44与暴露在互连基板20的第一表面21处的触点23之间的电连接的另一个替代实施例。如图3E所示,图1的导电柱64中的一些或全部可被替换为相应导电柱88和互连基板20的至少一个凸起表面66。
每个凸起表面66可以是在互连基板20的第一表面21上方在竖直方向V上延伸的互连基板20的相应凸起部分29的朝上表面。每个凸起表面66可在水平方向H上位于第二逻辑芯片32和第三逻辑芯片33的相对的横向边缘37之间。如图3E所示,每个凸起部分29可包括***体部分24的凸起段24',并且电介质层60可沉积覆盖在***体部分和其凸起段上。
每个凸起表面66可具有在该处暴露的至少一个导电触点23,该触点与多条导电迹线62电连接。第二存储器芯片42可通过至少一个凸起表面66的至少一个导电触点23电连接到所述多条迹线62。
导电柱88中的每一个可在竖直方向V上从暴露在第二存储器芯片42的正面45处的相应导电触点44延伸,并可在水平方向H上位于第二逻辑芯片32和第三逻辑芯片33的相对的横向边缘37之间。每个导电柱88可通过导电块78与凸起表面66的相应触点23连接。导电块78可以是焊料球或上文结合导电块27所述的任何其他材料。
在每个凸起部分29包括***体部分24的凸起段24'的实施例中,可通过将掩膜层例如光致抗蚀剂层施加到***体部分24的初始表面上需要形成凸起段的位置处来形成凸起段,然后可在未被掩膜层保护的位置中对***体部分进行蚀刻,使得受保护的凸起段在中间表面25上方延伸。随后,可移除掩膜层,并将电介质层60沉积覆盖在***体部分24和其凸起段24'上。
在具体实施例(未示出)中,每个凸起部分29可由电介质材料制成,例如上文结合电介质层60所述的任何材料。在该实施例中,每个凸起部分29可包括覆盖在互连基板20的第一表面21上的多个堆叠电介质层。在一个实例中,每个凸起部分29可使用电介质增层法形成。
现在参见图4,根据本发明实施例的微电子组件110包括互连基板120、覆盖在基板120的第一表面121上的逻辑芯片130、存储器芯片140、以及覆盖在每个逻辑芯片的背面上的散热器150,其中每个存储器芯片至少部分地覆盖在逻辑芯片中的至少一个的背面136上。一个或多个电介质层160可覆盖在基板120的第一表面121上。
具有***体部分124的互连基板120和覆盖在其中间表面125上的一个或多个电介质层160与上文结合图1所述的互连基板20、***体部分24和电介质层60相同。
逻辑芯片130与上文结合图1所述的逻辑芯片30相同,不同的是第一逻辑芯片131位于图4的右侧,而第二逻辑芯片132和第三逻辑芯片133位于图4的左侧。
散热器150与上文结合图1所述的散热器50相同,不同的是所述散热器覆盖在逻辑芯片130上并位于存储器芯片140之下。如图4所示,散热器150可直接接触逻辑芯片130的背面136。在具体实施例中,可将热粘合剂(未示出)设置在散热器150的下表面151与逻辑芯片130的背面136之间。在一个实例中,散热器150可至少部分地覆盖在逻辑芯片130中的至少一个的背面136上。
存储器芯片140与上文结合图1所述的存储器芯片40相同,不同的是第一存储器芯片141位于图4的右侧,而第二存储器芯片142位于图4的左侧。
存储器芯片140中的每一个可至少部分地覆盖在逻辑芯片130中的至少一个的背面136和散热器150的上表面152上。第一存储器芯片141的背面146可面对散热器150的上表面152,使得第一存储器芯片可相对于基板120的第一表面121呈面朝上取向。第二存储器芯片142的正面145可面对散热器150的上表面152,使得第二存储器芯片可相对于基板120的第一表面121呈面朝下取向。
在一个实例中,第一存储器芯片141可通过在第一存储器芯片的背面146与散热器的上表面152之间延伸的粘合剂层172附接到散热器150。在具体实施例中,第二存储器芯片142可通过在第二存储器芯片的正面145与散热器的上表面152之间延伸的粘合剂层172附接到散热器150。在这样的实施例中,粘合剂层172可沿着第二存储器芯片142的正面145在其横向边缘147附近延伸,使得粘合剂层不接触第二存储器芯片的触点144。
与图1的微电子组件10类似,第一存储器芯片141的触点144中的一些或全部可通过在触点144和触点123之间延伸的各自接线键合163电连接到触点123。这样的接线键合163可在水平方向H上位于第一逻辑芯片131和第二逻辑芯片132的横向边缘137之间,并且这样的接线键合可延伸穿过开口153,其中开口153延伸穿过散热器150的上表面152与下表面151之间。第一存储器芯片141可通过接线键合163中的至少一根连接到所述多条导电迹线162。在一个实施例(未示出)中,接线键合163可在两个相邻的散热器150的横向边缘之间延伸,而不是延伸穿过单个散热器中的开口153。
图5A示出了图4所示的第二存储器芯片142的触点144与暴露在互连基板120的第一表面121处的触点123之间的电连接的进一步详情。与图1的微电子组件10类似,触点144中的一些或全部可通过在触点144和触点123之间延伸的各自导电柱164电连接到触点123。此类导电柱164可在水平方向H上位于第二逻辑芯片132和第三逻辑芯片133的横向边缘137之间,并且这样的导电柱可延伸穿过开口154,其中开口154延伸穿过散热器150的上表面152与下表面151之间。第二存储器芯片142可通过导电柱164中的至少一个连接到所述多条导电迹线162。在一个实施例(未示出)中,导电柱164可在两个相邻散热器150的横向边缘之间延伸,而不是延伸穿过单个散热器中的开口154。
在具体实施例(未示出)中,导电柱164中的一些或全部可与相应开口154的内表面155的轮廓相符,使得每个导电柱和其相应的开口可被视为贯穿的散热器导电通孔。在具有延伸穿过散热器150的开口的导电通孔的此类实施例中,电介质层可在导电通孔与开口的内表面之间延伸,以用于将导电通孔与散热器分离和绝缘。在一个实例中,散热器可具有从其相对的上表面和下表面之间延伸穿过的至少一个贯穿的散热器导电通孔,使得至少一个存储器芯片140可通过导电通孔电连接到所述多条迹线162。
在一些实施例中,延伸穿过散热器150中的开口153的接线键合163或延伸穿过散热器中的开口154的导电柱164可被视为延伸穿过散热器中的开口的引线,并且基板120的导电结构可被视为包括此类引线。如本文所用,“引线”是在两个导电元件之间延伸的电连接的一部分或全部,诸如包括接线键合163的引线,其中接线键合163从第一存储器芯片141的触点144之一延伸穿过散热器150中的开口153,然后到达暴露在互连基板120的第一表面121处的导电触点123之一。
图5B示出了图4所示的第二存储器芯片142的触点144与暴露在互连基板120的第一表面121处的触点123之间的电连接的替代实施例。如图5B所示,图4的导电柱164中的一些或全部可被替换为相应的导电柱186和导电块177。
与结合图3D所述的导电柱86类似,导电柱186中的每一个可在竖直方向V上从暴露在第二存储器芯片142的正面145处的相应导电触点144延伸,并可在水平方向H上位于第二逻辑芯片132和第三逻辑芯片133的相对的横向边缘137之间。
此类导电柱186还可延伸穿过开口154,其中开口154延伸穿过散热器150的上表面152与下表面151之间。第二存储器芯片142可通过导电柱186中的至少一个连接到所述多条导电迹线162。
每个导电柱186可通过导电块177与各自的触点123连接。导电块177可是焊料球或上文结合导电块27所述的任何其他材料。
与上文结合图5A所述的导电柱164类似,在具体实施例(未示出)中,导电柱186中的一些或全部可与相应开口154的内表面155的轮廓相符,使得每个导电柱和其相应的开口可被视为贯穿的吸热部件导电通孔。在具有延伸穿过散热器150的开口的导电柱164的此类实施例中,电介质层可在导电柱与开口的内表面之间延伸,以用于将导电柱与散热器分离和绝缘。
现在参见图6,根据本发明实施例的微电子组件210与上文结合图1所述的微电子组件10相同,不同的是微电子组件210包括覆盖在互连基板20的第一表面21上的平整化封装剂290,并且组件210包括在存储器芯片40的触点44与暴露在第一表面21处的触点23之间的替代电连接。尽管图6中未示出散热器,但散热器(诸如图1中所示的散热器50)可包括在微电子组件210中,并覆盖在逻辑芯片30和/或存储器芯片40上。
平整化的封装剂290可在水平方向H上在逻辑芯片30之间延伸,使得平整化封装剂基本上包围逻辑芯片的横向边缘37。平整化的封装剂290可具有与逻辑芯片30中的每一个的背面36一起平整化的主表面291。
平整化的封装剂290可包括至少一个从主表面291和与其相对的第二表面292之间延伸穿过的导电通孔264。此类导电通孔264可在水平方向H上位于相邻的逻辑芯片30的横向边缘37之间。存储器芯片40中的至少一个可通过所述至少一个导电通孔264电连接到所述多条迹线62。
在具体实施例中,导电通孔264中的至少一个可通过将导电金属沉积在延伸穿过平整化的封装剂290的开口254内来形成。可通过将金属镀覆到开口254的内表面255上来进行导电金属的沉积,从而形成导电通孔264。导电通孔264可以是实心的,或者导电通孔可包括可被电介质材料填充的内部空隙。在另一个实例中,可以例如通过丝网印刷、镂花涂装或点胶方法将导电烧结材料沉积到封装剂290的开口内,随后固化烧结材料以便在开口内形成无空隙的导电基体,从而形成导电通孔。在另一个实例中,可使用丝网印刷、镂花涂装或点胶方法将导电膏诸如焊膏或银填充膏等沉积到开口内。
在另一个实例中,导电通孔264可在将逻辑芯片30或存储器芯片40附接到互连基板20之前形成。在此种实施例中,可将金属层沉积到覆盖在电介质层60上的互连基板20的第一表面21上。可将掩膜层诸如光致抗蚀剂层施加到金属层上需要形成导电通孔264的位置。然后,可将未被掩膜层保护的位置中的金属层蚀刻掉,从而留下从第一表面21延伸的导电通孔264。随后,可移除掩膜层,并且可施加封装剂290,使封装剂290在导电通孔264的横向表面与逻辑芯片30的横向边缘37周围延伸。
如图6所示,第一存储器芯片41的触点44中的一些或全部可通过在触点44和导电通孔264之间延伸的相应接线键合263电连接到导电通孔264,使得第一存储器芯片可通过接线键合和导电通孔连接到所述多条导电迹线62。每根接线键合263可从触点44延伸至相应导电通孔264的上表面265。每个上表面265可暴露在平整化的封装剂290的主表面291处。
图7A示出了图6中所示的第二存储器芯片42的触点44与暴露在互连基板20的第一表面21处的触点23之间的电连接的进一步详情。如图7A所示,每个导电通孔264可在触点23与暴露在平整化的封装剂290的主表面291处的导电焊盘266之间延伸。导电块275可在每个导电焊盘266与第二存储器芯片42的对应触点44之间延伸。
图7B示出了图6和7A中所示的在第二存储器芯片42的触点44与暴露在互连基板20的第一表面21处的触点23之间延伸的导电通孔264的替代实施例。如图7B所示,在触点23与暴露在平整化的封装剂290的主表面291处的导电焊盘266之间延伸的导电通孔264'可具有圆柱形形状,而不是图7A所示的导电通孔264的截头圆锥形形状。
图8为可对应于图1至7B中示出的微电子组件的俯视平面图。如图8所示,微电子组件310可包括多个覆盖在互连基板20的第一表面21上的逻辑芯片30和覆盖在逻辑芯片的背面36上的存储器芯片40。每个存储器芯片40可相对于存储器芯片平放在其上的逻辑芯片30具有任何纵向取向。优选的是,每个存储器芯片40至少部分地覆盖在至少一个逻辑芯片30的背面36上。
现在参见图9,根据本发明实施例的微电子结构400可包括微电子组件410和第二基板401,其中微电子组件410可以是上文所述的微电子组件10、110、210或310中的任何一种。在一个实例中,第二基板401可具有大于或等于10ppm/℃的有效CTE。
在具体实施例中,第二基板401可以是其中另外包含微电子组件410的封装的基板。在示例性实施例中,第二基板401可以是电路面板,诸如母板。在一个实施例中,第二基板401可以是模块基板,其可进一步连接到电路面板或另一个元件。
第二基板401可具有第一表面402和与第一表面相对的第二表面403。第二基板401的第一表面402可面向互连基板420的第二表面422。第二基板401可具有暴露在第一表面402处的导电触点404和暴露在第二表面403处的电端子405,以用于与另一个元件诸如电路板连接。在具体实施例中,电端子405可位于与面向互连基板420的第一表面402相对的第二表面403上。
每个导电触点404可通过导电块427与互连基板420的各自电端子426电连接。电端子405可通过导电块406电连接到另一个元件。导电块406和427可以是焊料球或上文结合导电块27所述的任何其他材料。
上文所述的微电子组件可用于构建各式各样的电子***,如图10所示。例如,根据本发明的另一个实施例的***500包括与其他电子元件508和510相结合的上述微电子组件506。微电子组件506可以是上文所述的微电子组件10、110、210或310中的任何一种,或者微电子组件506可以是上文所述的微电子结构400。在所述的实例中,元件508为半导体芯片,而元件510为显示屏,但可使用任何其他元件。当然,尽管为了清楚起见,图10中只示出了两个附加元件,但***可包括任何数量的此类元件。微电子组件506可以是上文所述的组件中的任何一种。在另一种变型形式中,可使用任何数量的此类微电子组件。
微电子组件506以及元件508和510安装在用虚线示意性描绘的共同外壳501中,并且在必要时彼此电互连以形成所需的电路。在示出的示例性***中,该***包括电路面板502,诸如电路板或柔性印刷电路板,并且电路面板包括许多使元件彼此互连的导体504,图10仅示出了其中的一个。然而,这仅是示例性的;可使用任何适于进行电连接的结构。
外壳501被示出为可用于例如移动电话或个人数字助理的便携式外壳,并且屏幕510暴露在外壳的表面处。如果结构506包括光敏组件诸如成像芯片,则还可提供用于将光路由至该结构的透镜511或其他光学装置。此外,图10中所示的简化***也仅是示例性的;可使用上文所述的结构制成其他***,包括通常被视为固定结构的***,例如台式计算机、路由器等。
本文所公开的开口和导电元件可通过例如以下专利申请中更详细公开的那些方法形成:2010年7月23日提交的共同未决且共同转让的美国专利申请12/842,587、12/842,612、12/842,651、12/842,669、12/842,692和12/842,717,以及已公布的美国专利申请公开2008/0246136,所述专利申请的公开内容以引用方式并入本文。
虽然本文已参照具体的实施例描述了本发明,但应当理解,这些实施例仅仅是举例说明本发明的原理和应用。因此,应当理解,可对所述示例性实施例进行许多修改,并且可在不脱离如所附权利要求所定义的本发明的实质和范围的情况下设想出其他布置方式。
应当理解,本文示出的多个从属权利要求和特征可使用与初始权利要求中所呈现的方式不同的方式相组合。还应当理解,结合各个实施例所述的特征可与所述实施例中的其他实施例共享。
工业适用性
本发明享有广泛的工业适用性,包括但不限于微电子组件和制造微电子组件的方法。
Claims (31)
1.一种微电子组件,包括:
互连基板,所述互连基板具有第一表面、在竖直方向上远离所述第一表面的第二表面、所述互连基板上的导电结构、以及暴露在所述第二表面处用于与元件连接的端子;
覆盖在所述基板的所述第一表面上的至少两个逻辑芯片,每个逻辑芯片在其面对所述互连基板的所述第一表面的正面处具有多个信号触点,每个逻辑芯片的所述信号触点通过所述基板的所述导电结构直接电连接到其他逻辑芯片的信号触点以用于在所述逻辑芯片之间传输信号,所述信号代表数据或指令中的至少一者,所述逻辑芯片适于同时执行进程的给定线程的一组指令,并且每个逻辑芯片具有与所述正面相对的背面;以及
存储器芯片,所述存储器芯片具有其上具有触点的正面,所述存储器芯片的所述正面面对所述至少两个逻辑芯片中的每一个的所述背面,所述存储器芯片的所述触点通过所述基板的所述导电结构直接电连接到所述至少两个逻辑芯片中的至少一个的所述信号触点。
2.根据权利要求1所述的微电子组件,还包括在垂直于竖直方向的水平方向上位于所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片之间的中间***体基板,所述中间***体基板具有在其相对的第一表面和第二表面之间延伸穿过所述中间***体基板的至少一个导电通孔,其中所述基板的所述导电结构包括所述至少一个导电通孔。
3.根据权利要求1所述的微电子组件,还包括至少一个焊料连接件,所述焊料连接件在竖直方向上从所述存储器芯片的所述正面延伸,并在垂直于竖直方向的水平方向上位于所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片之间,其中所述基板的所述导电结构包括所述至少一个焊料连接件。
4.根据权利要求1所述的微电子组件,还包括至少一个导电桩,所述至少一个导电桩在竖直方向上从所述互连基板延伸,并在垂直于竖直方向的水平方向上位于所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片之间,其中所述基板的所述导电结构包括所述至少一个导电桩,每个导电桩通过导电块电连接到暴露在所述存储器芯片的所述正面处的各自的导电元件。
5.根据权利要求1所述的微电子组件,还包括至少一个导电柱,所述至少一个导电柱在竖直方向上从所述存储器芯片的所述正面延伸,并在垂直于竖直方向的水平方向上位于所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片之间,其中所述基板的所述导电结构包括所述至少一个导电柱,每个导电柱通过导电块电连接到暴露在所述第一表面处的各自的导电元件。
6.根据权利要求1所述的微电子组件,还包括在竖直方向上从所述互连基板延伸的至少一个导电桩和在竖直方向上从所述存储器芯片的所述正面延伸的至少一个导电柱,所述导电桩和导电柱中的每一个在垂直于竖直方向的水平方向上位于所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片之间,其中所述基板的导电结构包括所述导电桩和导电柱,每个导电桩通过导电块电连接到各自的导电柱。
7.根据权利要求1所述的微电子组件,其中所述互连基板包括在竖直方向上在所述第一表面上方延伸的至少一个凸起表面,所述至少一个凸起表面在垂直于竖直方向的水平方向上位于所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片之间,其中所述基板的所述导电结构包括所述至少一个凸起表面的至少一个导电触点。
8.根据权利要求7所述的微电子组件,其中所述至少一个凸起表面包括覆盖在所述互连基板的所述第一表面上的多个堆叠电介质层。
9.根据权利要求1所述的微电子组件,还包括具有基本上平坦的主表面的封装剂,所述封装剂在垂直于竖直方向的水平方向上在所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片之间延伸,其中所述封装剂的所述主表面与所述第一逻辑芯片和第二逻辑芯片中的每一个的背面基本上共平面。
10.根据权利要求9所述的微电子组件,其中所述封装剂具有在所述主表面和与所述主表面相对的第二表面之间延伸穿过所述封装剂的至少一个导电通孔,并且所述基板的所述导电结构包括所述至少一个导电通孔。
11.一种微电子组件,包括:
互连基板,所述互连基板具有第一表面、在竖直方向上远离所述第一表面的第二表面、所述互连基板上的导电结构、以及暴露在所述第二表面处用于与元件连接的端子;
覆盖在所述基板的所述第一表面上的至少两个逻辑芯片,所述逻辑芯片具有间隔开不超过500微米的相邻平行边缘,每个逻辑芯片在其面对所述互连基板的所述第一表面的正面处具有多个信号触点,每个逻辑芯片的所述信号触点通过所述基板的所述导电结构直接电连接到其他逻辑芯片的信号触点以用于在所述逻辑芯片之间传输信号,所述信号代表数据或指令中的至少一者,所述逻辑芯片适于同时执行进程的给定线程的一组指令,并且每个逻辑芯片具有与所述正面相对的背面;以及
存储器芯片,所述存储器芯片具有其上具有触点的正面和与所述正面相对的背面,所述存储器芯片的所述正面面对所述至少两个逻辑芯片中的至少一个的所述背面,所述存储器芯片的所述触点通过所述基板的所述导电结构直接电连接到所述至少两个逻辑芯片中的至少一个的所述信号触点。
12.根据权利要求11所述的微电子组件,还包括从所述存储器芯片的所述正面延伸至所述互连基板的所述第一表面的至少一根接线键合,所述至少一根接线键合在垂直于竖直方向的水平方向上位于所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片之间,其中所述基板的所述导电结构包括所述至少一根接线键合。
13.根据权利要求1或权利要求11所述的微电子组件,其中所述互连基板具有小于10ppm/℃的有效热膨胀系数。
14.根据权利要求13所述的微电子组件,还包括第二基板,所述第二基板具有面向所述互连基板的所述第二表面的表面,所述第二基板具有与所述互连基板的所述端子电连接的触点,所述第二基板具有大于或等于10ppm/℃的有效热膨胀系数,并且在与面向所述互连基板的所述表面相对的表面上具有第二端子。
15.根据权利要求1或权利要求11所述的微电子组件,其中所述互连基板具有小于7ppm/℃的有效热膨胀系数。
16.根据权利要求1或权利要求11所述的微电子组件,其中所述至少两个逻辑芯片具有基本上相同的结构。
17.根据权利要求1或权利要求11所述的微电子组件,其中所述基板的所述导电结构包括在基本上平行于所述第一表面的方向上延伸的多条导电迹线。
18.根据权利要求1或权利要求11所述的微电子组件,还包括散热器,所述散热器至少部分地覆盖在所述逻辑芯片中的至少一个的背面上。
19.根据权利要求18所述的微电子组件,其中所述散热器至少部分地覆盖在所述存储器芯片上。
20.根据权利要求19所述的微电子组件,其中所述存储器芯片在垂直于竖直方向的水平方向上具有第一宽度,并且所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片在水平方向上具有组合的第二宽度,所述第一宽度小于所述第二宽度。
21.根据权利要求20所述的微电子组件,其中所述散热器包括延伸超出其下表面的基座部分,所述基座部分接触所述第一逻辑芯片和第二逻辑芯片中的至少一个的所述背面。
22.根据权利要求18所述的微电子组件,其中所述存储器芯片至少部分地覆盖在所述散热器的上表面上。
23.根据权利要求22所述的微电子组件,其中所述基板的所述导电结构包括延伸穿过所述散热器中的开口的引线。
24.根据权利要求22所述的微电子组件,还包括包含所述散热器在内的多个散热器,所述多个散热器中的每一个至少部分地覆盖在所述逻辑芯片中的至少一个的背面上,其中所述基板的所述导电结构包括在所述多个散热器中的相邻两个散热器的边缘之间延伸的引线。
25.一种包括根据权利要求1或权利要求11所述的结构以及电连接到所述结构的一个或多个其他电子元件的***。
26.根据权利要求25所述的***,还包括外壳,所述结构和所述其他电子元件被安装至所述外壳。
27.一种制造微电子组件的方法,包括:
提供互连基板,所述互连基板具有第一表面、在竖直方向上远离所述第一表面的第二表面、所述互连基板上的导电结构、以及暴露在所述第二表面处用于与元件连接的端子;
通过所述基板的所述导电结构将至少两个逻辑芯片的信号触点彼此电连接以用于在所述逻辑芯片之间传输信号,所述信号代表数据或指令中的至少一者,所述逻辑芯片适于同时执行进程的给定线程的一组指令,每个逻辑芯片具有面对所述互连基板的所述第一表面的正面;以及
通过所述基板的所述导电结构将暴露在存储器芯片的正面处的触点电连接到所述至少两个逻辑芯片中的至少一个的所述信号触点,所述存储器芯片的所述正面面对所述至少两个逻辑芯片中每一个的所述背面。
28.根据权利要求27所述的方法,还包括在垂直于竖直方向的水平方向上在所述至少两个逻辑芯片之间提供封装剂。
29.根据权利要求28所述的方法,其中电连接暴露在所述存储器芯片的所述正面处的所述触点的步骤包括:形成开口,所述开口在竖直方向上在所述封装剂的主表面和所述基板的第一表面之间延伸穿过所述封装剂,使得所述基板的所述导电结构的触点暴露在所述开口内,所述开口在水平方向上位于所述至少两个逻辑芯片的第一逻辑芯片和第二逻辑芯片之间;以及形成导电通孔,所述导电通孔与所述基板的所述导电结构的触点接触并在所述开口内延伸;以及将所述存储器芯片的所述触点与所述导电通孔电连接。
30.根据权利要求29所述的方法,其中所述第一逻辑芯片和第二逻辑芯片每一个都具有与其各自的正面相对的背面,并且提供所述封装剂的步骤包括使所述封装剂的主表面平整化,使得所述主表面与所述第一逻辑芯片和第二逻辑芯片中的每一个的所述背面基本上共平面。
31.根据权利要求30所述的方法,其中通过研磨所述封装剂的所述主表面与所述第一逻辑芯片和第二逻辑芯片中的每一个的背面来执行所述平整化。
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KR20140041496A (ko) | 2014-04-04 |
TW201248830A (en) | 2012-12-01 |
TWI545722B (zh) | 2016-08-11 |
US8956916B2 (en) | 2015-02-17 |
US20140357021A1 (en) | 2014-12-04 |
EP2700099A1 (en) | 2014-02-26 |
US20150236002A1 (en) | 2015-08-20 |
US20120267777A1 (en) | 2012-10-25 |
WO2012145370A1 (en) | 2012-10-26 |
US9484333B2 (en) | 2016-11-01 |
US8841765B2 (en) | 2014-09-23 |
JP2014512691A (ja) | 2014-05-22 |
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