CN103616814B - A kind of synchronized sampling closed-loop corrected method and system of clock based on FPGA - Google Patents

Abstract

The invention discloses a kind of synchronized sampling closed-loop corrected method and system of clock based on FPGA.The method, initially with judging PPS pulse signal pulse duration and adjacent pulse triggering cycle respectively, detects the correctness of its pulse signal；Then real-time reception detect the actuating signal that PPS judge module sends, to make corresponding reaction；Then pass through error correction module the frequency of local crystal oscillator clock is corrected and according to the state of actuating signal, the phase error synchronizing the heavily number of accepting and believing is measured and corrected；Generate finally by frequency multiplication computing module and synchronize the heavily number of accepting and believing, output signal is fed back to error correction module simultaneously and defines a closed-loop system, and according to control information control information, output is adjusted automatically.This method solving on the basis of research is based on GPS sampling data synchronization, combining unit synchronized sampling clock is strong to crystal oscillator dependence, so that in the case of, frequency accuracy aging at crystal oscillator reduces, the problem that output error is bigger.

Description

A kind of synchronized sampling closed-loop corrected method and system of clock based on FPGA

Technical field

The invention belongs to electrical technology field, be specifically related to a kind of synchronized sampling closed-loop corrected side of clock based on FPGA Method.

Background technology

Intelligent substation is standardized as basic demand with information digitalization of entirely standing, communications platform networking, information sharing, real Existing information gathering, measure, control, protect, monitor and the function such as metering, and domain information real-time synchronization acquisition technique of standing is to realize intelligence The basis of the various application function of energy transformer station, it requires that electronic mutual inductor reaches every to the data sampling of power network current and voltage Number of seconds thousand times, once sampled can by multiple intelligent substations in each intelligent electronic device (IED) share.But no matter control, Protection, or the calculating of monitoring, metering processes and is desirable that sampled data should gather at the same time, in order to avoid phase place and width Value produces error.

Overcurrent protection etc. is protected, because the short-term stability of merging unit of electronic transformer this locality crystal oscillator clock The highest, the operation precision of protection will not be impacted.But for differential protection and metering, due to combining unit this locality crystal oscillator Clock is not very accurate, through long error accumulation, can cause across compartment difference combining unit phase error and The gradually expansion of amplitude error, causes the misoperation of differential protection and the gross error of metering.

Therefore, invent that a kind of performance is the most superior, that range of application synchronized sampling clock the most widely is closed-loop corrected is new Method becomes the problem needing solution badly.

Summary of the invention

For the problems referred to above, the present invention proposes setting of synchronized sampling clock in a kind of merging unit of electronic transformer Meter, is devoted to solve combining unit synchronized sampling clock strong to crystal oscillator dependence, aging at crystal oscillator, the feelings that frequency accuracy reduces Under condition, the deficiency that output error is bigger.

For reaching above-mentioned purpose, the technical scheme that the present invention takes is:

In a kind of merging unit of electronic transformer, the design of synchronized sampling clock, comprises the steps:

1) by PPS judge module, PPS pulse signal pulse duration and adjacent pulse triggering cycle are carried out respectively Judge, detect the correctness of its pulse signal；

2) pass through error handling module real-time reception and detect the actuating signal that PPS judge module sends, corresponding to make Reaction；

3) by error correction module the frequency of local crystal oscillator clock is corrected and according to the state pair of actuating signal The frequency error and the phase error that synchronize the heavily number of accepting and believing measure and correct；

4) generated the synchronization heavily number of accepting and believing of 80 points/cycle by frequency multiplication computing module, output signal is fed back to by mistake simultaneously Difference correction module defines a closed-loop system, sends the control information come according to error correction module and automatically adjusts output Whole.

Step one uses PPS judge module PPS pulse signal pulse duration and adjacent pulse are triggered the cycle to divide Not judging, detecting the correctness of pulse signal, i.e. after combining unit system starts, FPGA begins to constantly circulate reading Take PPS pulse signal input pin signal, until detect that pulse signal rising edge triggers two counters after arriving and opens simultaneously Begin counting, is detected PPS pulse signal by local clock source.Then the judgement carrying out two counter values judges The validity of pulse signal.

Step 3 use cumulative method measure 4000 interval T synchronizing heavily to adopt pulse signal_c, and calculate mould by frequency multiplication Block ensures T_c=T_pEven if to avoid in the case of Crystal Oscillator Errors is maximized, its two subsynchronous heavy number of accepting and believing interval error is also Only 0.25Hz, is difficult to the problem detected.

Step 4 be have employed a kind of frequency-doubling method realized by accumulator, FPGA can define bit wide W Reg register type accumulator Baund_acc and accumulated value variable Baund_inc.Accumulator Baund_acc capacity 2^wRepresent same Step heavily adopts the digital quantization value of signal period, and accumulated value Baund_inc represents the digital quantization value in crystal oscillator cycle.So that

F_cry/F_res=2^w/Baund_inc

ConsiderF_res=4000Hz, can try to achieve

$\mathrm{Baund}\_\mathrm{inc}=4000\·2^w/\stackrel{\‾}{M}$

When each crystal oscillator cycle arrives, accumulator Baund_acc can add Baund_inc, carries out one-accumulate meter Calculate, then the highest order output of accumulator is the synchronization heavily number of accepting and believing that dutycycle is 50%.The method is for realizing synchronizing the heavily number of accepting and believing Zero moment output error correction need the maximum duration to be

t_s=F_cry/(500·F_res)=25s

After PPS pulse signal accesses, add that the PPS of 3s judges the time, at most need 28s, i.e. can be completely achieved and heavily adopt The synchronism output of signal.The method overcomes when local oscillator frequency deviation is bigger, and the error synchronizing the heavily number of accepting and believing is relatively big, no Can realize synchronizing the output at equal intervals of the heavily number of accepting and believing, the accuracy class of crystal oscillator is required higher, and be unfavorable for synchronizing heavily to accept and believe Number the problem that is corrected of zero moment output error.

Relative to prior art, beneficial effects of the present invention mainly has: the method, while improving output accuracy, reduces The crystal oscillation frequency error impact on synchronized sampling clock, has saved production cost, it is ensured that synchronized sampling clock long-term steady Fixed operation.The realization of synchronised clock during the method also apply be applicable to other IED equipment simultaneously, realizes information for intelligent substation real Time synchronous acquisition lay a good foundation.

Accompanying drawing explanation

The FB(flow block) of Fig. 1 present invention；

Fig. 2 PPS pulse input waveform figure；

Fig. 3 PPS pulse detection flow chart；

Fig. 4 error correction schematic diagram；

Fig. 5 frequency multiplication computing module operational flow diagram；

Fig. 6 synchronized sampling clocked sequential analogous diagram；

Fig. 7 (a) experimental error angular difference test figure；

Fig. 7 (b) experimental error ratio test figure.

Detailed description of the invention

Below in conjunction with drawings and Examples, the invention will be further described.

As it is shown in figure 1, the design of synchronized sampling clock in a kind of merging unit of electronic transformer, comprise the steps:

1) PPS judges.PPS pulse signal trigger characteristic is as in figure 2 it is shown, trigger when light intensity rises reach amplitude 50% Moment arrives, its pulse duration t_h> 10 μ s, interpulse period t_I> 500ms, adjacent pulse triggers cycle T_p=1s.Therefore Can judge respectively by its pulse duration and adjacent pulse being triggered the cycle, just detecting PPS pulse signal Really property, PPS judge module overhaul flow chart is as shown in Figure 3.

After combining unit system starts, FPGA begins to constantly circulate reading PPS pulse signal input pin signal, directly To detecting that pulse signal rising edge triggers two counters after arriving and starts counting up, by local clock source to PPS arteries and veins simultaneously Rush signal to detect.Select herein precision be the common quartz crystal oscillator of 50MHz of 20ppm as local clock source, then crystal oscillator is real Border vps is 5 × 10⁷Between ± 1000.Start counter 1, to basis in PPS pulse signal high level lasting time Ground crystal oscillator vibration number carries out accumulation calculating, when count value N of trailing edge arrival hour counter 1₁It is latched, then performs judgement 1, it is judged that N₁Whether more than 500, i.e. t_h>10μs.If but N₁It count down to 25 × 10⁶Also at counting, i.e. t_h> 500ms, then it is automatically stopped Counting, performs to judge that 1 makes mistakes.Start counter 2, to crystal oscillator vibration time local in the PPS pulse signal adjacent pulse triggering cycle Number carries out accumulation calculating, count value N of counter 2 after the arrival of next pulse signal rising edge being detected₂It is latched, then Perform judgement 2, it is judged that N₂Whether more than 4.9999 × 10⁷, i.e. T_p≈1s.If but N2 count down to 5.0001 × 10⁷Also at counting, I.e. T_p> 1s, then it is automatically stopped counting, performs to judge that 2 make mistakes.When judge 1 or judge 2 make mistakes time, then automatically into error handling processing All for PPS judge module registers are reset by program, return to wait the original state of PPS pulse signal rising edge.If judging 1 Enter judgement 3 with judging 2 can meet then simultaneously, need then to think that PPS pulse signal is effective through continuous three correct judgments, defeated Going out synchronous mark signal syn=1, the most no matter whether the value of counter 1 sum counter 2 is reset by correct judgment.

2) error handle.Error handling module real-time reception also detects the syn signal that PPS judge module sends, if its value Being 0, be then sent out synchronous abnormality bright light alarm signal, synchronized sampling clock carries out asynchronous punctual output, until PPS pulse is believed Number again correct access and within continuous three seconds, judge that effectively syn signal value is 1, resets error handling module.

3) error correction.Error correction schematic diagram is as shown in Figure 4.IEC61850-9-2LE standard-required combining unit is sampled Rate is 80 points/cycle or 256 points/cycle (50Hz), herein as a example by 80 commonly used points/cycle, i.e. requires to synchronize heavily to adopt Signal output speed is fixed as 4000 points/second.Owing to the time interval between the adjacent sync heavily number of accepting and believing is the shortest, even if therefore existing In the case of Crystal Oscillator Errors is maximized, its two subsynchronous heavy number of accepting and believing interval error also only has 0.25Hz, is difficult to detect.So Accumulative can be used, measure 4000 interval T synchronizing heavily to adopt pulse signal_c, and ensure T by frequency multiplication computing module_c=T_p。 When error correction module detects that syn signal value is 1, after judging that in PPS judge module 2 conditions meet, in counter 2 First three time count value N₂Carry out mean value computation and obtain mean valueAnd the actual vibration frequency as crystal oscillator is sent to again Frequently computing module is corrected processing.When error correction module detects that syn signal value is 0, then calculate before losing synchronization Go outValue is sent to frequency multiplication computing module, enters asynchronous punctual state.

When PPS pulse signal arrives, and rising edge triggers, error correction module starts timing.Define after this simultaneously Or first synchronization heavily number of accepting and believing of times frequency module output this moment is No. 0, after when No. 0, heavily the number of accepting and believing arrives, error correction module is stopped Only timing, measures the time difference t between PPS pulse signal and No. 0 synchronization heavily number of accepting and believing₀, i.e. t₀Crystal oscillator vibration number in time K, and K is sent to frequency multiplication computing module be modified process, ensure that the output synchronizing the heavily number of accepting and believing is without phase deviation with this. When error correction module detects that syn signal value is 0, then K value is reset, enter asynchronous punctual state.

4) frequency multiplication calculates.Frequency multiplication computing module operational flow diagram is as shown in Figure 5.

Owing in FPGA, reg register type variable can freely define bit wide, the reg that therefore can define bit wide W posts Storage type accumulator Baund_acc and accumulated value variable Baund_inc.Accumulator Baund_acc capacity 2^wRepresent and synchronize heavily to adopt The digital quantization value of signal period, accumulated value Baund_inc represents the digital quantization value in crystal oscillator cycle.Therefore have

F_cry/F_res=2^w/ Baund_inc (3)

ConsiderF_res=4000Hz, can try to achieve

$\mathrm{Baund}\_\mathrm{inc}=4000\·2^w/\stackrel{\‾}{M}---\left(4\right)$

When frequency multiplication computing module receives the crystal oscillator frequency corrected value that error correction module sendsAfter, formula (4) can be passed through Round downwards and calculate accumulated value Baund_inc.Because accumulator Baund_acc is unsigned int, therefore can be ignored it Overflow, constantly do cycle accumulor.When each crystal oscillator cycle arrives, accumulator Baund_acc can add Baund_inc, enters Row one-accumulate calculates, then the highest order output of accumulator is the synchronization heavily number of accepting and believing that dutycycle is 50%.

Because Baund_inc rounds downwards when calculating, in causing a period of time, accumulator count value is less than normal, can be right Synchronize count value is modified by zero moment output error correction of the heavily number of accepting and believing.When frequency multiplication computing module receives error school During zero moment output error value K that positive module sends, now the highest order of accumulator Baund_acc has just completed by 0 to 1 turn Become, generate No. 0 heavily number of accepting and believing.Baund_inc is multiplied by K and obtains t_oDigital quantization value Baund_err.Due to Baund_err The time value of the number of accepting and believing of attaching most importance to lag output, therefore can be by entering accumulator count value Baund_acc plus Baund_err Line delay compensates.In view of synchronize heavily the number of accepting and believing adjustment need realize a smooth transition, for prevent adjacent two heavily the number of accepting and believing it Between interval too small, cause program run-time error, need Baund_err is any limitation as, when K more than 500 time, Baund_err is 500·Baund_inc.The zero moment output error correction then realizing synchronizing the heavily number of accepting and believing needs the maximum duration to be

t_s=F_cry/(500·F_res)=25s (5)

After PPS pulse signal accesses, add that the PPS of 3s judges the time, at most need 28s, i.e. can be completely achieved and heavily adopt The synchronism output of signal.

Embodiment:

The error analysis of synchronized sampling clock:

Due to floor operation when Baund_inc calculates in this synchronized sampling clock, the heavily number of accepting and believing place can be synchronized n-th Generation error:

${\mathrm{\ξ}}_2=|\frac{n}{F_{\mathrm{res}}}-\frac{n\·2^W}{\mathrm{Baund}\_\mathrm{inc}}\·\frac{1}{F_{\mathrm{cry}}}|---\left(6\right)$

During owing to synchronizing, the error correction of the counterweight number of accepting and believing per second once, so taking maximum 4000 and Baund_ as n Inc round-off error is 1 to the maximum, i.e. n=4000,Time, ξ₂The maximum is had to be

${\mathrm{\ξ}}_{2\max }=\frac{\stackrel{\‾}{M}}{4000\·2^W-\stackrel{\‾}{M}}---\left(7\right)$

It is different from formula (2) the synchronization heavily number of accepting and believing output error ξ of tradition frequency-doubling method₁Only affected by crystal oscillator precision, From formula (7), output worst error ξ is heavily accepted and believed in the synchronization realized by context of methods_2maxSimultaneously by crystal oscillator precision with cumulative The impact of device bit wide W.Therefore can be the highest in crystal oscillator precision, crystal oscillator actual vibration frequencyTime bigger, strengthen bit wide W, subtract Little ξ_2max.Exist for research furtherTake maximum 5.0001 × 10⁷Time, the different values of bit wide W are to ξ_2maxAffect situation, Baund_inc calculated value and round-off error percentage δ thereof are observed, as shown in table 1 simultaneously.

Table 1 bit wide W different value impact (M=5.0001 × 10 on error amount⁷)

W	Baund_inc	δ(%)	ξ2max(μs)
				32	343590	1.48977×10-4	2.91045
40	87959171	4.39513×10-8	1.1369×10-2
				41	175918342	4.39513×10-8	5.6845×10-3
48	2.25175×1010	3.98250×10-9	4.4410×10-5
				64	1.47571×1015	1.34631×10-14	6.7764×10-10

During by table 1 it can be seen that bit wide W is the biggest, calculated value corresponding for Baund_inc is the biggest, and it is ignored when calculating The round-off error percentage δ that fractional part produces is also the least, therefore corresponds to the ξ that round-off error causes_2maxThe least.

The experimental study of synchronized sampling clock:

Utilizing Quartus II that synchronized sampling clock is programmed emulation, as shown in Figure 6, wherein clk is its time stimulatiom Local crystal oscillator clock input, PPS_clk is the input of PPS pulse signal, and resample_clk is for synchronizing the heavily number of accepting and believing output, syn It is internal register variable with K.When PPS judge module detects that PPS pulse signal is effective, synchronous regime syn becomes 1, generation Table synchronizes.Error correction module is heavily adopted pulse signal to No. 0 and is corrected subsequently, obtains its output error value K, uses simultaneously Timebar instrument records the heavily number of accepting and believing lag output PPS pulse signal 17.12 μ s.Owing to K is 856, more than 500, so Only compensate for 500 during single compensation, after next PPS pulse signal arrives, re-calibrate the output heavily adopting pulse signal Error is 356, and is compensated.Finally synchronizing the heavily number of accepting and believing and PPS pulse signal and carve triggering at the same time, its output phase place is by mistake Difference K is 0.

This synchronized sampling clock is downloaded in electronic current mutual inductor combining unit, uses Jiangsu to insult wound NT702 electricity Minor mutual inductor steady state check system has carried out testing results.Crystal oscillator is the common quartz crystal oscillator of 20ppm, and specified measurement electric current is 5A, the synchronously sampled data error of the combining unit under different current strength is as shown in Figure 7.Can be seen that synchronously sampled data Ratio be distributed more uniform concentration, when electric current is less, owing to the burr of white noise disturbs, angular difference fluctuation is relatively big, but totally On can meet the required precision of IEEE60044 standard 0.2S level, reflect good synchronism.

Those skilled in the art the present invention can be carried out various change and modification without deviating from the present invention spirit and Scope.So, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, Then the present invention is also intended to comprise these change and modification.

Claims (6)

1. the synchronized sampling closed-loop corrected method of clock based on FPGA, it is characterised in that: comprise the steps:

1) PPS judges step, and the cycle of triggering PPS pulse signal pulse duration and adjacent pulse judges respectively, comes Detect the correctness of its pulse signal；

2) error handling steps, real-time reception also detects the actuating signal that PPS judge module sends, to make corresponding reaction；

3) error correction step, is corrected the frequency of local crystal oscillator clock and heavily adopts synchronization according to the state of actuating signal The frequency error of signal and phase error measure and correct；

Specific as follows: to use cumulative method to measure multiple synchronizations and heavily adopt the interval T of pulse signal_c, and ensured by frequency multiplication calculation procedure T_c=T_p, T_pThe cycle is triggered for adjacent pulse；Crystal oscillator vibration number local in the PPS pulse signal adjacent pulse triggering cycle is entered The counter of row accumulation calculating is counter 2, and the count value of counter 2 is N₂；Thus PPS judges that step judges N₂It is more than 4.9999×10⁷After, try to achieve first three in counter 2 time count value N₂Carry out mean value computation and obtain mean valueIn the hope of frequency Error；PPS pulse signal arrives, and when rising edge triggers, error correction step starts timing, and after this or this moment frequency multiplication calculates After first synchronization heavily number of accepting and believing of step output arrives, error correction step stops timing, measures PPS pulse signal and the Time difference t between one synchronization heavily number of accepting and believing₀, obtain t₀In time, crystal oscillator vibration number K is to obtain phase error, by frequency Error and phase error carry out error correction；

4) frequency multiplication calculation procedure, generates the synchronization heavily number of accepting and believing of 80 points/cycle, and output signal feeds back to error correction step simultaneously Suddenly form closed loop, according to the frequency error in error correction step and phase error, output is adjusted automatically.

The closed-loop corrected method of synchronized sampling clock the most according to claim 1, it is characterised in that: PPS judges to adopt in step With PPS judge module, PPS pulse signal pulse duration and adjacent pulse triggering cycle are judged respectively, detect arteries and veins Rushing the correctness of signal, i.e. after combining unit system starts, FPGA begins to constantly circulate reading PPS pulse signal input and draws Pin signal, until detecting that pulse signal rising edge arrives, triggering two counters the most simultaneously and starting counting up, passing through local clock PPS pulse signal is detected by source, is then judged the validity of pulse signal by the numerical value of two counters.

The closed-loop corrected method of synchronized sampling clock the most according to claim 1, it is characterised in that: logical in frequency multiplication calculation procedure Cross accumulator and realize frequency multiplication, FPGA can define the reg register type accumulator Baund_acc of bit wide W with cumulative Value variable Baund_inc, accumulator Baund_acc capacity 2^wRepresent the digital quantization value synchronizing heavily to adopt the signal period, accumulated value Baund_inc represents the digital quantization value in crystal oscillator cycle, then

F_cry/F_res=2^w/Baund_inc

When each crystal oscillator cycle arrives, accumulator Baund_acc can add Baund_inc, carries out one-accumulate calculating, then The highest order output of accumulator is the synchronization heavily number of accepting and believing that dutycycle is 50%.

4. a synchronized sampling clock closed loop correction system based on FPGA, it is characterised in that: include such as lower module:

1) PPS judge module, sentences respectively for PPS pulse signal pulse duration and adjacent pulse are triggered the cycle Disconnected, detect the correctness of its pulse signal；

2) error handling module, for real-time reception and detect the actuating signal that PPS judge module sends, corresponding anti-to make Should；

3) error correction module, for being corrected the frequency of local crystal oscillator clock and according to the state of actuating signal to synchronization Heavily frequency error and the phase error of the number of accepting and believing measures and corrects；

Use cumulative method to measure multiple synchronizations and heavily adopt the interval T of pulse signal_c, and ensure T by frequency multiplication computing module_c=T_p, T_p The cycle is triggered for adjacent pulse；Crystal oscillator vibration number local in the PPS pulse signal adjacent pulse triggering cycle is carried out cumulative meter The counter calculated is counter 2, and the count value of counter 2 is N₂；Thus PPS judgesMouldBlock judges N₂More than 4.9999 × 10⁷ After, try to achieve first three in counter 2 time count value N₂Carry out mean value computation and obtain mean valueIn the hope of frequency error；PPS arteries and veins Rushing signal to arrive, when rising edge triggers, error correction module starts timing, after this or this moment frequency multiplication computing module output First synchronizes error correction module stopping timing after the heavily number of accepting and believing arrival, measures PPS pulse signal and first synchronization weight Time difference t between the number of accepting and believing₀, obtain t₀In time, crystal oscillator vibration number K is to obtain phase error, by frequency error and phase place Error carries out error correction；

4) frequency multiplication computing module, for generating the synchronization heavily number of accepting and believing of 80 points/cycle, feeds back to error school simultaneously by output signal Positive module forms closed-loop system, and output is adjusted by frequency error and phase error automatically that send according to error correction module Whole.

Synchronized sampling clock closed loop correction system the most according to claim 4, it is characterised in that: PPS judge module, it is used for Use PPS judge module that PPS pulse signal pulse duration and adjacent pulse triggering cycle are judged respectively, detect The correctness of pulse signal, i.e. after combining unit system starts, FPGA begins to constantly circulate reading PPS pulse signal input Leg signal, until detecting that pulse signal rising edge arrives, triggering two counters the most simultaneously and starting counting up, during by this locality PPS pulse signal is detected by Zhong Yuan, is then judged the validity of pulse signal by the numerical value of two counters.

Synchronized sampling clock closed loop correction system the most according to claim 4, it is characterised in that: frequency multiplication computing module, use In realizing frequency multiplication by accumulator, can define in FPGA the reg register type accumulator Baund_acc of bit wide W with Accumulated value variable Baund_inc, accumulator Baund_acc capacity 2^wRepresent the digital quantization value synchronizing heavily to adopt the signal period, tired Value added Baund_inc represents the digital quantization value in crystal oscillator cycle, then

F_cry/F_res=2^w/Baund_inc

When each crystal oscillator cycle arrives, accumulator Baund_acc can add Baund_inc, carries out one-accumulate calculating, then The highest order output of accumulator is the synchronization heavily number of accepting and believing that dutycycle is 50%.