CN109765583B - Clock synchronization method based on GNSS receiver second pulse - Google Patents
Clock synchronization method based on GNSS receiver second pulse Download PDFInfo
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Abstract
The invention discloses a clock synchronization method based on GNSS receiver second pulse, which inputs the GNSS receiver second pulse 1PPS signal into a pre-processing circuit for eliminating jitter and restraining to generate a 1PPS anti-jitter signal to prevent a plurality of second pulses from appearing within 1 second; counting 1PPS anti-shake signals by using a first counter, wherein the result is the actual frequency value of a system clock signal, inputting the result into a fixed-point divider, and obtaining the accumulation step length of a second counter through formula operation; generating a sampling working clock by dividing a system clock signal through a second counter, wherein the number of bits of the second counter is kept unchanged, and the frequency of the sampling working clock signal is changed by changing the magnitude of the accumulation step delta of the second counter; carrying out phase compensation on the sampling working clock, and forcibly pulling up the sampling working clock when each 1PPS anti-shake signal arrives to align the sampling working clock with the 1PPS anti-shake signal; and performing time delay compensation on the sampling working clock. The invention well solves the problem that the calculation result of the real-time system is not synchronous with the actual system due to the accumulated error of the low-frequency sampling working clock.
Description
Technical Field
The invention relates to the field of clock synchronization of microelectronic integrated circuits, in particular to a clock synchronization method based on second pulse of a GNSS receiver.
Background
A main working sampling clock in the design of the integrated circuit is input through an external clock crystal oscillator and then is generated through frequency multiplication or frequency division of a special clock management module such as a PLL (phase locked loop) or MMCM (multimedia messaging service) in the FPGA, and when the required working clock frequency is lower than 1MHz, special clock management resources in the FPGA cannot meet the requirement. In certain applications where high precision low frequency clocks are particularly desirable, typical clock divider circuits are not capable of providing high quality and high reliability clocks without cumulative errors. The invention provides a clock synchronization method based on GNSS receiver second pulse, which solves the problem that the calculation result of a real-time system is not synchronous with the actual result caused by the accumulated error of a low-frequency sampling working clock.
Disclosure of Invention
In order to overcome the defects of the existing clock frequency division circuit, the invention provides a clock synchronization method based on second pulse of a GNSS receiver, which comprises the following steps:
inputting a GNSS receiver second pulse 1PPS signal into a jitter elimination and constraint preprocessing circuit to generate a 1PPS anti-jitter signal, and preventing a plurality of second pulses from occurring within 1 second;
counting 1PPS anti-shake signals by using a first counter, wherein the result is the actual frequency value of a system clock signal, inputting the result into a fixed-point divider, and obtaining the accumulation step length of a second counter through formula operation;
generating a sampling working clock by dividing a system clock signal through a second counter, wherein the number of bits of the second counter is kept unchanged, and the frequency of the sampling working clock signal is changed by changing the magnitude of the accumulation step delta of the second counter;
carrying out phase compensation on the sampling working clock, and forcibly pulling up the sampling working clock when each 1PPS anti-shake signal arrives to align the sampling working clock with the 1PPS anti-shake signal;
and performing time delay compensation on the sampling working clock.
Optionally, the jitter elimination and constraint preprocessing circuit continuously samples the 1PPS second pulse signal by using a sampling operation clock signal, and sends each sampling result to the shift register, and if the continuous sampling results are all 1, the real signal is considered to be 1, otherwise, the real signal is 0.
Optionally, the formula is:
delta＝2n*fc/fswhere n is the number of bits of the counter, fcFor sampling the operating clock frequency, fsIs the actual frequency value of the system clock signal.
Alternatively, the fixed point divider is 64-bit word long, and is 40-bit fixed point, i.e. the decimal part has 40 bits, the integer part has 24 bits, and the way of converting the decimal into binary is by 2.
Optionally, the delay compensation method includes the following steps:
recording 1PPS until the divider completes calculation, wherein the accumulation frequency is n;
defining an accumulation step difference Δ ═ delta (k) -delta (k-1);
after the divider has completed the calculation, n · Δ is calculated and n · Δ is added to the second counter.
Compared with the prior art, the clock synchronization method has the advantages that the clock precision of the sampling working clock output by the frequency division clock circuit is improved, the long-term accumulated error and the stability of the output sampling working clock are improved, the output sampling working clock is strictly and accurately synchronized with the second pulse output of the GNSS receiver, the calculation error caused by long-time drift of the output sampling working clock is effectively avoided, and the clock synchronization method is suitable for system application with strict real-time synchronization requirements on the long-endurance high-precision low-frequency acquisition clock.
Drawings
FIG. 1 is a flowchart illustrating a clock synchronization method based on GNSS receiver second pulse according to the present invention.
Detailed Description
The invention is further illustrated with reference to figure 1.
The principle of the 1PPS second pulse jitter elimination and constraint preprocessing circuit is that a clock signal is utilized to continuously sample an input 1PPS second pulse signal for n times, each sampling result is sent to a shift register, if the n sampling results are all 1, a real signal is considered to be 1, and otherwise, the real signal is 0. Under the normal condition, the GNSS receiver outputs 1PPS second pulse signal every 1 second, the precision of the 1PPS signal is +/-20 ns, and in order to prevent the receiver from having faults, the 1PPS signal appears for many times in 1 second, and the constraint preprocessing circuit module is used for monitoring the 1PPS signal. The detection method comprises the following steps: counting is started at the next hop edge of a certain second pulse, the current system clock is counted, if a new second pulse occurs before the counting value reaches (99% of the system clock frequency), the abnormal second pulse is not sent to the system, and new counting is started by the next hop edge of the abnormal second pulse, and the method is adopted to prevent the generation of the system sampling clock from being influenced by a plurality of second pulses within 1 second.
The local sampling operation clock generation and measurement circuit is mainly realized based on an adder circuit and a fixed point divider circuit. The sampling operation clock is generated by using a local system operation generation and measurement circuit module. Assuming that the system clock is 100MHz, the basic principle of generating the required sampling operation clock is as follows: under the drive of a system clock, the second counter starts counting from an initial value of zero, each clock period is incremented by 1, accumulation is not enough in the initial stage, therefore, the first bit of the counter is 0, the first bit of the counter is continuously accumulated to be set to 1, and the counter is cleared after overflow due to accumulation because the bit number of the counter is limited, and the previous accumulation process is circulated, so that the first bit of the counter outputs a period of square waves, namely, sampling working clock signals required by people.
The design idea of the local sampling working clock generation and measurement circuit is that the number of bits of the counter is kept unchanged, and the frequency of the sampling working clock signal is changed by changing the magnitude of the accumulation step delta, so that the design idea is more flexible. Suppose that the sampling clock frequency is 4KHz, which is 0.00004 times the 4K/100M clock period, i.e. the period of the sampling clock signal should be 25000 times the clock period, i.e. the entire counter is full after 25000 accumulations, and the size of the counter in the program is 48 bits, so the size of each accumulation step delta is:
the 48-bit counter is div200_ counter, which increments delta at each rising edge of the system clock to achieve the above-described adder-based frequency division, delta being the result of the fixed-point divider circuit output (quotient [ 47: 0 ]).
The actual frequency of the system clock is different from its nominal frequency, and an accurate system clock frequency is required to obtain an accurate 4KHz clock. The 1PPS signal is a pulse signal generated by a receiver based on satellite time service, and the signal is generated 1 time per second, so that the signal is called a "one pulse per second (1 PPS) signal, and the frequency of a local system clock is measured by taking the pulse per second (one pulse per second) signal as a time reference, namely, the number of the system clocks between two times of 1PPS is recorded by using a first counter, so that a local clock measurement value is obtained. After obtaining the local clock, according to the calculation formula
delta-2n*fc/fs(wherein n is the number of bits of the counter, the frequency of the sampling working clock and the actual frequency value of the system clock signal) sending the local clock to the fixed-point divider for calculation.
The system clock and the generated sampling working clock are not necessarily in integral multiple relation, the integral multiple relation is small, but the system clock and the generated sampling working clock are accumulated according to integral multiple, the digit of the fixed-point divider is limited, and the calculated quotient has truncation errors. Because of these two errors, phase compensation is required. In order to force the generated sampling clock to align with 1PPS, the generated sampling clock is forced to be pulled high every 1PPS arrives, so that the initial value of the second counter div200_ counter is 0x 800000000000, and the output clock is 1 (high level). However, due to the existence of the two errors, after 1 second accumulation, div200_ counter is smaller than 0x 800000000000, that is, there is a phase difference, so it is necessary to eliminate the phase error accumulated in the last 1 second at the new 1 second period, that is, when 1PPS arrives, how much the difference between the current accumulation counter values 0x 800000000000 is calculated, which is the phase error, and the phase error is compensated at the beginning of the new accumulation period. By the sampling working clock phase compensation circuit, the accumulated error can be ensured not to exceed 1 second, and the generation precision of the generated working clock can not be influenced as long as the accumulated error does not exceed 1 accumulation step length.
When 1PPS arrives, the local clock measured this time is used for recalculating the accumulated step delta, but because the divider needs time for calculation, the delta calculated in the last 1 second is actually used in the period from 1PPS to the time when the divider completes the calculation; after the divider is calculated, new delta is used for accumulation, and in order to compensate the influence caused by the time delay of the divider, the solution idea of the sampling working clock time delay compensation circuit is as follows:
recording 1PPS until the divider completes the calculation, wherein the accumulation frequency is n；
Defining an accumulation step difference Δ ═ delta (k) -delta (k-1);
after the divider finishes the calculation, calculating n & delta, and adding n & delta to the accumulation register;
the specific method for realizing the compensation comprises the following steps:
using the register div _ cnt, under the control of the enable signal div _ cnt _ en, the number of times that the second counter accumulates until the divider completes the counting of 1PPS is counted to obtain n. After the divider finishes the calculation, the calculation result is subtracted from the last calculation result to obtain delta, and the size is compared firstly during the calculation, so that the difference between the large value and the small value is ensured to be always used, and the negative number condition is avoided. After the delta is calculated, the delta calculated this time is latched for the next difference. A multiplier is constructed using the Xilinx IP core, multiplying n by Δ to obtain a compensation amount n Δ, and compensating into a second counter.
Claims (4)
1. A clock synchronization method based on GNSS receiver pulse per second is characterized by comprising the following steps:
inputting a GNSS receiver second pulse 1PPS signal into a jitter elimination and constraint preprocessing circuit to generate a 1PPS anti-jitter signal, and preventing a plurality of second pulses from occurring within 1 second;
counting 1PPS anti-shake signals by using a first counter, wherein the result is the actual frequency value of a system clock signal, inputting the result into a fixed-point divider, and obtaining the accumulation step length of a second counter through formula operation;
generating a sampling working clock by dividing a system clock signal through a second counter, wherein the number of bits of the second counter is kept unchanged, and the frequency of the sampling working clock signal is changed by changing the magnitude of the accumulation step delta of the second counter;
carrying out phase compensation on the sampling working clock, and forcibly pulling up the sampling working clock when each 1PPS anti-shake signal arrives to align the sampling working clock with the 1PPS anti-shake signal;
performing time delay compensation on the sampling working clock, recording 1PPS arrival to a fixed point divider to complete calculation, wherein the accumulation frequency is n; defining an accumulation step difference Δ ═ delta (k) -delta (k-1); after the fixed point divider completes the calculation, n & delta is calculated, and n & delta is added to the second counter, wherein delta is the accumulation step length.
2. The method of claim 1, wherein the dejitter and constraint pre-processing circuit samples the 1 PPS-sec signal sequentially using a sampling clock signal, and feeds each sampling result to the shift register, wherein if the sequential sampling results are all 1, the true signal is considered to be 1, and otherwise the true signal is 0.
3. The method of claim 2, wherein the formula is:
delta＝2n*fc/fswhere n is the number of bits of the counter, fcFor sampling the operating clock frequency, fsIs the actual frequency value of the system clock signal.
4. The method of claim 3, wherein the fixed point divider is 64-bit word long, and the fixed point divider is 40-bit fixed point, i.e., the fractional part has 40 bits, the integer part has 24 bits, and the decimal conversion is a multiplication-by-2 integer.
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| CN111208539B (en) * | 2019-12-18 | 2023-06-23 | 中国航空工业集团公司成都飞机设计研究所 | High-precision GNSS simulator time synchronization method |
| CN111641490B (en) * | 2020-05-20 | 2021-07-09 | 中国人民解放军国防科技大学 | High-precision phase calibration and time reference determination method for sampling clock |
| CN112951134B (en) * | 2021-04-20 | 2022-09-20 | 合肥京东方显示技术有限公司 | Clock recovery device, source electrode driving circuit, display panel and equipment |
| CN117716644A (en) * | 2021-07-27 | 2024-03-15 | 华为技术有限公司 | Clock synchronization method, device, system and chip |
| CN114363125A (en) * | 2021-12-07 | 2022-04-15 | 上海华虹集成电路有限责任公司 | Method for generating sampling pulse in digital asynchronous communication system |
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