CN103560797A - Method and device for five times of iterative decoding of superstrong forward error correction - Google Patents
Method and device for five times of iterative decoding of superstrong forward error correction Download PDFInfo
- Publication number
- CN103560797A CN103560797A CN201310491546.7A CN201310491546A CN103560797A CN 103560797 A CN103560797 A CN 103560797A CN 201310491546 A CN201310491546 A CN 201310491546A CN 103560797 A CN103560797 A CN 103560797A
- Authority
- CN
- China
- Prior art keywords
- bch
- row
- decoding
- sfec
- code
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
The invention discloses a method and device for five times of iterative decoding of superstrong forward error correction, and relates to the field of channel error correction coding and decoding in an optical communication system. The device comprises a synchronization word analytical unit, an internal frame mapping unit, an RAM storage unit, a control unit for five times of iterative decoding, a BCH (900, 860) code syndrome computing unit, a BCH (900, 860) code BM algorithm unit, a BCH (900, 860) code data buffer unit, a BCH (900, 860) code forward search and error correction unit, a BCH (500, 491) code syndrome computing unit, a BCH (500, 491) code data buffer unit, a BCH (500, 491) code forward search and error correction unit, an internal frame inverse mapping unit and a decoding performance monitoring unit. Hardware implementation resources are small in scale, and the good coding gain error correction performance is acquired through five times of iterative decoding.
Description
Technical field
The present invention relates to the channel Error-correcting Encoding and Decoding field in optical communication system, particularly relate to method and the device of five iterative decodings of a kind of super forward error correction.
Background technology
Along with the universal of Internet with develop rapidly, the demand of communication is also the trend of rapid growth.Because optical fiber exists huge band resource and excellent transmission performance, because of but realize at a high speed, the most desirable transmission medium of large volume transport.Along with the development of optical fiber transmission technique, optical fiber communication is occupied an leading position in transmission field.But growing distance or extra long distance, large capacity DWDM(Dense Wavelength Division Multiplexing, dense wave division multipurpose) in optical fiber telecommunications system, interference in signal attenuation, interchannel noise and an optical fiber that the dispersion of optical fiber, long Distance Transmission cause between a plurality of wavelength can make the performance of system greatly decline, for this reason, on fiber optic backbone, every about 80 kilometers, just must carry out once light relaying, every 400 kilometers of left and right, must carry out the regeneration of a signal of telecommunication, thereby the cost of networking and operation is increased severely.Keep again enough OSNR(Optical Signal Noise Ratio, Optical Signal To Noise Ratio when making transmission range longer), can be added to fiber optical power, the every increase of incident optical power 3dB can extend transmission range one times.Yet improving simply of incident optical power can cause larger fiber nonlinear effect, is unfavorable on the contrary realizing extra long distance transmission.
FEC(Forward Error Correction, forward error correction) be in Non-relay Ultra Long Span Optical Transmission System, effectively to increase a key technology of power system capacity, it by adding a small amount of redundant information in signal, find and correct the error code being caused by a variety of causes in transmitting procedure, reduce optical link neutral line and the impact of non-linear factor on systematic function, with lower cost and less bandwidth loss, exchange high-quality transmission for.The coding gain that adopts FEC to obtain, can improve the performance of existing fiber link, improves antijamming capability, reduces bit error rate; Increase the transmission range between two repeaters, realize long distance or the non-relay transmission of over distance; Keeping, under same bit error rate condition, can improving the rate of information throughput, increase the capacity of system; Realizing under the condition of same output bit error rate and identical traffic distance, can reduce transmitting power, reduce system cost simultaneously.Therefore, FEC technology will be one of the key core technology in this field, have stronger technology life cycle along with optical fiber communication speed is more and more higher in future.
Yet, needs along with extra long distance optical fiber transmission System Development, the increase of fibre system transmission rate, some unfavorable factors of restriction system transmission range, as more and more serious in the impact of signal attenuation, chromatic dispersion, polarization mode dispersion and nonlinear effect etc., the SFEC(Super Forward Error Correction in the urgent need to Design and implementation with stronger error correcting capability, super forward error correction).SFEC is for ITU-T(International Telecommunication Union Telecommunication Standardization Sector, standardization department of international telecommunication union telecommunication) the standard FEC of agreement defined G.709.Its RS(Reed-Solomon to standard forward error correction, Read-Solomon) (255,239) algorithm improves, and has adopted the forward error correction code encoding/decoding mode with more powerful error correcting capability, can significantly reduce the requirement of system to OSNR.At ITU-T, G.975.1 in agreement, multiple SFEC algorithm has been proposed, I.7, its appendix proposes to adopt two kinds of BCH(Bose-Chaudhuri-Hocquenghem, Bo Si-Cha Dehuli-Huo Kun lattice nurse) the enhanced FEC code plan that code carries out quadrature cascade, but how with hardware circuit, realizing iterative decoding function wherein, agreement is not explained.
Summary of the invention
The object of the invention is, in order to overcome the deficiency of above-mentioned background technology, provides method and the device of five iterative decodings of a kind of super forward error correction, and it is little that hardware is realized resource extent, but has obtained good coding gain error-correcting performance by five iterative decodings.
The method that the invention provides five iterative decodings of a kind of super forward error correction, comprises the following steps:
A, according to 2 rank optical transport unit OTU2 frame data of input, extract the synchronization character information of relevant positions, and it is analyzed, obtain the spread parameter of each code element of row, column code word in SFEC frame interior; According to the spread parameter of each code element of row, column code word in SFEC frame interior, by the data-mapping of OTU2 frame structure, be the data of SFEC frame interior structure: the data of OTU2 frame are classified according to loading section and check part, and it is stored in respectively in payload buffer memory and effect buffer memory, remove the data of synchronization character information in data flow simultaneously, the data of synchronization character information in data flow are preserved in addition; According to the spread parameter of each code element of row, column code word in SFEC frame interior, the data in payload buffer memory and effect buffer memory are read respectively according to the rule of SFEC frame interior, be filled in buffer memory RAM; The assembling of SFEC frame interior be take row code character and is carried out as unit;
B, at least 49 random access memory rams of use are stored in order to SFEC frame interior, and every block RAM is only deposited a SFEC frame interior, and data first deposit the 1st block RAM in, the 2nd, the 3rd successively ... until the 49th block RAM, then again since the 1st block RAM storage, so circulation; Control the read-write operation of 49 block RAMs, its input and output port corresponds respectively to the corresponding input/output signal of decoding five times, 5 iterative decodings are parallel to carry out: the 1st the SFEC frame interior preparation of selecting shine upon carries out for the first time (900,860) row decoding, meanwhile, select 2nd～23 SFEC frame interiors to prepare to carry out for the first time (500,491) column decoding, select the 24th SFEC frame interior to prepare to carry out for the second time (900,860) row decoding; Meanwhile, select 25th～46 SFEC frame interiors to prepare to carry out for the second time (500,491) column decoding, select the 47th SFEC frame interior to prepare to carry out (900,860) row decoding for the third time, the 48th SFEC frame interior carried out inverse mapping operation;
C, the data of each SFEC frame interior are carried out to five iterative decodings process, for single SFEC frame interior, first carry out BCH(900 for the first time, 860) row decoding, then carry out BCH(500 for the first time, 491) column decoding, carry out again BCH(900 for the second time, 860) row decoding, then carries out BCH(500 for the second time, 491) column decoding, finally carry out BCH(900 for the third time, 860) row decoding, for the data of optional position in SFEC frame interior, only, after previous decoding completes, just carry out decoded operation next time;
In above five iterative decoding processes, first carry out BCH(900,860) calculating of code syndrome, then utilize the syndrome result obtaining to carry out the calculating of BM algorithm, solve error location polynomial, according to the error location polynomial calculating, carry out money search and determine the position of wrong code element in BCH code word and carry out error correction, thereby complete the decoding of row code word one by one, process, the processing mode of row code word is as follows: first according to synchronization character information, from different SFEC frame interiors, select 16 or 17 row 32 Bit datas, be spliced into the row code word of 500 bits, each SFEC frame interior only selects 1 row, according to synchronization character information, find the head of each row code word, and unnecessary data are put into buffer memory, then 500 Bit datas of selecting are carried out to BCH(500, 491) decoding is processed: first adopt BCH(500, 491) code carries out the calculating of syndrome, the error correcting capability of column decoding is 1 bit, the result of being calculated by syndrome directly obtains error location polynomial, adopt again money search to carry out correction process, then by the redundant data in decode results and buffer memory, the form when reading re-starts combination, and be backfilled in SFEC frame interior corresponding position,
Error correction information in D, five decoding of statistical report;
E, SFEC frame interior is carried out to inverse mapping processing, SFEC frame interior data inverse is mapped as to the data of OTU2 frame structure.
On the basis of technique scheme, step B specifically comprises the following steps:
Step B1: defining a block RAM, to write a required time of SFEC frame interior data be a SFEC frame interior cycle, suppose to be in any one SFEC frame interior cycle k(k >=49), this cycle is carried out 7 operations simultaneously, these 7 operations for be different SFEC frame interiors; Definition i is SFEC frame interior sequence number, and i=k-49, and what (i+49) individual SFEC frame interior was prepared to carry out this moment is map operation, and soon the data-mapping in OTU2 is in SFEC frame interior buffer memory RAM; And its previous SFEC frame interior, (i+48) individual SFEC frame interior prepares to carry out BCH(900 for the first time in this moment, and 860) row decoding, simultaneously, (i+47)～(i+26) individual SFEC frame interior is prepared to carry out is BCH(500 for the first time, 491) and column decoding; (i+25) individual SFEC frame interior is prepared to carry out at cycle k is BCH(900 for the second time, 860) row decoding, (i+24)～(i+3) individual SFEC frame interior is prepared to carry out is BCH(500 for the second time, 491) column decoding, (i+2) individual SFEC frame interior is prepared to carry out is BCH(900 for the third time, 860) row decoding, last inverse mapping operation is carried out for (i+1) individual SFEC frame interior;
Step B2: at cycle k+1, at this moment there are again new data to be mapped as SFEC frame interior, i.e. (i+50) frame, (i+49) individual SFEC frame interior that upper one-period completes map operation carries out BCH(900 for the first time in this cycle, 860) row decoding, (i+48) individual SFEC frame interior joins BCH(500 for the first time, 491) in column decoding troop, carry out BCH(500 for the first time, 491) column decoding; Simultaneously, (i+26) individual SFEC frame interior has completed its whole column decoding tasks, then carry out BCH(900 for the second time, 860) row decoding, the rest may be inferred, and (i+25)～(i+4) individual SFEC frame interior carries out BCH(500 for the second time, and 491) column decoding, (i+3) and (i+2) individual SFEC frame interior carry out respectively BCH(900 for the third time, 860) row decoding and inverse mapping;
Step B3: k+48 cycle, (i+97) individual SFEC frame interior carries out map operation, (i+49) the individual SFEC frame interior that completes the earliest map operation carries out its last operation inverse mapping.
On the basis of technique scheme, the frame interior of SFEC described in step B1 carries out BCH(500 for the first time, 491) in the process of column decoding, each SFEC frame interior through at least 22 SFEC frame interiors week after date, just carry out BCH(900 for the second time, 860) row decoding.
On the basis of technique scheme, five iterative decoding processing procedures in step C are as follows:
Step C1, carry out BCH(900 for the first time, 860) row decoding: ready (i+48) individual SFEC frame interior in step B1 is carried out to BCH(900 for the first time, 860) row decoding, a SFEC frame interior has 32 row, row code word of each behavior, use 32 row decoders to carry out BCH(900 for the first time, 860 to 32 row code word data wherein simultaneously) row decoding, the processing mode of each row code word is identical;
The treatment step of row code word is as follows separately:
Step 101, calculate BCH(900,860) syndrome of code word, obtain 8 BCH(900,860) value of code syndrome;
Step 102,32 row code word data are put into buffer memory, then postponing certain umber of beats sends into step 104 and carries out correction process, the input data of decoding direction are carried out to buffer memory, treat BCH(900,860) syndrome, the BM Algorithm for Solving of code are complete while carrying out money search error correction, more synchronous sense data is sent into money search correction module and carried out synchronous correction process from this buffer memory;
Step 103,8 BCH(900 that obtain according to step 101,860) value of code syndrome, adopts the expression formula of BM Algorithm for Solving BCH code error location polynomial, obtains the root of error location polynomial;
The root of step 104, the error location polynomial that obtains according to step 103, and step 102 puts into 32 row code word data of buffer memory, completes the error correction of the wrong code element in BCH code word, and decode results is write to (i+48) individual SFEC frame interior again;
Step C2, carry out BCH(500 for the first time, 491) column decoding: to ready (i+47) in step B1～(i+26) individual SFEC frame interior carries out BCH(500 for the first time, 491) column decoding, 4 column decoders of each use carry out BCH(500 to 4 row code word data simultaneously, 491) decoding is processed, and the processing mode of each row code word is identical;
The treatment step of row code word is as follows separately:
Step 201: calculate BCH(500,491) syndrome of code word, obtains 2 BCH(500,491) value of code syndrome;
Step 202: the row code word data of input are put into buffer memory, then postponing certain umber of beats sends into step 203 and carries out correction process, the data of decoding direction are inputted into buffer memory, treat BCH(500,491) syndrome of code solves completely while carrying out money search error correction, more synchronous sense data is sent in money search correction module and carried out synchronous correction process from this buffer memory;
Step 203: 2 BCH(500 that obtain according to step 201,491) value of code syndrome, and step 202 puts into the row code word data of buffer memory, complete the error correction of the wrong code element in BCH code word, decode results is write to (i+47)～(i+26) individual SFEC frame interior again;
Step C3, carry out BCH(900 for the second time, 860) row decoding: ready (i+25) individual SFEC frame interior in step B1 is carried out to BCH(900 for the second time, 860) row decoding, use 32 row decoders to carry out BCH(900 for the second time to 32 row code word data wherein simultaneously, 860) row decoding, the processing mode of each row code word and BCH(900 for the first time, 860) row decoding is identical;
Step C4, carry out BCH(500 for the second time, 491) column decoding: to ready (i+24) in step B1～(i+3) individual SFEC frame interior carries out BCH(500 for the second time, 491) column decoding, 4 column decoders of each use carry out BCH(500 to 4 row code word data simultaneously, 491) decoding is processed, the processing mode of each row code word and BCH(500 for the first time, 491) column decoding is identical.
Step C5, carry out BCH(900 for the third time, 860) row decoding: ready (i+2) individual SFEC frame interior in step B1 is carried out to BCH(900 for the third time, 860) row decoding, use 32 row decoders to carry out BCH(900 for the third time to 32 row code word data wherein simultaneously, 860) row decoding, the processing mode of each row code word and BCH(900 for the first time, 860) row decoding is identical.
On the basis of technique scheme, step D comprises the following steps:
BCH(900 for the first time, 860) in row decoding, have 32 BCH code words, each clock cycle of each BCH code word produces 4 and entangles 1 error statistics signal, entangles 1 error statistics signal be added these 128, obtaining final BCH(900 for the first time, 860) row decoding entangles 1 error statistics; In like manner obtaining BCH(900 for the first time, 860) row decoding entangles 0 error statistics signal; BCH(900 for the first time, 860) in row decoding, there are 32 BCH code words, each clock cycle of each BCH code word produces one and can not error correction miss statistical signal, these 32 can not be added by error correction mistake statistical signal, obtaining final BCH(900 for the first time, 860) row decoding can not entangle error statistics;
BCH(500 for the first time, 491) in column decoding, have 4 BCH code words, each clock cycle of each BCH code word produces 32 and entangles 1 error statistics signal, entangles 1 error statistics signal be added these 128, obtaining final BCH(500 for the first time, 491) column decoding entangles 1 error statistics; In like manner obtaining BCH(500 for the first time, 491) column decoding entangles 0 error statistics signal;
BCH(900 for the second time, 860) in row decoding, have 32 BCH code words, each clock cycle of each BCH code word produces 4 and entangles 1 error statistics signal, entangles 1 error statistics signal be added these 128, obtaining final BCH(900 for the second time, 860) row decoding entangles 1 error statistics; In like manner obtaining BCH(900 for the second time, 860) row decoding entangles 0 error statistics signal; BCH(900 for the second time, 860) in row decoding, there are 32 BCH code words, each clock cycle of each BCH code word produces one and can not error correction miss statistical signal, these 32 can not be added by error correction mistake statistical signal, obtaining final BCH(900 for the second time, 860) row decoding can not entangle error statistics;
BCH(500 for the second time, 491) in column decoding, have 4 BCH code words, each clock cycle of each BCH code word produces 32 and entangles 1 error statistics signal, entangles 1 error statistics signal be added these 128, obtaining final BCH(500 for the second time, 491) column decoding entangles 1 error statistics; In like manner obtaining BCH(500 for the second time, 491) column decoding entangles 0 error statistics signal;
BCH(900 for the third time, 860) in row decoding, have 32 BCH code words, each clock cycle of each BCH code word produces 4 and entangles 1 error statistics signal, entangles 1 error statistics signal be added these 128, obtaining final BCH(900 for the third time, 860) row decoding entangles 1 error statistics; In like manner obtaining BCH(900 for the third time, 860) row decoding entangles 0 error statistics signal; BCH(900 for the third time, 860) in row decoding, there are 32 BCH code words, each clock cycle of each BCH code word produces one and can not error correction miss statistical signal, these 32 can not be added by error correction mistake statistical signal, obtaining final BCH(900 for the third time, 860) row decoding can not entangle error statistics.
On the basis of technique scheme, step e comprises the following steps: from OTU2 to SFEC mapping process, preserved relevant map information, the relevant information of preserving according to mapping, load data on SFEC relevant position and checking data are write respectively in the payload buffer memory and effect buffer memory of inverse mapping, and then formed the data of OTU2 frame structure.
On the basis of technique scheme, the length of the frame interior of SFEC described in steps A is 900 bits, and width is 32 bits, there are 32 row, 900 row, each SFEC frame interior takies a block RAM, the data width of every block RAM is 32 bits, and the address degree of depth is 900 bits.
On the basis of technique scheme, in steps A, a row code character comprises 4 row code words, for each row code character, 4 bits of each code word the first row are filled in order, then carry out the filling of next 4 bits, after having filled a row code character in current line code character, refill and join next row code character, the assemble sequence of whole row code character is carried out according to order from left to right, from top to bottom.
On the basis of technique scheme, described in step C in five iterative decoding processes, each row decoding is processed 32 row in SFEC frame interior respectively with 32 decoders simultaneously, the degree of parallelism of each decoder is 4, be single treatment 4 Bit datas, need 225 clock cycle to handle the row code word data of 900 bits; Each column decoding adopts 4 decoders 4 row code words to be carried out to decoding processing simultaneously, and the degree of parallelism of each column decoder is 32, i.e. single treatment 32 Bit datas need 16 clock cycle to handle the data of 500 bits.
It is a kind of for realizing the device of five iterative decodings of super forward error correction of said method that the present invention also provides, comprise synchronization character analytic unit, frame interior map unit, ram memory cell, five iterative decoding control units, BCH(900, 860) code syndrome computing unit, BCH(900, 860) code BM algorithm unit, BCH(900, 860) code data buffer cell, BCH(900, 860) search of code money and error correction unit, BCH(500, 491) code syndrome computing unit, BCH(500, 491) code data buffer cell, BCH(500, 491) search of code money and error correction unit, frame interior inverse mapping unit and decoding performance monitoring unit, wherein:
Synchronization character analytic unit, for: extract the synchronization character information of OTU2 frame data relevant position and analyze, the SFEC frame interior parameter obtaining being passed to frame interior mapping block simultaneously;
Frame interior map unit, for: by the data-mapping of OTU2 frame format, be the data of SFEC frame interior form;
Ram memory cell, for: deposit in order the SFEC frame interior data of having shone upon in RAM, and carry out read-write operation according to the instruction of five iterative decoding control units and frame interior inverse mapping unit;
Five iterative decoding control units, be used for: control SFEC frame interior data and carry out in order three row decodings and twice column decoding, the order of five iterative decodings is: BCH(900 for the first time, 860) row decoding, BCH(500 for the first time, 491) column decoding, BCH(900 for the second time, 860) row decoding, BCH(500 for the second time, 491) column decoding, BCH(900 for the third time, 860) row decoding, data for optional position, only, after previous decoding completes, just can carry out decoded operation next time;
BCH(900,860) code syndrome computing unit, for: complete BCH(900,860) calculating of 8 syndromes of code;
BCH(900,860) code BM algorithm unit, for: according to the BCH(900 having obtained, 860) value of code syndrome, solve the expression formula of error location polynomial, obtain the root of error location polynomial;
BCH(900,860) code data buffer cell, for: data to decode is put into buffer memory, then postpones certain umber of beats and send into BCH(900,860) code money searches for and error correction unit is carried out correction process;
BCH(900,860) search of code money and error correction unit, for: solve BCH(900,860) root of the error location polynomial that code BM algorithm unit obtains, orient each BCH(900,860) wrong element position in code word, thus complete the error correction of the wrong code element in code word;
BCH(500,491) code syndrome computing unit, for: complete BCH(500,491) calculating of code syndrome, obtain BCH(500,491) code syndrome;
BCH(500,491) code data buffer cell, for: data to decode is put into buffer memory, then postpones certain umber of beats and send into BCH(500,491) code money searches for and error correction unit is carried out correction process;
BCH(500,491) search of code money and error correction unit, be used for: utilize BCH(500,491) BCH(500 that code syndrome computing unit calculates, 491) code syndrome, orient each BCH(500,491) wrong element position in code word, thus complete the error correction of the wrong code element in code word;
Frame interior inverse mapping unit, for: realize data flow from SFEC frame interior to the format conversion OTU2 frame, be about to the OTU2 frame structure data of SFEC frame interior structured data in being converted to G.975;
Decoding performance monitoring unit, for: the performance monitoring function that completes five iterative decodings.
Compared with prior art, advantage of the present invention is as follows:
It is little that hardware of the present invention is realized resource extent, but obtained good coding gain error-correcting performance by five iterative decodings.
Accompanying drawing explanation
Fig. 1 is the flow chart of the method for five iterative decodings of super forward error correction in the embodiment of the present invention.
Fig. 2 is the structural representation of OTU2 frame in the embodiment of the present invention.
Fig. 3 is the structural representation of SFEC frame interior in the embodiment of the present invention.
Fig. 4 is the flow chart of SFEC frame interior data assembling in the embodiment of the present invention.
Fig. 5 is the schematic diagram of five iterative decoding parallel work-flows in the embodiment of the present invention.
Fig. 6 is the schematic diagram of 5 iterative decodings of a SFEC frame interior in the embodiment of the present invention.
Fig. 7 is the structured flowchart of the device of five iterative decodings of embodiment of the present invention super forward error correction.
Embodiment
Below in conjunction with drawings and the specific embodiments, the present invention is described in further detail.
Shown in Figure 1, the embodiment of the present invention provides the method for five iterative decodings of a kind of super forward error correction, comprises the following steps:
A, according to input OTU2(Optical Transport Unit2,2 rank optical transport units) frame data extract the synchronization character information of relevant position, and it is analyzed, obtain the spread parameter of each code element of row, column code word in SFEC frame interior, shown in Figure 2, each OTU2 frame has 32 bits for transmitting synchronizing information; According to the spread parameter of each code element of row, column code word in SFEC frame interior, by the data-mapping of OTU2 frame structure, be the data of SFEC frame interior structure: the data of OTU2 frame are classified according to loading section and check part, and it is stored in respectively in payload buffer memory and effect buffer memory, remove the data of synchronization character information in data flow simultaneously, the data of synchronization character information in data flow are preserved in addition; According to the spread parameter of each code element of row, column code word in SFEC frame interior, data in payload buffer memory and effect buffer memory are read respectively according to the rule of SFEC frame interior, be filled in buffer memory RAM, the length of each SFEC frame interior is 900 bits, and width is 32 bits, there are 32 row, 900 row, shown in Figure 3, each SFEC frame interior takies a block RAM, the data width of every block RAM is 32 bits, and the address degree of depth is 900 bits.The assembling of SFEC frame interior be take row code character and is carried out as unit, and a row code character comprises 4 row code words, and for each row code character, 4 bits of each code word the first row are filled in order, then carry out the filling of next 4 bits.After having filled a row code character in current line code character, refill and join next row code character, the assemble sequence that is whole row code character be according to from left to right, from top to bottom in sequence, shown in Figure 4, in Fig. 4, the label of each bit represents its assemble sequence in assembling process.
B, use at least 49 block RAMs (Random Access Memory, random asccess memory) SFEC frame interior is stored in order, every block RAM is only deposited a SFEC frame interior, data first deposit the 1st block RAM in, the 2nd, the 3rd successively ... until the 49th block RAM, then again since the 1st block RAM storage, so circulation; Control the read-write operation of 49 block RAMs, its input and output port corresponds respectively to the corresponding input/output signal of decoding five times, in order to realize pipeline operation, 5 parallel carrying out of iterative decoding, shown in Figure 5, the 1st the SFEC frame interior preparation of selecting shine upon carries out for the first time (900,860) row decoding, simultaneously, select 2nd～23 SFEC frame interiors to prepare to carry out for the first time (500,491) column decoding, selects the 24th SFEC frame interior to prepare to carry out for the second time (900,860) row decoding; Meanwhile, select 25th～46 SFEC frame interiors to prepare to carry out for the second time (500,491) column decoding, select the 47th SFEC frame interior to prepare to carry out (900,860) row decoding for the third time, the 48th SFEC frame interior carried out inverse mapping operation.
Particularly, step B can be subdivided into following 3 sub-steps:
Step B1: defining a block RAM, to write a required time of SFEC frame interior data be a SFEC frame interior cycle, hypothesis is in any one SFEC frame interior cycle k(k >=49 so), this cycle can be carried out 7 operations simultaneously, just these 7 operations for be different SFEC frame interiors; Definition i is SFEC frame interior sequence number, and i=k-49, and so at the moment, what (i+49) individual SFEC frame interior was prepared to carry out is map operation, and soon the data-mapping in OTU2 is in SFEC frame interior buffer memory RAM; And its previous SFEC frame interior, (i+48) individual SFEC frame interior prepares to carry out BCH(900 for the first time in this moment, and 860) row decoding, simultaneously, (i+47)～(i+26) individual SFEC frame interior is prepared to carry out is BCH(500 for the first time, 491) and column decoding.Because each column decoding relates at most 22 SFEC frame interiors, so each SFEC frame interior is through all after dates of at least 22 SFEC frame interiors, just can carry out BCH(900 for the second time, 860) row decoding.For example, during cycle k, (i+47) individual SFEC frame interior is to participate in for the first time column decoding, and afterwards until cycle k+23, it just can carry out BCH(900 for the second time, 860) row decoding.In like manner, (i+25) individual SFEC frame interior is prepared to carry out at cycle k is BCH(900 for the second time, 860) row decoding, (i+24)～(i+3) individual SFEC frame interior is prepared to carry out is BCH(500 for the second time, 491) column decoding, (i+2) individual SFEC frame interior is prepared to carry out is BCH(900 for the third time, 860) and row decoding, last inverse mapping operation is carried out for (i+1) individual SFEC frame interior.
Step B2: at cycle k+1, at this moment there are again new data to be mapped as SFEC frame interior, i.e. (i+50) frame, (i+49) individual SFEC frame interior that upper one-period completes map operation carries out BCH(900 for the first time in this cycle, 860) row decoding, (i+48) individual SFEC frame interior joins BCH(500 for the first time, 491) in column decoding troop, carry out BCH(500 for the first time, 491) column decoding; Meanwhile, (i+26) individual SFEC frame interior is because having completed its whole column decoding tasks, then carries out BCH(900 for the second time, 860) row decoding.The rest may be inferred, and (i+25)～(i+4) individual SFEC frame interior carries out BCH(500 for the second time, and 491) column decoding, (i+3) and (i+2) individual SFEC frame interior carry out respectively BCH(900 for the third time, 860) row decoding and inverse mapping.
Step B3: k+48 cycle, (i+97) individual SFEC frame interior carries out map operation, (i+49) the individual SFEC frame interior that completes the earliest map operation carries out its last operation inverse mapping.Fig. 6 has provided the process that a SFEC frame interior completes 7 operations of decoding.Visible, from mapping, start to finish to inverse mapping, the whole decode procedure of a SFEC frame interior will experience 48 cycles.Once certain SFEC frame interior completes inverse mapping, its memory space just can be for preserving new data, therefore whole process only need to be preserved the data of 49 SFEC frame interiors.
C, the data of each SFEC frame interior are carried out to five iterative decodings process, for single SFEC frame interior, first carry out BCH(900 for the first time, 860) row decoding, then carry out BCH(500 for the first time, 491) column decoding, carry out again BCH(900 for the second time, 860) row decoding, then carries out BCH(500 for the second time, 491) column decoding, finally carry out BCH(900 for the third time, 860) row decoding, for the data of optional position in SFEC frame interior, only, after previous decoding completes, just can carry out decoded operation next time.And in order to meet the requirement of code check, in the scope of 49 SFEC frame interiors, five times iterative decoding carries out simultaneously, the content non-overlapping copies that each row or column decoding comprises, it processes respectively the data of different SFEC frame interiors, corrects the mistake receiving in data by these 5 iterative decodings.
In above five iterative decoding processes, each row decoding is processed 32 row in SFEC frame interior respectively with 32 decoders simultaneously, the degree of parallelism of each decoder is 4, i.e. single treatment 4 Bit datas need 225 clock cycle to handle the row code word data of 900 bits.Its idiographic flow is: first carry out BCH(900,860) calculating of code syndrome, then utilize the syndrome result obtaining to carry out BM(Berlekamp-Massey, Berlekamp-Mei Xi) calculating of algorithm, solve error location polynomial, according to the error location polynomial calculating, carry out money search and determine the position of wrong code element in BCH code word and carry out error correction, thereby complete the decoding of row code word one by one, process.
The processing mode of row code word is as follows: first according to synchronization character information, from different SFEC frame interiors, select 16 or 17 row 32 Bit datas, be spliced into the row code word of 500 bits, each SFEC frame interior only selects 1 row, can not be divided exactly by 32 due to 500, so need to find according to synchronization character information the head of each row code word, and unnecessary data are put into buffer memory, then 500 Bit datas of selecting are carried out to BCH(500, 491) decoding is processed: first adopt BCH(500, 491) code carries out the calculating of syndrome, because the error correcting capability of column decoding is 1 bit, the result that can be calculated by syndrome directly obtains error location polynomial, adopt again money search to carry out correction process, then by the redundant data in decode results and buffer memory, the form when reading re-starts combination, and be backfilled in SFEC frame interior corresponding position.Each column decoding adopts 4 decoders 4 row code words to be carried out to decoding processing simultaneously, and the degree of parallelism of each column decoder is 32, i.e. single treatment 32 Bit datas need 16 clock cycle to handle the data of 500 bits.
Describe five iterative decoding processing procedures in step C below in detail.
Step C1, carry out BCH(900 for the first time, 860) row decoding: ready (i+48) individual SFEC frame interior in step B1 is carried out to BCH(900 for the first time, 860) row decoding.A SFEC frame interior has 32 row, row code word of each behavior.Use 32 row decoders to carry out BCH(900 for the first time, 860 to 32 row code word data wherein simultaneously) row decoding, the processing mode of each row code word is identical.
The treatment step of row code word can be divided into following sub-step separately:
Step 101, calculate BCH(900,860) syndrome of code word, obtain 8 BCH(900,860) value of code syndrome;
Step 102,32 row code word data are put into buffer memory, then postpone certain umber of beats and send into step 104 and carry out correction process.Owing to carrying out BCH(900,860) in the process of code decoding, solve BCH(900,860) syndrome of code, the time of clock cycle that BM algorithm all needs some carry out BCH(900,860) processing of the wrong code element location of code word, therefore the input data of decoding direction need to be carried out to buffer memory, treat BCH(900,860) syndrome, the BM Algorithm for Solving of code are complete while carrying out money search error correction, more synchronous sense data is sent into money search correction module and carried out synchronous correction process from this buffer memory.
Step 103,8 BCH(900 that obtain according to step 101,860) value of code syndrome, adopts the expression formula of BM Algorithm for Solving BCH code error location polynomial, thereby obtains the root of error location polynomial.
The root of step 104, the error location polynomial that obtains according to step 103, and step 102 puts into 32 row code word data of buffer memory, completes the error correction of the wrong code element in BCH code word, and decode results is write to (i+48) individual SFEC frame interior again.
Step C2, carry out BCH(500 for the first time, 491) column decoding: to ready (i+47) in step B1～(i+26) individual SFEC frame interior carries out BCH(500 for the first time, 491) column decoding.In this device, use 4 column decoders 4 row code word data to be carried out to BCH(500,491 at every turn simultaneously) decoding processing, the processing mode of each row code word is identical,
The treatment step of row code word can be divided into following sub-step separately:
Step 201: calculate BCH(500,491) syndrome of code word, obtains 2 BCH(500,491) value of code syndrome.
Step 202: the row code word data of input are put into buffer memory, then postpone certain umber of beats and send into step 203 and carry out correction process.Owing to carrying out BCH(500,491) in the process of code decoding, solve BCH(500,491) syndrome of code needs the time of the clock cycle of some to carry out BCH(500,491) processing of the wrong code element location of code word, therefore need to input the data of decoding direction into buffer memory, treats BCH(500,491) syndrome of code solves completely while carrying out money search error correction, more synchronous sense data is sent in money search correction module and carried out synchronous correction process from this buffer memory.
Step 203: 2 BCH(500 that obtain according to step 201,491) value of code syndrome, and step 202 puts into the row code word data of buffer memory, complete the error correction of the wrong code element in BCH code word, decode results is write to (i+47)～(i+26) individual SFEC frame interior again.
Step C3, carry out BCH(900 for the second time, 860) row decoding: ready (i+25) individual SFEC frame interior in step B1 is carried out to BCH(900 for the second time, 860) row decoding.Use 32 row decoders to carry out BCH(900 for the second time, 860 to 32 row code word data wherein simultaneously) row decoding, the processing mode of each row code word and BCH(900 for the first time, 860) row decoding is identical.
Step C4, carry out BCH(500 for the second time, 491) column decoding: to ready (i+24) in step B1～(i+3) individual SFEC frame interior carries out BCH(500 for the second time, 491) column decoding.Each use 4 column decoders 4 row code word data to be carried out to BCH(500,491 simultaneously) decoding processes, the processing mode of each row code word and BCH(500 for the first time, 491) column decoding is identical.
Step C5, carry out BCH(900 for the third time, 860) row decoding: ready (i+2) individual SFEC frame interior in step B1 is carried out to BCH(900 for the third time, 860) row decoding.Use 32 row decoders to carry out BCH(900 for the third time, 860 to 32 row code word data wherein simultaneously) row decoding, the processing mode of each row code word and BCH(900 for the first time, 860) row decoding is identical.
Error correction information in D, five decoding of statistical report:
BCH(900 for the first time, 860) in row decoding, there are 32 BCH code words, each clock cycle of each BCH code word produces 4 and entangles 1 error statistics signal, by this 128(32*4) the individual 1 error statistics signal that entangles is added, obtaining final BCH(900 for the first time, 860) row decoding entangles 1 error statistics; In like manner obtaining BCH(900 for the first time, 860) row decoding entangles 0 error statistics signal; BCH(900 for the first time, 860) in row decoding, there are 32 BCH code words, each clock cycle of each BCH code word produces one and can not error correction miss statistical signal, these 32 can not be added by error correction mistake statistical signal, obtaining final BCH(900 for the first time, 860) row decoding can not entangle error statistics;
BCH(500 for the first time, 491) in column decoding, there are 4 BCH code words, each clock cycle of each BCH code word produces 32 and entangles 1 error statistics signal, by this 128(4*32) the individual 1 error statistics signal that entangles is added, obtaining final BCH(500 for the first time, 491) column decoding entangles 1 error statistics; In like manner obtaining BCH(500 for the first time, 491) column decoding entangles 0 error statistics signal;
BCH(900 for the second time, 860) in row decoding, there are 32 BCH code words, each clock cycle of each BCH code word produces 4 and entangles 1 error statistics signal, by this 128(32*4) the individual 1 error statistics signal that entangles is added, obtaining final BCH(900 for the second time, 860) row decoding entangles 1 error statistics; In like manner obtaining BCH(900 for the second time, 860) row decoding entangles 0 error statistics signal; BCH(900 for the second time, 860) in row decoding, there are 32 BCH code words, each clock cycle of each BCH code word produces one and can not error correction miss statistical signal, these 32 can not be added by error correction mistake statistical signal, obtaining final BCH(900 for the second time, 860) row decoding can not entangle error statistics;
BCH(500 for the second time, 491) in column decoding, there are 4 BCH code words, each clock cycle of each BCH code word produces 32 and entangles 1 error statistics signal, by this 128(4*32) the individual 1 error statistics signal that entangles is added, obtaining final BCH(500 for the second time, 491) column decoding entangles 1 error statistics; In like manner obtaining BCH(500 for the second time, 491) column decoding entangles 0 error statistics signal;
BCH(900 for the third time, 860) in row decoding, there are 32 BCH code words, each clock cycle of each BCH code word produces 4 and entangles 1 error statistics signal, by this 128(32*4) the individual 1 error statistics signal that entangles is added, obtaining final BCH(900 for the third time, 860) row decoding entangles 1 error statistics; In like manner obtaining BCH(900 for the third time, 860) row decoding entangles 0 error statistics signal; BCH(900 for the third time, 860) in row decoding, there are 32 BCH code words, each clock cycle of each BCH code word produces one and can not error correction miss statistical signal, these 32 can not be added by error correction mistake statistical signal, obtaining final BCH(900 for the third time, 860) row decoding can not entangle error statistics.
E, ready (i+1) individual SFEC frame interior in step B1 is carried out to inverse mapping processing, SFEC frame interior data inverse is as shown in Figure 3 mapped as to the data of OTU2 frame structure as shown in Figure 2.Due to from OTU2 to SFEC mapping process, preserved relevant map information.The process of inverse mapping is similar to mapping, and the relevant information of preserving according to mapping, writes the load data on SFEC relevant position and checking data respectively in the payload buffer memory and effect buffer memory of inverse mapping, and then forms the data of OTU2 frame structure.
Shown in Figure 7, on the basis of the method for five iterative decodings of above-mentioned super forward error correction, the embodiment of the present invention also provides the device of five iterative decodings of a kind of super forward error correction, comprise synchronization character analytic unit, frame interior map unit, ram memory cell, five iterative decoding control units, BCH(900, 860) code syndrome computing unit, BCH(900, 860) code BM algorithm unit, BCH(900, 860) code data buffer cell, BCH(900, 860) search of code money and error correction unit, BCH(500, 491) code syndrome computing unit, BCH(500, 491) code data buffer cell, BCH(500, 491) search of code money and error correction unit, frame interior inverse mapping unit and decoding performance monitoring unit, wherein:
Synchronization character analytic unit, for: extract the synchronization character information of OTU2 frame data relevant position and analyze, the SFEC frame interior parameter obtaining being passed to frame interior mapping block simultaneously;
Frame interior map unit, for: by the data-mapping of OTU2 frame format, be the data of SFEC frame interior form;
Ram memory cell, for: deposit in order the SFEC frame interior data of having shone upon in RAM, and carry out read-write operation according to the instruction of five iterative decoding control units and frame interior inverse mapping unit;
Five iterative decoding control units, be used for: control SFEC frame interior data and carry out in order three row decodings and twice column decoding, the order of five iterative decodings is BCH(900 for the first time, 860) row decoding, BCH(500 for the first time, 491) column decoding, BCH(900 for the second time, 860) row decoding, BCH(500 for the second time, 491) column decoding, BCH(900 for the third time, 860) row decoding, data for optional position, only, after previous decoding completes, just can carry out decoded operation next time;
BCH(900,860) code syndrome computing unit, for: complete BCH(900,860) calculating of 8 syndromes of code;
BCH(900,860) code BM algorithm unit, for: according to the BCH(900 having obtained, 860) value of code syndrome, solve the expression formula of error location polynomial, obtain the root of error location polynomial;
BCH(900,860) code data buffer cell, for: data to decode is put into buffer memory, then postpones certain umber of beats and send into BCH(900,860) code money searches for and error correction unit is carried out correction process;
BCH(900,860) search of code money and error correction unit, for: solve BCH(900,860) root of the error location polynomial that code BM algorithm unit obtains, orient each BCH(900,860) wrong element position in code word, thus complete the error correction of the wrong code element in code word;
BCH(500,491) code syndrome computing unit, for: complete BCH(500,491) calculating of code syndrome, obtain BCH(500,491) code syndrome;
BCH(500,491) code data buffer cell, for: data to decode is put into buffer memory, then postpones certain umber of beats and send into BCH(500,491) code money searches for and error correction unit is carried out correction process;
BCH(500,491) search of code money and error correction unit, be used for: utilize BCH(500,491) BCH(500 that code syndrome computing unit calculates, 491) code syndrome, orient each BCH(500,491) wrong element position in code word, thus complete the error correction of the wrong code element in code word;
Frame interior inverse mapping unit, for: realize data flow from SFEC frame interior to the format conversion OTU2 frame, be about to the OTU2 frame structure data of SFEC frame interior structured data in being converted to G.975;
Decoding performance monitoring unit, for: the performance monitoring function that completes five iterative decodings.
Those skilled in the art can carry out various modifications and variations to the embodiment of the present invention, if these revise and modification within the scope of the claims in the present invention and equivalent technologies thereof, these modifications and modification are also within protection scope of the present invention.
The prior art that the content of not describing in detail in specification is known to the skilled person.
Claims (10)
1. a method for five iterative decodings of super forward error correction, is characterized in that, comprises the following steps:
A, according to 2 rank optical transport unit OTU2 frame data of input, extract the synchronization character information of relevant positions, and it is analyzed, obtain the spread parameter of each code element of row, column code word in SFEC frame interior; According to the spread parameter of each code element of row, column code word in SFEC frame interior, by the data-mapping of OTU2 frame structure, be the data of SFEC frame interior structure: the data of OTU2 frame are classified according to loading section and check part, and it is stored in respectively in payload buffer memory and effect buffer memory, remove the data of synchronization character information in data flow simultaneously, the data of synchronization character information in data flow are preserved in addition; According to the spread parameter of each code element of row, column code word in SFEC frame interior, the data in payload buffer memory and effect buffer memory are read respectively according to the rule of SFEC frame interior, be filled in buffer memory RAM; The assembling of SFEC frame interior be take row code character and is carried out as unit;
B, at least 49 random access memory rams of use are stored in order to SFEC frame interior, and every block RAM is only deposited a SFEC frame interior, and data first deposit the 1st block RAM in, the 2nd, the 3rd successively ... until the 49th block RAM, then again since the 1st block RAM storage, so circulation; Control the read-write operation of 49 block RAMs, its input and output port corresponds respectively to the corresponding input/output signal of decoding five times, 5 iterative decodings are parallel to carry out: the 1st the SFEC frame interior preparation of selecting shine upon carries out for the first time (900,860) row decoding, meanwhile, select 2nd～23 SFEC frame interiors to prepare to carry out for the first time (500,491) column decoding, select the 24th SFEC frame interior to prepare to carry out for the second time (900,860) row decoding; Meanwhile, select 25th～46 SFEC frame interiors to prepare to carry out for the second time (500,491) column decoding, select the 47th SFEC frame interior to prepare to carry out (900,860) row decoding for the third time, the 48th SFEC frame interior carried out inverse mapping operation;
C, the data of each SFEC frame interior are carried out to five iterative decodings process, for single SFEC frame interior, first carry out BCH(900 for the first time, 860) row decoding, then carry out BCH(500 for the first time, 491) column decoding, carry out again BCH(900 for the second time, 860) row decoding, then carries out BCH(500 for the second time, 491) column decoding, finally carry out BCH(900 for the third time, 860) row decoding, for the data of optional position in SFEC frame interior, only, after previous decoding completes, just carry out decoded operation next time;
In above five iterative decoding processes, first carry out BCH(900,860) calculating of code syndrome, then utilize the syndrome result obtaining to carry out the calculating of BM algorithm, solve error location polynomial, according to the error location polynomial calculating, carry out money search and determine the position of wrong code element in BCH code word and carry out error correction, thereby complete the decoding of row code word one by one, process, the processing mode of row code word is as follows: first according to synchronization character information, from different SFEC frame interiors, select 16 or 17 row 32 Bit datas, be spliced into the row code word of 500 bits, each SFEC frame interior only selects 1 row, according to synchronization character information, find the head of each row code word, and unnecessary data are put into buffer memory, then 500 Bit datas of selecting are carried out to BCH(500, 491) decoding is processed: first adopt BCH(500, 491) code carries out the calculating of syndrome, the error correcting capability of column decoding is 1 bit, the result of being calculated by syndrome directly obtains error location polynomial, adopt again money search to carry out correction process, then by the redundant data in decode results and buffer memory, the form when reading re-starts combination, and be backfilled in SFEC frame interior corresponding position,
Error correction information in D, five decoding of statistical report;
E, SFEC frame interior is carried out to inverse mapping processing, SFEC frame interior data inverse is mapped as to the data of OTU2 frame structure.
2. the method for five iterative decodings of super forward error correction as claimed in claim 1, is characterized in that: step B specifically comprises the following steps:
Step B1: defining a block RAM, to write a required time of SFEC frame interior data be a SFEC frame interior cycle, suppose to be in any one SFEC frame interior cycle k(k >=49), this cycle is carried out 7 operations simultaneously, these 7 operations for be different SFEC frame interiors; Definition i is SFEC frame interior sequence number, and i=k-49, and what (i+49) individual SFEC frame interior was prepared to carry out this moment is map operation, and soon the data-mapping in OTU2 is in SFEC frame interior buffer memory RAM; And its previous SFEC frame interior, (i+48) individual SFEC frame interior prepares to carry out BCH(900 for the first time in this moment, and 860) row decoding, simultaneously, (i+47)～(i+26) individual SFEC frame interior is prepared to carry out is BCH(500 for the first time, 491) and column decoding; (i+25) individual SFEC frame interior is prepared to carry out at cycle k is BCH(900 for the second time, 860) row decoding, (i+24)～(i+3) individual SFEC frame interior is prepared to carry out is BCH(500 for the second time, 491) column decoding, (i+2) individual SFEC frame interior is prepared to carry out is BCH(900 for the third time, 860) row decoding, last inverse mapping operation is carried out for (i+1) individual SFEC frame interior;
Step B2: at cycle k+1, at this moment there are again new data to be mapped as SFEC frame interior, i.e. (i+50) frame, (i+49) individual SFEC frame interior that upper one-period completes map operation carries out BCH(900 for the first time in this cycle, 860) row decoding, (i+48) individual SFEC frame interior joins BCH(500 for the first time, 491) in column decoding troop, carry out BCH(500 for the first time, 491) column decoding; Simultaneously, (i+26) individual SFEC frame interior has completed its whole column decoding tasks, then carry out BCH(900 for the second time, 860) row decoding, the rest may be inferred, and (i+25)～(i+4) individual SFEC frame interior carries out BCH(500 for the second time, and 491) column decoding, (i+3) and (i+2) individual SFEC frame interior carry out respectively BCH(900 for the third time, 860) row decoding and inverse mapping;
Step B3: k+48 cycle, (i+97) individual SFEC frame interior carries out map operation, (i+49) the individual SFEC frame interior that completes the earliest map operation carries out its last operation inverse mapping.
3. the method for five iterative decodings of super forward error correction as claimed in claim 2, it is characterized in that: the frame interior of SFEC described in step B1 carries out BCH(500 for the first time, 491) in the process of column decoding, each SFEC frame interior is through at least 22 SFEC frame interiors week after date, just carry out BCH(900 for the second time, 860) row decoding.
4. the method for five iterative decodings of super forward error correction as claimed in claim 2, is characterized in that: five iterative decoding processing procedures in step C are as follows:
Step C1, carry out BCH(900 for the first time, 860) row decoding: ready (i+48) individual SFEC frame interior in step B1 is carried out to BCH(900 for the first time, 860) row decoding, a SFEC frame interior has 32 row, row code word of each behavior, use 32 row decoders to carry out BCH(900 for the first time, 860 to 32 row code word data wherein simultaneously) row decoding, the processing mode of each row code word is identical;
The treatment step of row code word is as follows separately:
Step 101, calculate BCH(900,860) syndrome of code word, obtain 8 BCH(900,860) value of code syndrome;
Step 102,32 row code word data are put into buffer memory, then postponing certain umber of beats sends into step 104 and carries out correction process, the input data of decoding direction are carried out to buffer memory, treat BCH(900,860) syndrome, the BM Algorithm for Solving of code are complete while carrying out money search error correction, more synchronous sense data is sent into money search correction module and carried out synchronous correction process from this buffer memory;
Step 103,8 BCH(900 that obtain according to step 101,860) value of code syndrome, adopts the expression formula of BM Algorithm for Solving BCH code error location polynomial, obtains the root of error location polynomial;
The root of step 104, the error location polynomial that obtains according to step 103, and step 102 puts into 32 row code word data of buffer memory, completes the error correction of the wrong code element in BCH code word, and decode results is write to (i+48) individual SFEC frame interior again;
Step C2, carry out BCH(500 for the first time, 491) column decoding: to ready (i+47) in step B1～(i+26) individual SFEC frame interior carries out BCH(500 for the first time, 491) column decoding, 4 column decoders of each use carry out BCH(500 to 4 row code word data simultaneously, 491) decoding is processed, and the processing mode of each row code word is identical;
The treatment step of row code word is as follows separately:
Step 201: calculate BCH(500,491) syndrome of code word, obtains 2 BCH(500,491) value of code syndrome;
Step 202: the row code word data of input are put into buffer memory, then postponing certain umber of beats sends into step 203 and carries out correction process, the data of decoding direction are inputted into buffer memory, treat BCH(500,491) syndrome of code solves completely while carrying out money search error correction, more synchronous sense data is sent in money search correction module and carried out synchronous correction process from this buffer memory;
Step 203: 2 BCH(500 that obtain according to step 201,491) value of code syndrome, and step 202 puts into the row code word data of buffer memory, complete the error correction of the wrong code element in BCH code word, decode results is write to (i+47)～(i+26) individual SFEC frame interior again;
Step C3, carry out BCH(900 for the second time, 860) row decoding: ready (i+25) individual SFEC frame interior in step B1 is carried out to BCH(900 for the second time, 860) row decoding, use 32 row decoders to carry out BCH(900 for the second time to 32 row code word data wherein simultaneously, 860) row decoding, the processing mode of each row code word and BCH(900 for the first time, 860) row decoding is identical;
Step C4, carry out BCH(500 for the second time, 491) column decoding: to ready (i+24) in step B1～(i+3) individual SFEC frame interior carries out BCH(500 for the second time, 491) column decoding, 4 column decoders of each use carry out BCH(500 to 4 row code word data simultaneously, 491) decoding is processed, the processing mode of each row code word and BCH(500 for the first time, 491) column decoding is identical.
Step C5, carry out BCH(900 for the third time, 860) row decoding: ready (i+2) individual SFEC frame interior in step B1 is carried out to BCH(900 for the third time, 860) row decoding, use 32 row decoders to carry out BCH(900 for the third time to 32 row code word data wherein simultaneously, 860) row decoding, the processing mode of each row code word and BCH(900 for the first time, 860) row decoding is identical.
5. the method for five iterative decodings of super forward error correction as claimed in claim 4, is characterized in that: step D comprises the following steps:
BCH(900 for the first time, 860) in row decoding, have 32 BCH code words, each clock cycle of each BCH code word produces 4 and entangles 1 error statistics signal, entangles 1 error statistics signal be added these 128, obtaining final BCH(900 for the first time, 860) row decoding entangles 1 error statistics; In like manner obtaining BCH(900 for the first time, 860) row decoding entangles 0 error statistics signal; BCH(900 for the first time, 860) in row decoding, there are 32 BCH code words, each clock cycle of each BCH code word produces one and can not error correction miss statistical signal, these 32 can not be added by error correction mistake statistical signal, obtaining final BCH(900 for the first time, 860) row decoding can not entangle error statistics;
BCH(500 for the first time, 491) in column decoding, have 4 BCH code words, each clock cycle of each BCH code word produces 32 and entangles 1 error statistics signal, entangles 1 error statistics signal be added these 128, obtaining final BCH(500 for the first time, 491) column decoding entangles 1 error statistics; In like manner obtaining BCH(500 for the first time, 491) column decoding entangles 0 error statistics signal;
BCH(900 for the second time, 860) in row decoding, have 32 BCH code words, each clock cycle of each BCH code word produces 4 and entangles 1 error statistics signal, entangles 1 error statistics signal be added these 128, obtaining final BCH(900 for the second time, 860) row decoding entangles 1 error statistics; In like manner obtaining BCH(900 for the second time, 860) row decoding entangles 0 error statistics signal; BCH(900 for the second time, 860) in row decoding, there are 32 BCH code words, each clock cycle of each BCH code word produces one and can not error correction miss statistical signal, these 32 can not be added by error correction mistake statistical signal, obtaining final BCH(900 for the second time, 860) row decoding can not entangle error statistics;
BCH(500 for the second time, 491) in column decoding, have 4 BCH code words, each clock cycle of each BCH code word produces 32 and entangles 1 error statistics signal, entangles 1 error statistics signal be added these 128, obtaining final BCH(500 for the second time, 491) column decoding entangles 1 error statistics; In like manner obtaining BCH(500 for the second time, 491) column decoding entangles 0 error statistics signal;
BCH(900 for the third time, 860) in row decoding, have 32 BCH code words, each clock cycle of each BCH code word produces 4 and entangles 1 error statistics signal, entangles 1 error statistics signal be added these 128, obtaining final BCH(900 for the third time, 860) row decoding entangles 1 error statistics; In like manner obtaining BCH(900 for the third time, 860) row decoding entangles 0 error statistics signal; BCH(900 for the third time, 860) in row decoding, there are 32 BCH code words, each clock cycle of each BCH code word produces one and can not error correction miss statistical signal, these 32 can not be added by error correction mistake statistical signal, obtaining final BCH(900 for the third time, 860) row decoding can not entangle error statistics.
6. the method for five iterative decodings of super forward error correction as claimed in claim 5, it is characterized in that: step e comprises the following steps: from OTU2 to SFEC mapping process, preserved relevant map information, the relevant information of preserving according to mapping, load data on SFEC relevant position and checking data are write respectively in the payload buffer memory and effect buffer memory of inverse mapping, and then formed the data of OTU2 frame structure.
7. the method for five iterative decodings of the super forward error correction as described in any one in claim 1 to 6, it is characterized in that: the length of the frame interior of SFEC described in steps A is 900 bits, width is 32 bits, there are 32 row, 900 row, each SFEC frame interior takies a block RAM, and the data width of every block RAM is 32 bits, and the address degree of depth is 900 bits.
8. the method for five iterative decodings of the super forward error correction as described in any one in claim 1 to 6, it is characterized in that: in steps A, a row code character comprises 4 row code words, for each row code character, 4 bits of each code word the first row are filled in order, then carry out the filling of next 4 bits, after having filled a row code character in current line code character, refill and join next row code character, the assemble sequence of whole row code character is carried out according to order from left to right, from top to bottom.
9. the method for five iterative decodings of the super forward error correction as described in any one in claim 1 to 6, it is characterized in that: described in step C in five iterative decoding processes, each row decoding is processed 32 row in SFEC frame interior respectively with 32 decoders simultaneously, the degree of parallelism of each decoder is 4, be single treatment 4 Bit datas, need 225 clock cycle to handle the row code word data of 900 bits; Each column decoding adopts 4 decoders 4 row code words to be carried out to decoding processing simultaneously, and the degree of parallelism of each column decoder is 32, i.e. single treatment 32 Bit datas need 16 clock cycle to handle the data of 500 bits.
10. for realizing the device of five iterative decodings of super forward error correction of method described in claim 1 to 9 any one, it is characterized in that: comprise synchronization character analytic unit, frame interior map unit, ram memory cell, five iterative decoding control units, BCH(900, 860) code syndrome computing unit, BCH(900, 860) code BM algorithm unit, BCH(900, 860) code data buffer cell, BCH(900, 860) search of code money and error correction unit, BCH(500, 491) code syndrome computing unit, BCH(500, 491) code data buffer cell, BCH(500, 491) search of code money and error correction unit, frame interior inverse mapping unit and decoding performance monitoring unit, wherein:
Synchronization character analytic unit, for: extract the synchronization character information of OTU2 frame data relevant position and analyze, the SFEC frame interior parameter obtaining being passed to frame interior mapping block simultaneously;
Frame interior map unit, for: by the data-mapping of OTU2 frame format, be the data of SFEC frame interior form;
Ram memory cell, for: deposit in order the SFEC frame interior data of having shone upon in RAM, and carry out read-write operation according to the instruction of five iterative decoding control units and frame interior inverse mapping unit;
Five iterative decoding control units, be used for: control SFEC frame interior data and carry out in order three row decodings and twice column decoding, the order of five iterative decodings is: BCH(900 for the first time, 860) row decoding, BCH(500 for the first time, 491) column decoding, BCH(900 for the second time, 860) row decoding, BCH(500 for the second time, 491) column decoding, BCH(900 for the third time, 860) row decoding, data for optional position, only, after previous decoding completes, just can carry out decoded operation next time;
BCH(900,860) code syndrome computing unit, for: complete BCH(900,860) calculating of 8 syndromes of code;
BCH(900,860) code BM algorithm unit, for: according to the BCH(900 having obtained, 860) value of code syndrome, solve the expression formula of error location polynomial, obtain the root of error location polynomial;
BCH(900,860) code data buffer cell, for: data to decode is put into buffer memory, then postpones certain umber of beats and send into BCH(900,860) code money searches for and error correction unit is carried out correction process;
BCH(900,860) search of code money and error correction unit, for: solve BCH(900,860) root of the error location polynomial that code BM algorithm unit obtains, orient each BCH(900,860) wrong element position in code word, thus complete the error correction of the wrong code element in code word;
BCH(500,491) code syndrome computing unit, for: complete BCH(500,491) calculating of code syndrome, obtain BCH(500,491) code syndrome;
BCH(500,491) code data buffer cell, for: data to decode is put into buffer memory, then postpones certain umber of beats and send into BCH(500,491) code money searches for and error correction unit is carried out correction process;
BCH(500,491) search of code money and error correction unit, be used for: utilize BCH(500,491) BCH(500 that code syndrome computing unit calculates, 491) code syndrome, orient each BCH(500,491) wrong element position in code word, thus complete the error correction of the wrong code element in code word;
Frame interior inverse mapping unit, for: realize data flow from SFEC frame interior to the format conversion OTU2 frame, be about to the OTU2 frame structure data of SFEC frame interior structured data in being converted to G.975;
Decoding performance monitoring unit, for: the performance monitoring function that completes five iterative decodings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310491546.7A CN103560797B (en) | 2013-10-18 | 2013-10-18 | Method and the device of five iterative decodings of super forward error correction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310491546.7A CN103560797B (en) | 2013-10-18 | 2013-10-18 | Method and the device of five iterative decodings of super forward error correction |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103560797A true CN103560797A (en) | 2014-02-05 |
| CN103560797B CN103560797B (en) | 2016-05-25 |
Family
ID=50014974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310491546.7A Active CN103560797B (en) | 2013-10-18 | 2013-10-18 | Method and the device of five iterative decodings of super forward error correction |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103560797B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103944589B (en) * | 2014-04-30 | 2017-02-15 | 中国科学院微电子研究所 | BCH encoding and decoding method and device |
| CN109728875A (en) * | 2017-10-31 | 2019-05-07 | 深圳市中兴微电子技术有限公司 | A kind of BCH coding/decoding method and device |
| CN112054809A (en) * | 2020-08-28 | 2020-12-08 | 杭州华澜微电子股份有限公司 | Improved TPC error correction algorithm and apparatus |
| CN116192661A (en) * | 2023-04-26 | 2023-05-30 | 苏州联讯仪器股份有限公司 | Stability evaluation method, device and equipment of communication module and readable storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1411235A (en) * | 2002-12-06 | 2003-04-16 | 清华大学 | Method for enhancing product code decoding speed and decoding device |
| US20100275104A1 (en) * | 2009-04-28 | 2010-10-28 | Mitsubishi Electric Corporation | Error correcting device and error correcting method |
| CN102170327A (en) * | 2011-04-06 | 2011-08-31 | 烽火通信科技股份有限公司 | Super forward error correction hardware decoding method and apparatus thereof |
-
2013
- 2013-10-18 CN CN201310491546.7A patent/CN103560797B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1411235A (en) * | 2002-12-06 | 2003-04-16 | 清华大学 | Method for enhancing product code decoding speed and decoding device |
| US20100275104A1 (en) * | 2009-04-28 | 2010-10-28 | Mitsubishi Electric Corporation | Error correcting device and error correcting method |
| CN102170327A (en) * | 2011-04-06 | 2011-08-31 | 烽火通信科技股份有限公司 | Super forward error correction hardware decoding method and apparatus thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103944589B (en) * | 2014-04-30 | 2017-02-15 | 中国科学院微电子研究所 | BCH encoding and decoding method and device |
| CN109728875A (en) * | 2017-10-31 | 2019-05-07 | 深圳市中兴微电子技术有限公司 | A kind of BCH coding/decoding method and device |
| CN109728875B (en) * | 2017-10-31 | 2021-07-27 | 深圳市中兴微电子技术有限公司 | BCH decoding method and device |
| CN112054809A (en) * | 2020-08-28 | 2020-12-08 | 杭州华澜微电子股份有限公司 | Improved TPC error correction algorithm and apparatus |
| CN116192661A (en) * | 2023-04-26 | 2023-05-30 | 苏州联讯仪器股份有限公司 | Stability evaluation method, device and equipment of communication module and readable storage medium |
| CN116192661B (en) * | 2023-04-26 | 2023-09-29 | 苏州联讯仪器股份有限公司 | Stability evaluation method, device and equipment of communication module and readable storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103560797B (en) | 2016-05-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10673462B2 (en) | Coding method and coding device | |
| CN110235374B (en) | Transmitter, method and non-transitory computer readable storage medium for transmitting encoded codewords | |
| CN105429646B (en) | A kind of encoding and decoding method of tail biting ladder code | |
| US12004240B2 (en) | Forward error correction systems and methods | |
| CN102170327B (en) | Super forward error correction hardware decoding method and apparatus thereof | |
| CN102412847A (en) | Method and apparatus for decoding low density parity check code using united node processing | |
| CN103560797A (en) | Method and device for five times of iterative decoding of superstrong forward error correction | |
| CN101777921B (en) | Structured LDPC code decoding method and device for system on explicit memory chip | |
| US8438448B2 (en) | Decoding method and device for low density generator matrix codes | |
| CN106656205B (en) | Polar code decoding method and system for reducing memory consumption | |
| CN103873071A (en) | Method and device for forward error correction encoding, method and device for forward error correction decoding, and communication device and system | |
| EP2533450B1 (en) | Method and device for data check processing | |
| CN101969311B (en) | High-speed parallel segmented staggering Viterbi decoding method | |
| KR20190111991A (en) | Method and apparatus for processing rate matching of polar code | |
| EP3609082B1 (en) | Array based forward error correction for optical transmission | |
| CN101707510A (en) | High-speed Turbo decoding method and device | |
| CN103220007B (en) | The TPC iterative decoding algorithm of the unreliable figure place of a kind of self-adaptative adjustment subcode | |
| CN102468902B (en) | Method for Turbo coding of rate match/de-rate match in LTE (long term evolution) system | |
| CN107534491A (en) | Apparatus and method for the regeneration network node between the first and second link portions | |
| CN105610550B (en) | A kind of Viterbi interpretation method for power line carrier communication | |
| CN102318249B (en) | An interweaving and deinterleaving method,the interleaver and de-interleaver | |
| US9515683B2 (en) | Forward error correction architecture and implementation for power/space efficient transmission systems | |
| US9236890B1 (en) | Decoding a super-code using joint decoding of underlying component codes | |
| CN102361460B (en) | General high speed parallel cycle interleaving Viterbi decoding method | |
| CN115833993A (en) | oFEC decoding system facing next generation optical fiber communication standard |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170607 Address after: 430074, Hubei Wuhan East Lake Development Zone, Kanto Industrial Park, beacon Road, optical communications building, industrial building, two floor Patentee after: Wuhan flying Microelectronics Technology Co., Ltd. Address before: China Science and Technology Park Dongxin road East Lake Development Zone 430074 Hubei Province, Wuhan City, No. 5 Patentee before: Fenghuo Communication Science &. Technology Co., Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170809 Address after: 430000 East Lake high tech Development Zone, Hubei Province, No. 6, No., high and new technology development zone, No. four Co-patentee after: Wuhan flying Microelectronics Technology Co., Ltd. Patentee after: Fenghuo Communication Science &. Technology Co., Ltd. Address before: 430074, Hubei Wuhan East Lake Development Zone, Kanto Industrial Park, beacon Road, optical communications building, industrial building, two floor Patentee before: Wuhan flying Microelectronics Technology Co., Ltd. |