CN106656205B - Polar code decoding method and system for reducing memory consumption - Google Patents

Polar code decoding method and system for reducing memory consumption Download PDF

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CN106656205B
CN106656205B CN201610878396.9A CN201610878396A CN106656205B CN 106656205 B CN106656205 B CN 106656205B CN 201610878396 A CN201610878396 A CN 201610878396A CN 106656205 B CN106656205 B CN 106656205B
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CN106656205A (en
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权进国
张颢
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Shenzhen Graduate School Tsinghua University
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13Linear codes

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Abstract

A polar code decoding method and system for reducing memory consumption, the method comprising: partitioning processing of the coding tree: dividing a plurality of blocks, namely subtrees, in the decoding tree, adopting an SCL decoding algorithm in the subtrees, and adopting a standard SC decoding algorithm outside the subtrees; inter-block transfer processing of decoding operation: and arranging the blocks of the decoding tree, indexing the subtrees by the numbers, and then performing SCL decoding on the subtrees one by one according to the time sequence of the decoding operation, wherein the subtrees share a storage space. The method and the system can obviously reduce the consumption of the memory and facilitate the realization of hardware.

Description

Polar code decoding method and system for reducing memory consumption
Technical Field
The invention belongs to the field of optical communication, and particularly relates to a polar code decoding method and system for reducing memory consumption in optical channel transmission.
Background
The broadband optical network is an important basis for the development of the national economic society and is an important link for the integration of the national industrialization and the informatization,
with the emergence of emerging services such as video interaction and point-to-point file transmission in recent years, the demand of users on optical network bandwidth is also increasing. Currently, the world is in the transition from low speed 10G/40G to high speed 100G, and European and American operators have developed 100G commercial network construction. The domestic China telecom, China Mobile and China Unicom have started the laboratory test of 100G successively. Therefore, 100Gbit/s optical communication systems are already at the beginning of large-scale commercial deployment.
The first strict proof of the polarization code appeared in 2008 theoretically is that the polarization code can "reach" shannon capacity under the binary input symmetric discrete memoryless channel, and has lower encoding and decoding complexity. In a sense, the polar code theoretically solves the problem that the information theory and coding field always wants to solve in the last 60 years. Although the theory of the polar code is elegant, the practical performance of the polar code is not ideal, and although the polar code performance is improved with the proposal of technologies such as a sequential cancellation Decoding algorithm (SCL) Decoding), the Decoding algorithm needs a large amount of memory to store intermediate results, which is not favorable for the hardware implementation of Decoding.
Disclosure of Invention
The invention aims to provide a polar code decoding method and a polar code decoding system, which reduce the consumption of a memory and facilitate the realization of hardware.
In order to achieve the purpose, the invention adopts the following technical scheme:
a polar code decoding method for reducing memory consumption comprises the following steps:
partitioning processing of the coding tree: dividing a plurality of blocks, namely subtrees, in the decoding tree, adopting an SCL decoding algorithm in the subtrees, and adopting a standard SC decoding algorithm outside the subtrees;
inter-block transfer processing of decoding operation: and arranging the blocks of the decoding tree, indexing the subtrees by the numbers, and then performing SCL decoding on the subtrees one by one according to the time sequence of the decoding operation, wherein the subtrees share a storage space.
Further:
according to the partitioning of the decoding tree, only SCL decoding operation is carried out on each subtree, a plurality of decoding paths are reserved for final selection, and standard SC decoding operation is carried out on other parts except the subtree, and only local optimal decoding paths are reserved.
The list length and number of partitions decoded by the SCL are selected according to decoder performance requirements and hardware resources.
The block structure of the polar code SCL decoding tree comprises:
a root node of the decoding tree, which is the start of all decoding paths, from which decoding information is transmitted;
aiming at the block of the first layer decoding result 0, each layer of decoding in the block adopts an SCL decoding method, L decoding paths are reserved, and finally, the path meeting the CRC condition or the path with the highest path metric is output; the decoding of the block is performed first;
for the block of the first layer decoding result 1, each layer of decoding in the block adopts an SCL decoding method, and L decoding paths are reserved. Finally outputting the path meeting the CRC condition or the path with the highest path metric; the decoding of the block is performed later.
The decoding process comprises the following steps:
step 301, reading data to be decoded;
step 302, performing SC decoding on the first bit, and storing the obtained result in a root node of a decoding tree;
step 303, setting the number of the blocks to be 2 and setting a block counter to be 0;
step 304, judging whether the block counter reaches the block number, if so, turning to step 308, and if not, turning to step 305;
305, selecting blocks according to the value of the block counter, and entering intra-block decoding, wherein the intra-block decoding adopts an SCL (service level circle) decoding method, and a plurality of decoding paths are reserved for final decision;
step 306, sending the finally selected decoding path to a CRC check module, if the check is passed, taking the decoding path as a decoding result, and if the check is not passed, taking the path with the highest path metric as a result to be output;
step 307, storing the decoding path result of the block; go to step 304;
and step 308, outputting a final decoding result.
The block structure of the polar code SCL decoding tree comprises:
a root node of the decoding tree, which is the start of all decoding paths, from which decoding information is transmitted;
decoding a second layer node of the decoding tree, wherein the decoding of the node adopts an SC method, only a decoding path with the highest LLR is reserved, and the decoding path is transmitted to a lower layer;
aiming at the block of the decoding result 0 of the first node of the second layer, each layer of decoding in the block adopts an SCL method, L decoding paths are reserved, and finally, the path meeting the CRC condition or the path with the highest path metric is output; the decoding of the block is performed first; then SCL decoding of each block is carried out according to time sequence;
aiming at the block of the decoding result 1 of the last node of the second layer, each layer of decoding in the block adopts an SCL method, L decoding paths are reserved, and finally, the path meeting the CRC condition or the path with the highest path metric is output; the decoding of the block is performed last.
The decoding process comprises the following steps:
step 501, reading data to be decoded;
step 502, performing SC decoding on the first bit, and storing the obtained result in a root node of a decoding tree;
step 503, performing SC decoding on the second bit, and storing the obtained result in the root node of the decoding tree; all decoding tree branches are reserved and passed to the lower layer.
Step 504, setting the number of the blocks to be 2 and setting a block counter to be 0;
step 504', judge whether the block counter reaches the number of blocks, if yes, go to step 508, if no, go to step 505;
505, selecting blocks according to the value of the block counter, and entering intra-block decoding, wherein the intra-block decoding adopts an SCL decoding method, and a plurality of decoding paths are reserved for final decision;
step 506, the finally selected decoding path is sent to a CRC check module, if the check is passed, the finally selected decoding path is taken as a decoding result, and if the check is not passed, the path with the highest path metric is taken as a result to be output;
step 507, storing the decoding path result of the block; go to step 504';
and step 508, outputting the final decoding result.
A polar code decoding system that reduces memory consumption, comprising:
a block processing device for a decoding tree: dividing a plurality of blocks, namely subtrees, in the decoding tree, adopting an SCL decoding algorithm in the subtrees, and adopting a standard SC decoding algorithm outside the subtrees;
the inter-block transfer processing device of the decoding operation: and arranging the blocks of the decoding tree, indexing the subtrees by the numbers, and then performing SCL decoding on the subtrees one by one according to the time sequence of the decoding operation, wherein the subtrees share a storage space.
The polar code decoding algorithm of the invention uses a new decoding method of continuous elimination of a block list, because SCL decoding is only carried out in a block, namely a plurality of decoding paths are reserved for final selection, and common SC decoding is only carried out outside the block, only the local optimal decoding path is reserved, meanwhile, the decoding operation in the block is processed according to the time division principle, the storage space of each block can be shared, that is, the storage space does not need to be distributed to the whole decoding tree, and only the storage space needs to be distributed to one block (sub-tree). The polar code decoding algorithm provided by the invention can obviously reduce the consumption of a memory, does not need to additionally increase the complexity of the algorithm, and fully utilizes the parallel characteristic realized by hardware; by selecting the parameters appropriately, better performance than that of the conventional decoding algorithm can be achieved on the premise of lower memory.
Drawings
Fig. 1 shows the structure of a polar code SCL decoding tree;
FIG. 2 is a block diagram of an example of a polar code SCL decoding tree according to an embodiment of the present invention (I);
FIG. 3 is a decoding flow chart of the blocking method (I) according to an embodiment of the present invention;
FIG. 4 is a block diagram of an example of a polar code SCL decoding tree according to another embodiment of the present invention (II);
FIG. 5 is a decoding flow chart of another embodiment of the present invention for the blocking method (II).
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In an embodiment of the present invention, a polar code decoding method for reducing memory consumption includes:
partitioning processing of the coding tree: dividing a plurality of blocks, namely subtrees, in the decoding tree, adopting an SCL decoding algorithm in the subtrees, and adopting a standard SC decoding algorithm outside the subtrees;
inter-block transfer processing of decoding operation: and arranging the blocks of the decoding tree, indexing the subtrees by the numbers, and then performing SCL decoding on the subtrees one by one according to the time sequence of the decoding operation, wherein the subtrees share a storage space.
The decoding operations of the subtrees are performed in chronological order. The memory space is shared among the modules, and the memory consumption is reduced because the modules (subtrees) are smaller and the decoding path is shorter.
Furthermore, according to the partitioning of the decoding tree, only SCL decoding operation is performed on each subtree, a plurality of decoding paths are reserved for final selection, and only locally optimal decoding paths are reserved for standard SC decoding operation on other parts outside the subtree.
In the embodiment of the invention, the length of the list and the number of the blocks can be flexibly selected according to the performance requirement of the decoder and hardware resources.
In the embodiment of the present invention, the blocks of the decoding tree are specially processed for the decoding tree in the list continuous elimination decoding algorithm. Standard CRC-assisted list successive erasure decoding requires the generation of several codebook combinations with higher probability of success and selection of the codebook that meets the CRC constraint. The codebook combination with the highest probability of success is selected in case no codebook meets the CRC constraint. The present invention divides the coding tree into blocks, also called subtrees. SCL decoding operations are performed only on each subtree, while standard SC decoding operations are performed on other parts outside the subtree.
The inter-block transfer of the decoding operation is arranged for the blocks of the decoding tree, the existing blocks are indexed by numbers, and then SCL decoding is carried out on the blocks one by one according to the time sequence relation of the decoding operation.
The sharing of inter-block storage space can save storage space. Because only SCL decoding is carried out in the block, namely, a plurality of decoding paths are reserved for final selection, and only ordinary SC decoding is carried out outside the block, only locally optimal decoding paths are reserved, meanwhile, the decoding operation in the block is processed according to the time division principle, the storage space of each block can be shared, namely, the storage space does not need to be distributed to the whole decoding tree, and only the storage space needs to be distributed to one sub-block (sub-tree).
In various embodiments, the determination of the length of the list and the number of partitions may be determined based on a combination of hardware resources and decoding performance. If the hardware resources are sufficient, larger chunks and longer lists may be selected, whereas smaller chunks and shorter lists may be selected.
Referring to fig. 1, the structure of the polar code SCL decoding tree:
and the node 11: the root node of the decoding tree is the start of all decoding paths from which the decoding information is transmitted.
Path 12: for each non-invalid bit, two different paths are generated, traversing both 0, 1 possibilities, while addressing both different possibilities. A decoded likelihood ratio (LLR) is calculated and passed to the next layer.
And the node 13: the node generated by each layer contains two kinds of information, one is a decoding value, namely 0 or 1; the second is the coding path metric based on LLR computation.
Path 14: to avoid an exponential increase in decoding complexity, only a fixed number of decoding paths are reserved. That is, of all decoding paths, the L paths with the highest metrics are reserved.
Referring to fig. 2, in one embodiment, the partitioning method (I) of the polar code SCL decoding tree is based on the following structure:
node 21, the root node of the decoding tree, is the start of all decoding paths from which the decoding information is sent.
Block 22, block for first layer decoding result 0. Each layer of decoding in the block adopts an SCL decoding method, and L decoding paths are reserved. And finally outputting the path meeting the CRC condition or the path with the highest path metric. The decoding of the block is performed first.
Block 23, block for first layer decoding result 1. Each layer of decoding in the block adopts an SCL decoding method, and L decoding paths are reserved. And finally outputting the path meeting the CRC condition or the path with the highest path metric. The decoding of the block is performed after block 22.
Fig. 3 shows the decoding flow for the blocking method (I) as follows.
Step 301, reading data to be decoded;
step 302, performing SC decoding on the first bit, and storing the obtained result in a root node of a decoding tree;
step 303, setting the number of the blocks to be 2 and setting a block counter to be 0;
step 304, judging whether the block counter reaches the block number, if so, turning to step 308, and if not, turning to step 305;
and 305, selecting the blocks according to the value of the block counter, and entering block internal decoding. The intra-block decoding adopts an SCL decoding method, and a plurality of decoding paths are reserved for final decision;
step 306, sending the finally selected decoding path to a CRC check module, if the check is passed, taking the decoding path as a decoding result, and if the check is not passed, taking the path with the highest path metric as a result to be output;
step 307, store the decoding path result of the block. Go to step 304;
and step 308, outputting a final decoding result.
Referring to fig. 4, the partitioning method (II) of the polar code SCL decoding tree is based on the following structure:
node 41, the root node of the decoding tree, is the start of all decoding paths from which the decoding information is sent.
Node 42, the second layer node of the decoding tree, the decoding of the node adopts SC method, does not maintain multiple decoding paths, only keeps the decoding path with the highest LLR, transmits to the lower layer
And a block 43 for decoding the block of the result 0 for the first node in the second layer. Each layer of decoding in the block adopts an SCL method, and L decoding paths are reserved. And finally outputting the path meeting the CRC condition or the path with the highest path metric. The decoding of the block is performed first. The subsequent SCL decoding of each block is performed in time sequence.
And a module 44 for decoding the block of result 1 for the last node of the second layer. Each layer of decoding in the block adopts an SCL method, and L decoding paths are reserved. And finally outputting the path meeting the CRC condition or the path with the highest path metric. The decoding of the block is performed last.
Fig. 5 shows the decoding flow for the blocking method (II) as follows.
Step 501, reading data to be decoded;
step 502, performing SC decoding on the first bit, and storing the obtained result in a root node of a decoding tree;
step 503, performing SC decoding on the second bit, and storing the obtained result in the root node of the decoding tree; all decoding tree branches are reserved and transmitted to the lower layer;
step 504, setting the number of the blocks to be 2 and setting a block counter to be 0;
step 504', judge whether the block counter reaches the number of blocks, if yes, go to step 508, if no, go to step 505;
and 505, selecting the blocks according to the value of the block counter, and entering into the block for decoding. The intra-block decoding adopts an SCL decoding method, and a plurality of decoding paths are reserved for final decision;
step 506, the finally selected decoding path is sent to a CRC check module, if the check is passed, the finally selected decoding path is taken as a decoding result, and if the check is not passed, the path with the highest path metric is taken as a result to be output;
step 507, storing the decoding path result of the block. Go to step 504';
and step 508, outputting the final decoding result.
In another embodiment, a polar code decoding system for reducing memory consumption includes:
a block processing device for a decoding tree: dividing a plurality of blocks, namely subtrees, in the decoding tree, adopting an SCL decoding algorithm in the subtrees, and adopting a standard SC decoding algorithm outside the subtrees;
the inter-block transfer processing device of the decoding operation: and arranging the blocks of the decoding tree, indexing the subtrees by the numbers, and then performing SCL decoding on the subtrees one by one according to the time sequence of the decoding operation, wherein the subtrees share a storage space.
The foregoing is a more detailed description of the invention in connection with specific/preferred embodiments and is not intended to limit the practice of the invention to those descriptions. It will be apparent to those skilled in the art that various substitutions and modifications can be made to the described embodiments without departing from the spirit of the invention, and these substitutions and modifications should be considered to fall within the scope of the invention.

Claims (5)

1. A polar code decoding method for reducing memory consumption, comprising:
partitioning processing of the coding tree: dividing a plurality of blocks, namely subtrees, in the decoding tree, adopting an SCL decoding algorithm in the subtrees, and adopting a standard SC decoding algorithm outside the subtrees;
inter-block transfer processing of decoding operation: arranging the blocks of the decoding tree, indexing the subtrees by numbers, and then decoding SCL of each subtree one by one according to the time sequence of decoding operation, wherein each subtree shares a storage space;
the first partitioning structure of the polar code SCL decoding tree comprises:
a root node of the decoding tree, which is the start of all decoding paths, from which decoding information is transmitted;
aiming at the block of the first layer decoding result 0, each layer of decoding in the block adopts an SCL decoding method, L decoding paths are reserved, and finally, the path meeting the CRC condition or the path with the highest path metric is output; the decoding of the block is performed first;
aiming at the block of the first layer decoding result 1, each layer of decoding in the block adopts an SCL decoding method, L decoding paths are reserved, and finally, the path meeting the CRC condition or the path with the highest path metric is output; the decoding of the block is performed later;
alternatively, the first and second electrodes may be,
the second partitioning structure of the polar code SCL decoding tree comprises:
a root node of the decoding tree, which is the start of all decoding paths, from which decoding information is transmitted;
decoding a second layer node of the decoding tree, wherein the decoding of the node adopts an SC method, only a decoding path with the highest LLR is reserved, and the decoding path is transmitted to a lower layer;
aiming at the block of the decoding result 0 of the first node of the second layer, each layer of decoding in the block adopts an SCL method, L decoding paths are reserved, and finally, the path meeting the CRC condition or the path with the highest path metric is output; the decoding of the block is performed first; then SCL decoding of each block is carried out according to time sequence;
aiming at the block of the decoding result 1 of the last node of the second layer, each layer of decoding in the block adopts an SCL method, L decoding paths are reserved, and finally, the path meeting the CRC condition or the path with the highest path metric is output; the decoding of the block is performed last.
2. The decoding method according to claim 1, wherein according to the partitioning of the decoding tree, only SCL decoding operation is performed on each subtree, several decoding paths are reserved for final selection, and only locally optimal decoding paths are reserved for standard SC decoding operation on other parts outside the subtree.
3. The decoding method of claim 1 wherein the list length and the number of partitions for SCL decoding are selected based on decoder performance requirements and hardware resources.
4. The coding method according to claim 1, wherein for the first partition structure, the coding process comprises:
step 301, reading data to be decoded;
step 302, performing SC decoding on the first bit, and storing the obtained result in a root node of a decoding tree;
step 303, setting the number of the blocks to be 2 and setting a block counter to be 0;
step 304, judging whether the block counter reaches the block number, if so, turning to step 308, and if not, turning to step 305;
305, selecting blocks according to the value of the block counter, and entering intra-block decoding, wherein the intra-block decoding adopts an SCL (service level circle) decoding method, and a plurality of decoding paths are reserved for final decision;
step 306, sending the finally selected decoding path to a CRC check module, if the check is passed, taking the decoding path as a decoding result, and if the check is not passed, taking the path with the highest path metric as a result to be output;
step 307, storing the decoding path result of the block; go to step 304;
and step 308, outputting a final decoding result.
5. The decoding method according to claim 1, wherein for the second partition structure, the decoding process comprises:
step 501, reading data to be decoded;
step 502, performing SC decoding on the first bit, and storing the obtained result in a root node of a decoding tree;
step 503, performing SC decoding on the second bit, and storing the obtained result in the root node of the decoding tree; all decoding tree branches are reserved and transmitted to the lower layer;
step 504, setting the number of the blocks to be 2 and setting a block counter to be 0;
step 504', judge whether the block counter reaches the number of blocks, if yes, go to step 508, if no, go to step 505;
505, selecting blocks according to the value of the block counter, and entering intra-block decoding, wherein the intra-block decoding adopts an SCL decoding method, and a plurality of decoding paths are reserved for final decision;
step 506, the finally selected decoding path is sent to a CRC check module, if the check is passed, the finally selected decoding path is taken as a decoding result, and if the check is not passed, the path with the highest path metric is taken as a result to be output;
step 507, storing the decoding path result of the block; go to step 504';
and step 508, outputting the final decoding result.
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