CN114188311A - 半导体结构 - Google Patents

半导体结构 Download PDF

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Publication number
CN114188311A
CN114188311A CN202010965238.3A CN202010965238A CN114188311A CN 114188311 A CN114188311 A CN 114188311A CN 202010965238 A CN202010965238 A CN 202010965238A CN 114188311 A CN114188311 A CN 114188311A
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guard ring
semiconductor structure
interposer substrate
redistribution layer
layer
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陈春宏
林明哲
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN202010965238.3A priority Critical patent/CN114188311A/zh
Priority to US17/073,392 priority patent/US11482485B2/en
Publication of CN114188311A publication Critical patent/CN114188311A/zh
Priority to US17/943,215 priority patent/US11699646B2/en
Priority to US18/200,580 priority patent/US20230290719A1/en
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Abstract

本发明公开了一种半导体结构，包括一中介层基底，其包括一上表面及相对于该上表面的一下表面。一护卫环形成在该中介层基底中并且围绕该中介层基底的一元件区。至少一穿硅通孔形成在该中介层基底中，其中该护卫环邻近该上表面的一端部以及该穿硅通孔邻近该上表面的一端部互相齐平。

Description

半导体结构
技术领域
本发明涉及一种半导体结构，特别是涉及一种包括具有电子元件及护卫环的中介层基底的半导体结构。
背景技术
先进半导体技术中，异质整合技术利用中介层来乘载并电连接不同的芯片，可实现更高的速度、更高的频宽及更低的功耗。随着芯片复杂度提升及更小封装尺寸的要求，如何进一步提高整合集成度并减少封装中电子元件之间的信号干扰为本领域重要的课题。
发明内容
本发明的目的在于提供一种改良的半导体结构，可提高整合集成度及降低电子信号干扰。
根据本发明一实施例提供的一种半导体结构，包括一中介层基底，其包括一上表面及相对于该上表面的一下表面。一护卫环形成在该中介层基底中，并且围绕该中介层基底的一元件区。至少一穿硅通孔形成在该中介层基底中，其中该护卫环邻近该上表面的一端部以及该穿硅通孔邻近该上表面的一端部互相齐平。
附图说明
图1为本发明一实施例的半导体结构的部分区域的剖面示意图；
图2为本发明一实施例的半导体结构的中介层基底的部分区域俯视示意图；
图3至图6为本发明一实施例的半导体结构的制作方法的步骤剖面示意图；
图7至图9为本发明一实施例的半导体结构的制作方法的步骤剖面示意图；
图10为本发明一实施例的半导体结构的部分区域的剖面示意图；
图11为本发明一实施例的半导体结构的中介层基底的部分区域俯视示意图。
主要元件符号说明
100 中介层基底
102 上表面
104 下表面
110 元件区
112 电子元件
120 穿硅通孔
130 护卫环
132 辅助护卫环
134 辅助护卫环
136 辅助护卫环
140 第一重布线层
141 介电层
142 导电层
143 第一屏蔽层
150 第二重布线层
151 介电层
152 导电层
153 第二屏蔽层
160 凸块
300 芯片
302 微凸块
100a 前侧
100b 背侧
112' 沟槽
120' 孔洞
130' 沟槽
120a 端部
120b 端部
130a 端部
130b 端部
X 方向
Y 方向
Z 方向
具体实施方式
接下来的详细说明及叙述，参照相关附图所示内容，共同用来说明可依据本发明而具体实行的实施例。这些实施例已提供足够的细节，使此领域中的技术人员能充分了解并具体实行本发明。在不悖离本发明的范围内，可做结构、逻辑和电性上的修改，而应用在其他实施例上。
为了方便说明以及为了使本领域的技术人员能更容易了解本发明，本发明的各附图只是示意图，其详细的比例可依照设计的需求进行调整。在说明中所描述对于图形中相对器件的上下关系，本领域的技术人员应能理解其是指物件的相对位置，都可以翻转而呈现相同的构件，因此，都应同属本说明书所揭露的范围，在此容先叙明。
在本说明书中，「晶片」、「基底」或「基板」意指任何包含一暴露面，可依据本发明实施例所示在其上沉积材料，制作集成电路结构的结构物，例如布线层。需了解的是「基底」包含半导体晶片，但并不限于此。「基底」在制作工艺中也意指包含制作于其上的材料层的半导体结构物。
应当容易理解，本说明书使用的术语例如「在…上」、「在…之上」、「在…上方」「在…下」、「在…之下」、「在…下方」等空间相对术语的含意应以最宽泛的方式解释，使得这些术语不仅意味着「直接在某物上」或「直接在某物下」，而且还包括「在具有中间特征或层的情况下间接在某物上」或「在具有中间特征或层的情况下间接在某物下」的含意。
此外，上述空间相对术语是为了便于描述如附图所示的一个元件或特征与另一个(或多个)元件或特征的关系。除了附图中所示的取向之外，空间相对术语旨在涵盖元件在使用或操作中的不同取向。该元件可以其他方式定向(例如旋转90度或在其他取向)，并且同样可以对应地解释本文使用的空间相关描述词。
图1为根据本发明一实施例的半导体结构的部分区域的剖面示意图。如图1所示，半导体结构包括一中介层基底(interposer substrate)100，其前侧100a具有一上表面102，背侧100b具有一下表面104。上表面102和下表面104相对设置，并且均大致上沿着X方向和Y方向延伸。中介层基底100可包括硅基底或其他合适的半导体基底，但不限于此。中介层基底100定义有至少一元件区110，至少一电子元件112可通过半导体制作工艺形成在元件区110中。电子元件112可包括被动(无源)元件，例如可包括电容、电阻或电感的其中至少一者，但不限于此。在一些实施例中，电子元件112不包括主动(有源)元件，例如不包括晶体管(transistor)。至少一护卫环130形成在中介层基底110中并且围绕着元件区110。
半导体结构还包括至少一穿硅通孔(through silicon via,TSV)120(或称为穿板通孔(through substrate via))形成在中介层基底中100。在一些实施例中，护卫环130的端部130a与穿硅通孔120的端部120a可互相齐平，并且自中介层基底100的上表面102暴露出来。在一些实施例中，护卫环130的端部130b与穿硅通孔120的端部120b可互相齐平，并且自中介层基底100的下表面104暴露出来。
在一些实施例中，半导体结构可包括一第一重布线层140形成在中介层基底100的上表面102上，以及一第二重布线层150形成在中介层基底100的下表面104上。第一重布线层140和第二重布线层150分别包括至少一介电层(例如介电层141、151)以及至少一导电层(例如导电层142、152)。导电层可包括用于水平方向(例如位于XY平面的方向)电连接的导电线路及用于垂直方向(例如Z方向)电连接的导电孔。导电层还可包括用于设置凸块(bump)的凸块垫(bump pad)。第一重布线层140和第二重布线层150的介电层可包括无机介电材料例如氧化硅、氮化硅，或有机介电材料例如聚酰亚胺(polyimide,PI)，但不限于此。导电层可包括金属，例如铝、铜、钨、钛、氮化钛、钽、氮化钽或类似者，但不限于此。第一重布线层140中可包括与电子元件112电连接的导电线路(图未示)。
穿硅通孔120的一端部120a可与第一重布线层140的导电层142电连接，另一端部120b可与第二重布线层150的导电层152电连接，以实现第一重布线层140和第二重布线层150之间的电连接。
在一些实施例中，护卫环130的端部120a可与第二重布线层150电连接。可通过第二重布线层150将护卫环130电连接至一接地电压(或参考电压)，以对元件区110内的电子元件112提供电子屏蔽，降低信号干扰。
在一些实施例中，半导体结构可包括至少一芯片(或管芯)300以面向中介层基底100的上表面102的方式设置在中介层基底100的前侧100a。也就是说，芯片300沿着Z方向设置在中介层基底100的上方，其中Z方向为垂直于X方向和Y方向定义的平面的方向。芯片300可通过微凸块302与第一重布线层140的导电层142电连接。芯片300可为具有特定功能的主动集成电路芯片，例如绘图处理器(GPU)、中央处理器(CPU)、存储器芯片等，但不限于此。
在一些实施例中，半导体结构可包括一电路板(或封装基板)200以面向中介层基底100的下表面104的方式设置在中介层基底100的背侧100b，并通过凸块160与第二重布线层150的导电层152电连接。
需说明的是，图1所示半导体结构的芯片300、中介层基底100、电路板200的配置仅为举例，在其他实施例中也可使管芯(或芯片)以面向中介层基底100的下表面104的方式设置在中介层基底100的背侧100b，或者将电路板以面向中介层基底100的上表面102的方式设置在中介层基底100的前侧100a。
图2为根据本发明一实施例的半导体结构的中介层基底100的部分区域俯视示意图。面向上表面102时，中介层基底100可包括多个元件区110，分别被一封闭式环状的护卫环130连续围绕。护卫环130的形状可据元件区110的形状调整，例如当元件区110为矩形区域时，护卫环130可大致上为矩形环状。在其他实施例中，可根据应用需求将护卫环130设计为圆形环状、椭圆形环状、多边形环状等，但不限于此。
图3至图6为根据本发明一实施例的半导体结构的制作方法的步骤剖面示意图。本实施例中，穿硅通孔120及护卫环130可以是由相同制作工艺同时形成，并且包括相同材料以及相同高度。
请参考图3，首先提供一中介层基底100，其前侧100a具有一上表面102，背侧100b具有一下表面104。中介层基底100定义有至少一元件区110。
请参考图4，接着自中介层基底100的前侧100a在元件区110中形成至少一电子元件112。电子元件112可包括被动元件，例如电容、电阻或电感，但不限于此。电子元件112可以通过现有半导体制作工艺制作，例如光刻、蚀刻、薄膜沉积、化学机械研磨，但不限于此。为了简化说明在此不再赘述。
请参考图5，接着可选择性形成一垫层(图未示)于上表面102上，以保护电子元件112或作为后续研磨制作工艺的停止层，然后自中介层基底100的前侧100a在中介层基底100中形成护卫环130以及穿硅通孔120。举例来说，可通过光刻暨蚀刻制作工艺、激光钻孔或其他合适的方法在中介层基底100中制作距离上表面102一预定深度的穿硅通孔120的孔洞120’及护卫环130的沟槽130’，接着形成导电材料(例如铝、铜、钨、钛、氮化钛、钽、氮化钽等金属或类似的材料)填满孔洞120’及沟槽130’，然后从中介层基底100的前侧100a进行一研磨制作工艺以移除孔洞120’及沟槽130’外多余的导电材料。本实施例中，穿硅通孔120邻近上表面102的端部120a和护卫环130邻近上表面102的端部130a可大致位于同一水平高度且互相齐平。若上表面102上设有垫层(图未示)，穿硅通孔120的端部120a和护卫环130的端部130a可穿过该垫层，自该垫层显露出来。
请继续参考图5。形成护卫环130以及穿硅通孔120之后，接着在中介层基底100的上表面102上形成第一重布线层140。第一重布线层140包含至少一介电层141以及形成在介电层141中的至少一导电层142。穿硅通孔102的端部120a与导电层142电连接。若上表面102和第一重布线层140之间设有垫层(图未示)，垫层内可包括导电孔以将电子元件112电连接至第一重布线层140。
请参考图6，接着从中介层基底100的背侧100b对下表面104进行一研磨制作工艺，以薄化中介层基底100至显露出穿硅通孔120邻近下表面104的端部120b和护卫环130邻近下表面102的端部130b，然后于下表面104上形成第二重布线层150。第二重布线层150包含至少一介电层151以及形成在介电层151中的至少一导电层152。本实施例中，穿硅通孔102的端部120b和护卫环130的端部130b可大致位于同一水平高度上且互相齐平，并且分别与导电层152电连接。后续，可在第二重布线层150上形成多个凸块160，用于将中介层基底100接合至电路板(或封装基板)。
图7至图9为根据本发明另一实施例的半导体结构的制作方法的步骤剖面示意图。本实施例中，护卫环130可与电子元件112通过相同制作工艺同时形成，包括相同材料并延伸至中介层基底100的相同深度处。
请参考图7，首先提供一中介层基底100，其前侧100a具有一上表面102，背侧100b具有一下表面104，并且定义有至少一元件区110。接着自中介层基底100的前侧100a在元件区110内形成电子元件112以及围绕在元件区110外的护卫环130。本实施例中，电子元件112可包括深沟电容(deep trench capacitor,DTC)。形成电子元件112和护卫环130的步骤例如包括通过光刻暨蚀刻制作工艺、激光钻孔或其他合适的方法在中介层基底100中制作距离上表面102一预定深度的电子元件112的沟槽112’及护卫环130的沟槽130’，接着沉积一导电-介电-导电材料迭层填入沟槽112’和沟槽130’内，然后利用图案化制作工艺(例如光刻暨蚀刻制作工艺)移除多余的导电-介电-导电材料迭层。电子元件112及护卫环130的导电材料可包括多晶硅(polysilicon)，或者可包括金属，例如铝、铜、钨、钛、氮化钛、钽、氮化钽或类似者，但不限于此。电子元件112及护卫环130的介电材料可包括氧化硅、氮化硅、或高介电常数(high-k)材料，但不限于此。本实施例中，电子元件112邻近上表面102的端部112a和护卫环130邻近上表面102的端部130a可大致位于同一水平高度上且互相齐平。
请参考图8。形成电子元件112及护卫环130后，接着可选择性形成一垫层(图未示)于上表面102上，以保护电子元件112及护卫环130或作为后续研磨制作工艺的停止层，然后自中介层基底100的前侧100a在中介层基底100中形成穿硅通孔120。形成穿硅通孔120的步骤如前文所述，在此不再重述。后续，再于中介层基底100的上表面102上形成第一重布线层140。若上表面102和第一重布线层140之间设有垫层(图未示)，垫层内可包括导电孔以将电子元件112和护卫环130电连接至第一重布线层140。
请参考图9，接着从中介层基底100的背侧100b对下表面104进行一研磨制作工艺，以薄化中介层基底100至显露出穿硅通孔120邻近下表面104的端部120b，然后于下表面104上形成第二重布线层150，并使穿硅通孔102的端部120b与第二重布线层150的导电层152电连接。后续，可在第二重布线层150上形成多个凸块160，用于将中介层基底100接合至电路板(或封装基板)。在一些实施例中，如图9所示，护卫环130的端部130a可通过第一重布线层140的导电层142而与一穿硅通孔120的端部120a电连接，再通过穿硅通孔120及第二重布线层150电连接至一接地电压或参考电压。
图10为根据本发明一实施例的半导体结构的部分区域的剖面示意图。为了进一步提升对于电子元件112的电子屏蔽效果，本发明的半导体结构还可包括位于第一重布线层140及第二重布线层150中，且对应于电子元件112设置的第一屏蔽层143和第二屏蔽层153。第一屏蔽层143可与导电层142通过相同的制作工艺形成在介电层141中，包括与导电层142相同的材料。第二屏蔽层153可与导电层152通过相同的制作工艺形成在介电层151中，包括与导电层152相同的材料。在一些实施例中，第一屏蔽层143和第二屏蔽层153可分别与护卫环130的端部130a和端部130b电连接，并均电连接至一接地电压或参考电压，以同时提供电子元件112水平方向和垂直方向的电子屏蔽。在一些实施例中，也可选择使第一屏蔽层143及/或第二屏蔽层153电性浮置(floating)。应理解，在其他实施例中，可选择仅在第一重布线层140或第二重布线层150其中一者设置屏蔽层。
图11为根据本发明一实施例的半导体结构的中介层基底100的部分区域俯视示意图。为了进一步提升对于电子元件112的电子屏蔽效果，本发明的半导体结构还可包括位于中介层基底100中并且围绕着护卫环130的至少一个或多个辅助护卫环。如图11所示，中介层基底100中可设有辅助护卫环132、辅助护卫环134和辅助护卫环136，与护卫环130共同构成围绕着元件区110的多层同心环结构。在一些实施例中，辅助护卫环132、辅助护卫环134和辅助护卫环136可分别可为不连续环状。
辅助护卫环132、辅助护卫环134和辅助护卫环136可与护卫环130通过相同制作工艺同时形成，与护卫环130包括相同材料。辅助护卫环132、辅助护卫环134和辅助护卫环136可分别与第一重布线层140及/或第二重布线层150电连接，并连接至一接地电压或参考电压。在一些情况下，也可选择将护卫环130、辅助护卫环132、辅助护卫环134和辅助护卫环136连接至不同的电压，或电性浮置(floating)。此外，本发明可通过调整辅助护卫环的形状和配置，达到缓冲元件区110周围应力的功效。
综上所述，本发明在中介层基底中规划出元件区，用于设置电子元件例如电容、电阻或电感，可提高半导体结构的整合集成度，并通过于中介层基底中形成围绕着元件区的护卫环以对电子元件提供电子屏蔽，可减少电子元件之间的信号干扰。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (15)

1.一种半导体结构，其特征在于，包括
中介层基底，包括上表面及相对于该上表面的下表面；
护卫环，形成在该中介层基底中，并且围绕该中介层基底的元件区；
至少一穿硅通孔，形成在该中介层基底中，其中该护卫环邻近该上表面的端部以及该穿硅通孔邻近该上表面的端部互相齐平。
2.如权利要求1所述的半导体结构，另包括电子元件，形成在该中介层基底的该元件区中。
3.如权利要求2所述的半导体结构，其中该电子元件包括电容、电阻或电感的其中至少一者。
4.如权利要求2所述的半导体结构，其中该电子元件包括深沟电容，该护卫环与该深沟电容由相同材料构成。
5.如权利要求1所述的半导体结构，其中该护卫环与该穿硅通孔由相同材料构成。
6.如权利要求5所述的半导体结构，其中该护卫环的另一端部以及该穿硅通孔的另一端部互相齐平。
7.如权利要求1所述的半导体结构，另包括第一重布线层，设置在该中介层基底的该上表面上，其中该电子元件、该穿硅通孔以及该护卫环分别与该第一重布线层电连接。
8.如权利要求7所述的半导体结构，另包括第一屏蔽层，设置在该第一重布线层中，并且与该护卫环电连接。
9.如权利要求1所述的半导体结构，另包括第二重布线层，设置在该中介层基底的该下表面上，其中该穿硅通孔及该护卫环分别该第二重布线层电连接。
10.如权利要求9所述的半导体结构，另包括第二屏蔽层，设置在该第二重布线层中，并且与该护卫环电连接。
11.如权利要求9所述的半导体结构，另包括多个凸块，设置在该第二重布线层上。
12.如权利要求1所述的半导体结构，其中该护卫环电连接至接地电压。
13.如权利要求1所述的半导体结构，其中该护卫环为封闭式环状。
14.如权利要求1所述的半导体结构，另包括至少一辅助护卫环围绕该护卫环，与该护卫环构成围绕该元件区的多层同心环状结构。
15.如权利要求14所述的半导体结构，其中该至少一辅助护卫环为不连续环状。
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