CN103531562A - Semiconductor packaging structure and lead frame thereof - Google Patents
Semiconductor packaging structure and lead frame thereof Download PDFInfo
- Publication number
- CN103531562A CN103531562A CN201210229726.3A CN201210229726A CN103531562A CN 103531562 A CN103531562 A CN 103531562A CN 201210229726 A CN201210229726 A CN 201210229726A CN 103531562 A CN103531562 A CN 103531562A
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- China
- Prior art keywords
- protuberance
- lead frame
- semiconductor package
- scolder
- chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- Lead Frames For Integrated Circuits (AREA)
- Die Bonding (AREA)
Abstract
The invention provides a semiconductor packaging structure and a lead frame thereof. The semiconductor packaging structure comprises the lead frame, a chip and an adhesive body. The lead frame is provided with a plurality of pins; the pins are provided with first end portions and joining projections; the first end portions are provided with first upper surfaces; the joining projections are integrally formed at the upper surfaces and are provided with ring walls; the chip is disposed above the pins and is provided with a plurality of projection blocks and a plurality of solders; the joining projections are embedded into the solders so as to enable the solders to coat the ring walls of the joining projections; the solders cover the upper surfaces; and the chip and the pins are coated by the adhesive body.
Description
Technical field
The invention relates to a kind of semiconductor package, particularly relevant for a kind of semiconductor package that does not need scaling powder (flux).
Background technology
Existing known semiconductor package utilizes scolder to be electrically connected lead frame and chip, and must add scaling powder in the step of reflow, yet in the step of reflow, if excessively caving in, scolder makes the bond strength of lead frame and chip and electrically reliability reduction, and after reflow, also must remove scaling powder, increase process complexity.
As can be seen here, above-mentioned existing semiconductor package, in structure and use, obviously still has inconvenience and defect, and is urgently further improved.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but have no for a long time applicable design always, by development, completed, and common product does not have appropriate structure to address the above problem, this is obviously the problem that the anxious wish of relevant dealer solves.Therefore how to found a kind of semiconductor package and lead frame thereof of new structure, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Summary of the invention
The object of the invention is to, overcome the defect that existing semiconductor package exists, and a kind of semiconductor package and lead frame thereof of new structure are provided, technical problem to be solved is to be to provide a kind of semiconductor package, is very suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.Its proposition according to the present invention at least comprises: a lead frame, it has a plurality of pins, respectively this pin has a first end, a portion that etches partially and that connects this first end in conjunction with protuberance, this first end has one first upper surface and one first lower surface, this portion of etching partially has one second upper surface and one second lower surface, and this in conjunction with protuberance, is integrally formed at this first upper surface and this has a ringwall in conjunction with protuberance; One chip, it is arranged at described pin top, this chip has a plurality of projections and a plurality of scolder that is formed at described projection, and described combination protuberance is embedded in described scolder so that described scolder is coated the described ringwall of described combination protuberance, and described scolder covers described the first upper surface; And an adhesive body, its coated this chip and described pin, and this adhesive body manifests respectively this first lower surface of this first end.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid semiconductor package, wherein said described combination protuberance separately has a plurality of faying faces, and described projection has a plurality of end faces, and respectively this faying face has one first width, and respectively this end face has one second width, and this first width is not more than this second width.
Aforesaid semiconductor package, the wherein said described faying face described end face of conflicting.
Aforesaid semiconductor package, wherein said its respectively this pin separately there is a connection this etch partially the second end of portion, this portion of etching partially is positioned between this first end and this second end, and this second end has one the 3rd upper surface and one the 3rd lower surface and this adhesive body and appears respectively the 3rd lower surface.
Aforesaid semiconductor package, wherein said this lead frame separately has a knitting layer, and this knitting layer is formed at described the first upper surface, described the first lower surface, described the second upper surface and described the second lower surface.
Aforesaid semiconductor package, wherein said its respectively this scolder have one first height, respectively this projection separately have one second height, this second be highly not less than this first height.
Aforesaid semiconductor package, wherein said its respectively this ringwall be inclined plane.
The object of the invention to solve the technical problems also realizes by the following technical solutions.Its proposition according to the present invention has a plurality of pins, respectively this pin has a first end, a portion that etches partially and that connects this first end in conjunction with protuberance, this first end has one first upper surface and one first lower surface, this portion of etching partially has one second upper surface and one second lower surface, and this in conjunction with protuberance, is integrally formed at this first upper surface and this has a ringwall in conjunction with protuberance.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid lead frame, wherein said its respectively this pin separately there is a connection this etch partially the second end of portion, this portion of etching partially is positioned between this first end and this second end, this second end has one the 3rd upper surface and one the 3rd lower surface.
Aforesaid lead frame, wherein said its separately includes a knitting layer, and this knitting layer is formed at described the first upper surface, described the first lower surface, described the second upper surface and described the second lower surface.
Aforesaid lead frame, wherein said its respectively this ringwall be inclined plane.
The present invention compared with prior art has obvious advantage and beneficial effect.As known from the above, for achieving the above object, a kind of a kind of semiconductor package that provides is provided, it comprises a lead frame, one chip and an adhesive body, this lead frame has a plurality of pins, respectively this pin has a first end, one portion that etches partially and that connects this first end is in conjunction with protuberance, this first end has one first upper surface and one first lower surface, this portion of etching partially has one second upper surface and one second lower surface, this in conjunction with protuberance, is integrally formed at this first upper surface and this has a ringwall in conjunction with protuberance, this chip is arranged at described pin top, this chip has a plurality of projections and a plurality of scolder that is formed at described projection, described combination protuberance is embedded in described scolder so that the described ringwall of the coated described combination protuberance of described scolder, and described scolder covers described the first upper surface, coated this chip of this adhesive body and described pin, and this adhesive body manifests respectively this first lower surface of this first end.
By technique scheme, semiconductor package of the present invention and lead frame thereof at least have following advantages and beneficial effect: because described combination protuberance is integrally formed at described pin, therefore in hot pressing technique, described combination protuberance can directly penetrate described scolder and connect the described projection of this chip, make this lead frame be electrically connected this chip, thereby improve electrical reliability and the bond strength of this lead frame and this chip chamber, can omit the use of scaling powder and the removing of scaling powder to reduce process complexity, and can maintain the jointing altitude of described scolder simultaneously.
In sum, semiconductor package of the present invention comprises a lead frame, one chip and an adhesive body, this lead frame has a plurality of pins, respectively this pin has a first end and in conjunction with protuberance, this first end has one first upper surface, this in conjunction with protuberance, is integrally formed at this first upper surface and this has a ringwall in conjunction with protuberance, this chip is arranged at described pin top, this chip has a plurality of projections and a plurality of scolder, described combination protuberance is embedded in described scolder so that the described ringwall of the coated described combination protuberance of described scolder, and described scolder covers described the first upper surface, coated this chip of this adhesive body and described pin.The present invention is a significant progress in technology, and has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention, and can be implemented according to the content of specification, and for above and other objects of the present invention, feature and advantage can be become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Fig. 1: according to a preferred embodiment of the present invention, a kind of schematic cross-section of semiconductor package.
Fig. 2: according to a preferred embodiment of the present invention, the partial schematic diagram of lead frame in this semiconductor package.
100: semiconductor package 110: lead frame
111: pin 112: first end
112a: the first upper surface 112b: the first lower surface
113: etch partially the 113a of portion: the second upper surface
113b: the second lower surface 114: the second end
114a: the 3rd upper surface 114b: the 3rd lower surface
115: in conjunction with protuberance 115a: ringwall
115b: faying face 116: knitting layer
120: chip 121: projection
121a: end face 122: scolder
130: adhesive body
H1: the first height H 2: the second height
W1: the first width W 2: the second width
Embodiment
For further setting forth the present invention, reach technological means and the effect that predetermined goal of the invention is taked, below in conjunction with accompanying drawing and preferred embodiment, semiconductor package and its embodiment of lead frame, structure, feature and effect thereof to proposing according to the present invention, be described in detail as follows.
Refer to Fig. 1 and Fig. 2, its preferred embodiment of the present invention, a kind of semiconductor package 100 comprises a lead frame 110, one chip 120 and an adhesive body 130, refer to Fig. 2, this lead frame 110 has a plurality of pins 111, respectively this pin 111 has a first end 112, one connects the portion that etches partially 113 of this first end 112, one connects this second end 114 and one that etches partially portion 113 in conjunction with protuberance 115, this etches partially portion 113 between this first end 112 and this second end 114, this first end 112 has one first upper surface 112a and one first lower surface 112b, this etches partially portion 113 and has one second upper surface 113a and one second lower surface 113b, this the second end 114 has one the 3rd upper surface 114a and one the 3rd lower surface 114b, this in conjunction with protuberance 115, is integrally formed at this first upper surface 112a and this has a ringwall 115a in conjunction with protuberance 115, respectively this ringwall 115a is inclined plane, referring again to Fig. 1, this chip 120 is arranged at described pin 111 tops, this chip 120 has a plurality of projections 121 and a plurality of scolder 122 that is formed at described projection 121, respectively this scolder 122 has one first height H 1, respectively this projection 121 has one second height H 2, this second height H 2 is not less than this first height H 1, the described combination protuberance 115 of described pin 111 is embedded in described scolder 122 so that the described ringwall 115a of described scolder 122 coated described combination protuberances 115, and described the first upper surface 112a that described scolder 122 covers described first end 112 is to increase the bond strength of this chip 120 and this lead frame 110 and to improve electrical reliability.
Referring again to Fig. 1, in the present embodiment, described combination protuberance 115 separately has a plurality of faying face 115b, described projection 121 has a plurality of end face 121a, respectively this respectively this faying face 115b in conjunction with protuberance 115 has one first width W 1, respectively this end face 121a has one second width W 2, this first width W 1 is not more than this second width W 2, and the described faying face 115b described end face 121a that conflicts, coated this chip 120 of this adhesive body 130 and described pin 111, and this adhesive body 130 manifests this first lower surface 112b of this first end 112 respectively and the 3rd lower surface 114b of this second end 114 respectively.In addition, in the present embodiment, this lead frame 110 separately has a knitting layer 116, this knitting layer 116 is formed at described the first upper surface 112a, described the first lower surface 112b, described the second upper surface 113a, described the second lower surface 113b, described the 3rd upper surface 114a and described the 3rd lower surface 114b to prevent described pin 111 over oxidations of this lead frame 110, and the material of this knitting layer 116 is nickel/palladium/gold.Object of the present invention is in the technique of this chip 120 of hot pressing and this lead frame 110, by the described combination protuberance 115 that is integrally formed at described pin 111, directly penetrate described scolder 122 and connect the described projection 121 of this chip 120, make this lead frame 110 be electrically connected this chip 120, it can omit the use of scaling powder and the removing of scaling powder to reduce process complexity, in addition, because described combination protuberance 115 has described faying face 115b and fixing height, therefore in hot pressing technique, can maintain the jointing altitude of described scolder 122 and by the conflict described end face 121a of described projection 121 of described faying face 115b, improve electrical reliability and the bond strength of 120 of this lead frame 110 and this chips.
The above, it is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, although the present invention discloses as above with preferred embodiment, yet not in order to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when can utilizing the technology contents of above-mentioned announcement to make a little change or being modified to the equivalent embodiment of equivalent variations, in every case be not depart from technical solution of the present invention content, any simple modification of above embodiment being done according to technical spirit of the present invention, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (11)
1. a semiconductor package, is characterized in that it at least comprises:
One lead frame, it has a plurality of pins, respectively this pin has a first end, a portion that etches partially and that connects this first end in conjunction with protuberance, this first end has one first upper surface and one first lower surface, this portion of etching partially has one second upper surface and one second lower surface, and this in conjunction with protuberance, is integrally formed at this first upper surface and this has a ringwall in conjunction with protuberance;
One chip, it is arranged at described pin top, this chip has a plurality of projections and a plurality of scolder that is formed at described projection, and described combination protuberance is embedded in described scolder so that described scolder is coated the described ringwall of described combination protuberance, and described scolder covers described the first upper surface; And
One adhesive body, its coated this chip and described pin, and this adhesive body manifests respectively this first lower surface of this first end.
2. semiconductor package as claimed in claim 1, it is characterized in that described combination protuberance separately has a plurality of faying faces, described projection has a plurality of end faces, and respectively this faying face has one first width, respectively this end face has one second width, and this first width is not more than this second width.
3. semiconductor package as claimed in claim 2, is characterized in that the described faying face described end face of conflicting.
4. semiconductor package as claimed in claim 1, this etches partially the second end of portion to it is characterized in that respectively separately having a connection by this pin, this portion of etching partially is positioned between this first end and this second end, and this second end has one the 3rd upper surface and one the 3rd lower surface and this adhesive body and appears respectively the 3rd lower surface.
5. semiconductor package as claimed in claim 1, is characterized in that this lead frame separately has a knitting layer, and this knitting layer is formed at described the first upper surface, described the first lower surface, described the second upper surface and described the second lower surface.
6. semiconductor package as claimed in claim 1, is characterized in that respectively this scolder has one first height, and respectively this projection separately has one second height, and this second is highly not less than this first height.
7. semiconductor package as claimed in claim 1, it is characterized in that its respectively this ringwall be inclined plane.
8. a lead frame, it is characterized in that it has a plurality of pins, respectively this pin has a first end, a portion that etches partially and that connects this first end in conjunction with protuberance, this first end has one first upper surface and one first lower surface, this portion of etching partially has one second upper surface and one second lower surface, and this in conjunction with protuberance, is integrally formed at this first upper surface and this has a ringwall in conjunction with protuberance.
9. lead frame as claimed in claim 8, this etches partially the second end of portion to it is characterized in that respectively separately having a connection by this pin, this portion of etching partially is positioned between this first end and this second end, and this second end has one the 3rd upper surface and one the 3rd lower surface.
10. lead frame as claimed in claim 8, is characterized in that it separately includes a knitting layer, and this knitting layer is formed at described the first upper surface, described the first lower surface, described the second upper surface and described the second lower surface.
11. lead frames as claimed in claim 8, is characterized in that respectively this ringwall is inclined plane.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210229726.3A CN103531562B (en) | 2012-07-04 | 2012-07-04 | Semiconductor package and lead frame thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210229726.3A CN103531562B (en) | 2012-07-04 | 2012-07-04 | Semiconductor package and lead frame thereof |
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| Publication Number | Publication Date |
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| CN103531562A true CN103531562A (en) | 2014-01-22 |
| CN103531562B CN103531562B (en) | 2016-07-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201210229726.3A Active CN103531562B (en) | 2012-07-04 | 2012-07-04 | Semiconductor package and lead frame thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538378A (en) * | 2014-12-26 | 2015-04-22 | 江苏长电科技股份有限公司 | Wafer level package structure and technological method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1416595A (en) * | 2000-02-28 | 2003-05-07 | 日立化成工业株式会社 | Wiring beard, semiconductor device, and method of mfg. wiring board |
| CN101044619A (en) * | 2004-10-20 | 2007-09-26 | 皇家飞利浦电子股份有限公司 | Substrate with electric contacts and method of manufacturing the same |
| US20090160039A1 (en) * | 2007-12-20 | 2009-06-25 | National Semiconductor Corporation | Method and leadframe for packaging integrated circuits |
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2012
- 2012-07-04 CN CN201210229726.3A patent/CN103531562B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1416595A (en) * | 2000-02-28 | 2003-05-07 | 日立化成工业株式会社 | Wiring beard, semiconductor device, and method of mfg. wiring board |
| CN101044619A (en) * | 2004-10-20 | 2007-09-26 | 皇家飞利浦电子股份有限公司 | Substrate with electric contacts and method of manufacturing the same |
| US20090160039A1 (en) * | 2007-12-20 | 2009-06-25 | National Semiconductor Corporation | Method and leadframe for packaging integrated circuits |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538378A (en) * | 2014-12-26 | 2015-04-22 | 江苏长电科技股份有限公司 | Wafer level package structure and technological method thereof |
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| Publication number | Publication date |
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| CN103531562B (en) | 2016-07-06 |
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