CN103489909A - 具有空穴复合层的igbt终端结构及其制备方法 - Google Patents

具有空穴复合层的igbt终端结构及其制备方法 Download PDF

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CN103489909A
CN103489909A CN201310422648.3A CN201310422648A CN103489909A CN 103489909 A CN103489909 A CN 103489909A CN 201310422648 A CN201310422648 A CN 201310422648A CN 103489909 A CN103489909 A CN 103489909A
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recombination layer
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CN103489909B (zh
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李泽宏
宋文龙
邹有彪
顾鸿鸣
吴明进
张金平
任敏
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University of Electronic Science and Technology of China
Institute of Electronic and Information Engineering of Dongguan UESTC
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • H01L29/7396Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66325Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333Vertical insulated gate bipolar transistors
    • H01L29/66348Vertical insulated gate bipolar transistors with a recessed gate

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Abstract

具有空穴复合层的IGBT终端结构及其制备方法,属于功率半导体器件技术领域。所述IGBT终端结构是在常规IGBT终端结构的P型等位环中引入空穴复合层(由注入到P型等位环内的碳离子和氧离子经400~550℃温度条件下的退火处理所形成)。空穴复合层的引入可有效降低等位环处的空穴电流密度,减弱器件关断时的电流集中现象,抑制动态雪崩击穿和热击穿,提高IGBT器件的可靠性。由于空穴复合层的引入仅在器件终端的等位环内部,器件正向导通时漂移区的电导调制效应不受影响,因此正向导通压降不会改变。所述制备方法只要增加一张掩膜版进行碳、氧的离子注入,不会增加过多的附加成本。

Description

具有空穴复合层的IGBT终端结构及其制备方法
技术领域
本发明属于功率半导体器件技术领域,涉及绝缘栅双极型晶体管(Insulated Gate BipolarTransistor,IGBT),具体涉及IGBT终端结构。
背景技术
IGBT是一种电压控制的MOS/BJT复合型器件。从结构上,IGBT的结构与VDMOS极为相似,只是将VDMOS的N+衬底调整为P+衬底,但是引入的电导调制效应克服了VDMOS本身固有的导通电阻与击穿电压的矛盾,从而使IGBT同时具有双极型功率晶体管和功率MOSFET的主要优点:输入阻抗高、导通压降低、电流容量大、开关速度快等。正是由于IGBT独特的、不可取代的性能优势使其自推出实用型产品便在诸多领域得到广泛的应用,例如:新能源技术、以动车、高铁为代表的先进交通运输工具、混合动力汽车、办公自动化以及家用电器等领域。
IGBT正向导通时,正的栅极电压使得沟道开启,发射极电子经过沟道流向漂移区,由于集电极正向偏置以及电中性的要求,大量空穴从集电极注入漂移区并和漂移区的电子形成电导调制。正是由于IGBT正向导通时的电导调制效应使得IGBT具有低正向导通压降、高通态电流、低损耗的优点。然而在IGBT关断过程中,当栅极电压减小到低于阈值电压后,沟道截止,发射极电子电流变为零。在广泛应用的感性负载的应用电路中,由于电感电流不能突变,即:流过IGBT的电流不能突变。因此,所有流过IGBT的电流必须由集电极注入漂移区的空穴形成的空穴电流提供。此时,对于IGBT器件的终端区域(如图1所示),漂移区内的大量空穴不能直接从终端浮空的场限环处抽走,而是在终端的等位环处集中,从而在终端的等位环处形成空穴电流的局部积聚效应(如图2所示),导致局部的高压大电流,使器件温度急剧升高,引起器件的动态雪崩击穿和热击穿,使器件烧毁,导致器件的关断失效。
发明内容
为了减小IGBT器件终端等位环处的电流积聚效应,提升IGBT器件的可靠性,本发明提供一种具有空穴复合层的IGBT终端结构。该IGBT终端结构在终端等位环中引入空穴复合层,能够有效降低终端等位环处的空穴电流密度,减弱对应的电流集中现象,抑制由于电流集中引起的动态雪崩击穿和热击穿,提高IGBT器件的可靠性。同时空穴复合层的引入仅在器件终端的等位环内部,正向导通时漂移区的电导调制效应不受影响,因此正向导通压降不会改变。本发明同时提供具有空穴复合层的IGBT终端结构的制备方法。
本发明技术方案如下:
具有空穴复合层的IGBT终端结构,其结构如图3所示,包括与IGBT有源区相连接的IGBT终端结构,所述IGBT终端结构包括N-漂移区7、N型缓冲层8、P+集电区9、金属集电极10、P型等位环12、P型场限环14和N+截止环20;其中N型缓冲层8位于N-漂移区7和P+集电区9之间,P+集电区9位于N型缓冲层8和金属集电极10之间;所述P型等位环12位于靠近IGBT有源区的N-漂移区7中,P型等位环12中具有等位环的P+接触区11,所述等位环的P+接触区11通过金属连线实现与IGBT有源区中金属发射极的等电位连接;所述N+截止环20位于远离IGBT有源区的N-漂移区7中;P型等位环12和N+截止环20之间的N-漂移区7中具有若干P型场限环14;P型等位环12、P型场限环14、N+截止环20和N-漂移区7的表面具有场氧化层16,场氧化层16表面与P型等位环12、P型场限环14和N+截止环20对应的位置处分别具有金属场板13、15、18和19;在所述P型等位环12内还具有空穴复合层21,所述空穴复合层21由注入到P型等位环12内的碳(C)离子和氧(O)离子经400~550℃温度条件下的退火处理所形成。
本发明同时提供具有空穴复合层的IGBT终端结构的制备方法,包括如下工艺步骤:在IGBT制造工艺中终端N-漂移区7中硼注入与推阱分别形成P型等位环12、P型场限环14和N+截止环20后,在P型等位环12内进行碳(C)离子和氧(O)离子注入,然后经400~550℃温度条件下的退火处理形成P型等位环12内的空穴复合层21。在形成P型等位环12内的空穴复合层21后,在进行后续工艺(包括有源区的光刻与栅槽的刻蚀,栅氧化层的生长,N+多晶硅的淀积与光刻,P-基区的自对准硼注入与推阱,N+发射区的砷注入与推阱,防闩锁P+层的硼注入,BPSG的淀积与回流,接触孔的光刻、硼注入与退火,正面铝层的淀积与光刻,背面减薄,背面金属化等。)
在空穴复合层的具体制作工艺方面,在以80~120KeV能量、1E15~4E15cm-2剂量进行硼注入,形成等位环与场限环后,在硅片水平放置的条件下分别向等位环内部离子注入碳离子和氧离子(如图4所示),其中碳离子注入的能量和剂量分别为:40~60KeV、1E12~3E12cm-2,氧离子注入的能量和剂量分别为:50~70KeV、2E12~6E12cm-2。然后在400~550℃条件下进行退火。
关于碳、氧的离子的具体注入能量与剂量、退火温度,需根据IGBT器件的实际设计要求进行合理的优化与选取,以期达到最理想的效果。
本发明的工作原理:
对于传统的IGBT终端结构(如图1所示),在IGBT关断时,漂移区内的大量空穴不能直接从终端浮空的场限环处抽走,而是在终端的等位环处集中,从而在终端的等位环处形成空穴电流的局部积聚效应(如图2所示),导致局部的高压大电流,使器件温度急剧升高,引起器件的动态雪崩击穿和热击穿,使器件烧毁,导致器件的关断失效。本发明提供的具有空穴复合层的IGBT终端结构,基于传统的IGBT终端结构,在形成等位环与场限环后,在硅片水平放置的条件下分别向等位环内部离子注入碳、氧(如图4所示),然后进行低温退火。作为非导电杂质的碳、氧,在硅晶格间进行耦合,形成空穴复合层,即为图3中的编号21所指的部分。在IGBT关断过程中,漂移区内存储的大量空穴由于不能直接从浮空的场限环处抽取,将在等位环处集中,并从等位环的P+接触区引出,从而形成空穴电流积聚。等位环处积聚的大量空穴被抽取并经过空穴复合层的过程中,一部分空穴被复合消失,从而有效降低此处的空穴电流密度,减弱对应的电流集中现象,抑制由于电流集中引起的动态雪崩击穿和热击穿,提高了IGBT器件的可靠性。
综上所述,本发明提供的具有空穴复合层的IGBT终端结构。该IGBT终端结构在终端等位环中引入空穴复合层,能够有效降低终端等位环处的空穴电流密度,减弱对应的电流集中现象,抑制由于电流集中引起的动态雪崩击穿和热击穿,提高IGBT器件的可靠性。同时空穴复合层的引入仅在器件终端的等位环内部,正向导通时漂移区的电导调制效应不受影响,因此正向导通压降不会改变。此外,本发明提出的具有空穴复合层的IGBT终端结构对应的制作方法,只要增加一张掩膜版进行碳、氧的离子注入,在尽量降低新增工艺步骤带来的附加成本条件下,可以获得最佳的IGBT器件可靠性改善作用。
附图说明
图1是传统IGBT终端结构示意图。
图2是传统IGBT终端结构的空穴电流分布示意图。
图3是提出的一种IGBT终端结构示意图。
图4是提出的一种IGBT终端结构的离子注入空穴复合层示意图。
图1至图4中:包括1为栅极,2为发射极,3为N+区,4为P+区,5为P-基区,6为N+多晶硅,7为N-漂移区,8为N型缓冲层,9为P+集电区,10为金属集电极,11为等位环的P+接触区,12为P型等位环,14为P型场限环,16为场氧化层,13、15、18、19为金属场板,20为N+截止环,21为空穴复合层,22、23为阱氧化层。
具体实施方式
具有空穴复合层的IGBT终端结构,其结构如图3所示,包括与IGBT有源区相连接的IGBT终端结构,所述IGBT终端结构包括N-漂移区7、N型缓冲层8、P+集电区9、金属集电极10、P型等位环12、P型场限环14和N+截止环20;其中N型缓冲层8位于N-漂移区7和P+集电区9之间,P+集电区9位于N型缓冲层8和金属集电极10之间;所述P型等位环12位于靠近IGBT有源区的N-漂移区7中,P型等位环12中具有等位环的P+接触区11,所述等位环的P+接触区11通过金属连线实现与IGBT有源区中金属发射极的等电位连接;所述N+截止环20位于远离IGBT有源区的N-漂移区7中;P型等位环12和N+截止环20之间的N-漂移区7中具有若干P型场限环14;P型等位环12、P型场限环14、N+截止环20和N-漂移区7的表面具有场氧化层16,场氧化层16表面与P型等位环12、P型场限环14和N+截止环20对应的位置处分别具有金属场板13、15、18和19;在所述P型等位环12内还具有空穴复合层21,所述空穴复合层21由注入到P型等位环12内的碳(C)离子和氧(O)离子经400~550℃温度条件下的退火处理所形成。
本发明同时提供具有空穴复合层的IGBT终端结构的制备方法,包括如下工艺步骤:在IGBT制造工艺中终端N-漂移区7中硼注入与推阱分别形成P型等位环12、P型场限环14和N+截止环20后,在P型等位环12内进行碳(C)离子和氧(O)离子注入,然后经400~550℃温度条件下的退火处理形成P型等位环12内的空穴复合层21。在形成P型等位环12内的空穴复合层21后,在进行后续工艺(包括有源区的光刻与栅槽的刻蚀,栅氧化层的生长,N+多晶硅的淀积与光刻,P-基区的自对准硼注入与推阱,N+发射区的砷注入与推阱,防闩锁P+层的硼注入,BPSG的淀积与回流,接触孔的光刻、硼注入与退火,正面铝层的淀积与光刻,背面减薄,背面金属化等。)
在空穴复合层的具体制作工艺方面,在以80~120KeV能量、1E15~4E15cm-2剂量进行硼注入,形成等位环与场限环后,在硅片水平放置的条件下分别向等位环内部离子注入碳离子和氧离子(如图4所示),其中碳离子注入的能量和剂量分别为:40~60KeV、1E12~3E12cm-2,氧离子注入的能量和剂量分别为:50~70KeV、2E12~6E12cm-2。然后在400~550℃条件下进行退火。

Claims (3)

1.具有空穴复合层的IGBT终端结构,其结构包括与IGBT有源区相连接的IGBT终端结构,所述IGBT终端结构包括N-漂移区(7)、N型缓冲层(8)、P+集电区(9)、金属集电极(10)、P型等位环(12)、P型场限环(14)和N+截止环(20);其中N型缓冲层(8)位于N-漂移区(7)和P+集电区(9)之间,P+集电区(9)位于N型缓冲层(8)和金属集电极(10)之间;所述P型等位环(12)位于靠近IGBT有源区的N-漂移区(7)中,P型等位环(12)中具有等位环的P+接触区(11),所述等位环的P+接触区(11)通过金属连线实现与IGBT有源区中金属发射极的等电位连接;所述N+截止环(20)位于远离IGBT有源区的N-漂移区(7)中;P型等位环(12)和N+截止环(20)之间的N-漂移区(7)中具有若干P型场限环(14);P型等位环(12)、P型场限环(14)、N+截止环(20)和N-漂移区(7)的表面具有场氧化层(16),场氧化层(16)表面与P型等位环(12)、P型场限环(14)和N+截止环(20)对应的位置处分别具有金属场板(13、15、18和19);在所述P型等位环(12)内还具有空穴复合层(21),所述空穴复合层(21)由注入到P型等位环(12)内的碳离子和氧离子经400~550℃温度条件下的退火处理所形成。 
2.具有空穴复合层的IGBT终端结构的制备方法,包括如下工艺步骤:在IGBT制造工艺中终端N-漂移区(7)中硼注入与推阱分别形成P型等位环(12)、P型场限环(14)和N+截止环(20)后,在P型等位环(12)内进行碳离子和氧离子注入,然后经400~550℃温度条件下的退火处理形成P型等位环(12)内的空穴复合层(21)。 
3.根据权利要求2所述的具有空穴复合层的IGBT终端结构的制备方法,其特征在于,所述碳离子注入的能量和剂量分别为:40~60KeV、1E12~3E12cm-2,所述氧离子注入的能量和剂量分别为:50~70KeV、2E12~6E12cm-2
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