CN103489874B - Array base palte and preparation method thereof, display unit - Google Patents
Array base palte and preparation method thereof, display unit Download PDFInfo
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- CN103489874B CN103489874B CN201310451037.1A CN201310451037A CN103489874B CN 103489874 B CN103489874 B CN 103489874B CN 201310451037 A CN201310451037 A CN 201310451037A CN 103489874 B CN103489874 B CN 103489874B
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Abstract
The invention provides a kind of array base palte and preparation method thereof, display unit, belong to Display Technique field, it can solve the problem that array base palte manufacturing process is complicated, transmitance is low.Array base palte preparation method of the present invention comprises: by using the patterning processes of ladder exposure to form the figure comprising grid line, grid, gate insulation layer, semiconductor layer, pixel electrode in substrate; Wherein, gate insulation layer does not exceed the top of grid line and grid; The substrate completing abovementioned steps forms separator, forms the source electrode via hole and drain via that are connected with semiconductor layer in the isolation layer, and the first via hole be connected with pixel electrode; The substrate completing abovementioned steps is formed by patterning processes the figure comprising source electrode, drain electrode; Wherein, source electrode, draining is electrically connected with semiconductor layer respectively by source electrode via hole, drain via, drains to be electrically connected with pixel electrode by the first via hole.
Description
Technical field
The invention belongs to Display Technique field, be specifically related to a kind of array base palte and preparation method thereof, display unit.
Background technology
The liquid crystal indicator of TN (twisted-nematic) pattern has fast response time, low cost and other advantages, is a kind of important model of liquid crystal indicator.
As shown in Figure 1, in the array base palte of TN pattern, grid 21/ grid line 22 of thin-film transistor is formed in substrate 9, gate insulation layer 31 cover gate 21/ grid line 22, gate insulation layer 31 is provided with semiconductor layer 41 (semiconductor layer 41 adds that namely ohmic contact layer, transition zone etc. form the active area of thin-film transistor), pixel electrode 11, source electrode 71, drain electrode 72, source electrode 71, drain electrode 72 are electrically connected with semiconductor layer 41, and drain electrode 72 is also electrically connected with pixel electrode 11.Meanwhile, also other structure (not shown)s such as data wire, public electrode wire, alignment film can be provided with in array base palte; And with array base palte on the color membrane substrates of box, be also provided with other structures such as public electrode.
As shown in Figure 1, in the array base palte of existing TN pattern, grid 21/ grid line 22, semiconductor layer 41 pixel electrode 11 need to manufacture in different patterning processes respectively, and being these structures of manufacture at least needs to carry out 3 photoetching, therefore its complicated process of preparation.
Meanwhile, gate insulation layer 31 covers whole substrate 9, and namely gate insulation layer 31 also has distribution at pixel electrode 11 place, and the gate insulation layer 31 of this position can affect printing opacity, thus reduces the transmitance of array base palte.
Summary of the invention
Technical problem to be solved by this invention comprises, and for array base palte complicated process of preparation, the problem that transmitance is low of existing TN pattern, provides array base palte that a kind of preparation technology is simple, transmitance is high and preparation method thereof, display unit.
The technical scheme that solution the technology of the present invention problem adopts is a kind of array base palte preparation method, and it comprises:
Step 1: by using the patterning processes of ladder exposure to form the figure comprising grid line, grid, gate insulation layer, semiconductor layer, pixel electrode in substrate; Wherein, gate insulation layer does not exceed the top of grid line and grid;
Step 2: form separator in the substrate completing abovementioned steps, forms the source electrode via hole and drain via that are connected with semiconductor layer in the isolation layer, and the first via hole be connected with pixel electrode;
Step 3: formed the figure comprising source electrode, drain electrode in the substrate completing abovementioned steps by patterning processes; Wherein, source electrode, draining is electrically connected with semiconductor layer respectively by source electrode via hole, drain via, drains to be electrically connected with pixel electrode by the first via hole.
Wherein, " patterning processes " comprises the step such as formation rete, coating photoresist, exposure, development, etching, stripping photoresist, and it is by unwanted part in above-mentioned steps removing rete, thus makes the remainder of rete form required figure.
Wherein, " ladder exposure " refers to the exposure carrying out in various degree to the diverse location of photoresist layer, thus makes the photoresist layer after development different at the thickness of diverse location, to complete follow-up patterning processes.
In array base palte preparation method of the present invention, grid line/grid, gate insulation layer, semiconductor layer, pixel electrode are being formed with in a patterning processes simultaneously, its needs single exposure (1Mask) technique i.e., therefore its preparation technology is simple, efficiency is high; Meanwhile, because the gate insulation layer of its array base palte does not exceed above grid and grid line, therefore its pixel electrode place does not have gate insulation layer, therefore gate insulation layer can not to light through having an impact, transmitance is high.
Preferably, described step 1 specifically comprises:
Step 11, in substrate, form transparent conductive material layer, insulation material layer, semiconductor material layer, photoresist layer successively;
Step 12, photoresist layer ladder exposed and develops, gate location is made to retain the photoresist layer of the first thickness, grid line position retains the photoresist layer of the second thickness, pixel electrode position retains the photoresist layer of the 3rd thickness, all the other positions are without photoresist layer, wherein the first thickness is greater than the second thickness, and the second thickness is greater than the 3rd thickness;
Step 13, removing are without semiconductor material layer, insulation material layer, the transparent conductive material layer in photoresist region;
The photoresist layer of step 14, removing the 3rd thickness, makes the semiconductor material layer of pixel electrode position expose;
Semiconductor material layer, the insulation material layer of step 15, removing pixel electrode position, form the figure of pixel electrode;
Step 16, removing thickness equal the photoresist layer of grid line position remaining photoresist layer thickness, and the semiconductor layer of grid line position is exposed;
The semiconductor material layer of step 17, removing grid line position, forms the figure of grid line;
Step 18, remove remaining photoresist layer, form the figure of grid, gate insulation layer, semiconductor layer.
Further preferably, described step 17 specifically comprises: the semiconductor material layer of removing grid line position, and removes the insulation material layer of grid line position, forms the figure of grid line.
Further preferably, described step 11 also comprises: form grid metal level at transparent conductive material layer and insulating material interlayer; Described step 13 also comprises: remove the grid metal level without photoresist region; Described step 15 also comprises: the grid metal level of removing pixel electrode position.
Further preferably, described ladder exposure is realized by grayscale mask plate or intermediate tone mask plate.
Preferably, described separator is any one in planarization layer, passivation layer, etching barrier layer.
Further preferably, described separator is planarization layer, and is made up of photosensitive material.
Preferably, described semiconductor layer is made up of metal oxide semiconductor material.
Preferably, described step 3 specifically comprises:
Step 31, formation source and drain metal level;
Step 32, form photoresist layer exposing, retain photoresist layer in separated source electrode position and drain locations, all the other positions are without photoresist layer; Wherein, source electrode position comprises source electrode via hole, and drain locations comprises drain via and the first via hole;
Step 33, removing without the source and drain metal level in photoresist layer region, then remove photoresist layer, the figure of formation source electrode and drain electrode.
The technical scheme that solution the technology of the present invention problem adopts is a kind of array base palte, and it comprises grid, grid line, gate insulation layer, semiconductor layer, pixel electrode, separator, source electrode, drain electrode, and
Described grid, grid line comprise transparent conductive material layer;
Described gate insulation layer does not exceed the top of grid line and grid;
Described separator cover gate, gate insulation layer, semiconductor layer, grid line, pixel electrode;
Described source electrode, drain electrode are positioned at above separator, and are electrically connected with semiconductor layer respectively by the source electrode via hole in separator, drain via; Drain electrode is also electrically connected with pixel electrode by the first via hole in separator.
Array base palte of the present invention can with above-mentioned method manufacture, and therefore its manufacture method is simple, and efficiency is high; Meanwhile, its gate insulation layer does not exceed above grid and grid line, therefore its pixel electrode place does not have gate insulation layer, therefore gate insulation layer can not to light through having an impact, transmitance is high.
Preferably, described gate insulation layer is identical with semiconductor layer figure, and is only positioned at above grid.
Preferably, described grid, grid line also comprise the grid metal level be positioned on transparent conductive material layer.
Preferably, described semiconductor layer is made up of metal oxide semiconductor material.
Preferably, described separator is any one in planarization layer, passivation layer, etching barrier layer.
Further preferably, described separator is planarization layer, and described separator is made up of photosensitive material.
Preferably, described source electrode, drain electrode are positioned on separator.
The technical scheme that solution the technology of the present invention problem adopts is a kind of display unit, and it comprises above-mentioned array base palte.
Because display unit of the present invention comprises above-mentioned array base palte, therefore its preparation technology is simple, efficiency is high, transmitance is high.
Wherein, array base palte preparation method of the present invention, array base palte, display unit are preferably all for liquid crystal display, namely its array base palte is preferably the LCD array substrate of TN type, display unit is preferably the liquid crystal indicator of TN type, but be to be understood that, the present invention also can be used for Organic Light Emitting Diode (OLED) display unit, and the pixel electrode namely in its array base palte can be equivalent to the male or female of Organic Light Emitting Diode.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of existing TN pattern array substrate;
Fig. 2 is the plan structure schematic diagram of array base palte in preparation process of embodiments of the invention 2;
Fig. 3 is the cross-sectional view along AA ' face of Fig. 2;
Fig. 4 is the plan structure schematic diagram of array base palte in preparation process of embodiments of the invention 2;
Fig. 5 is the cross-sectional view along AA ' face of Fig. 4;
Fig. 6 is the plan structure schematic diagram of array base palte in preparation process of embodiments of the invention 2;
Fig. 7 is the cross-sectional view along AA ' face of Fig. 6;
Fig. 8 is the plan structure schematic diagram of array base palte in preparation process of embodiments of the invention 2;
Fig. 9 is the cross-sectional view along AA ' face of Fig. 8;
Figure 10 is the plan structure schematic diagram of array base palte in preparation process of embodiments of the invention 2;
Figure 11 is the cross-sectional view along AA ' face of Figure 10;
Figure 12 is the plan structure schematic diagram of array base palte in preparation process of embodiments of the invention 2;
Figure 13 is the cross-sectional view along AA ' face of Figure 12;
Figure 14 is the plan structure schematic diagram of array base palte in preparation process of embodiments of the invention 2;
Figure 15 is the cross-sectional view along AA ' face of Figure 14;
Figure 16 is the cross-sectional view of array base palte in preparation process of embodiments of the invention 2;
Figure 17 is the cross-sectional view of array base palte in preparation process of embodiments of the invention 2;
Figure 18 is the plan structure schematic diagram of the array base palte of embodiments of the invention 2;
Figure 19 is the cross-sectional view along AA ' face of Figure 18;
Wherein Reference numeral is: 1, transparent conductive material layer; 11, pixel electrode; 2, grid metal level; 21, grid; 22, grid line; 3, insulation material layer; 31, gate insulation layer; 4, semiconductor material layer; 41, semiconductor layer; 5, planarization layer; 51, source electrode via hole; 52, drain via; 53, the first via hole; 7, source and drain metal level; 71, source electrode; 72, drain; 8, photoresist layer; 9, substrate; Q1, gate location; Q2, grid line position; Q3, pixel electrode position; Q4, all the other positions; Q71, source electrode position; Q72, drain locations.
Embodiment
For making those skilled in the art understand technical scheme of the present invention better, below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Embodiment 1:
The present embodiment provides a kind of array base palte preparation method, and it comprises:
Step 1: by using the patterning processes of ladder exposure to form the figure comprising grid line, grid, gate insulation layer, semiconductor layer, pixel electrode in substrate; Wherein, gate insulation layer does not exceed the top of grid line and grid;
Step 2: form separator in the substrate completing abovementioned steps, forms the source electrode via hole and drain via that are connected with semiconductor layer in the isolation layer, and the first via hole be connected with pixel electrode;
Step 3: formed the figure comprising source electrode, drain electrode in the substrate completing abovementioned steps by patterning processes; Wherein, source electrode, draining is electrically connected with semiconductor layer respectively by source electrode via hole, drain via, drains to be electrically connected with pixel electrode by the first via hole.
In the array base palte preparation method of the present embodiment, grid line/grid, gate insulation layer, semiconductor layer, pixel electrode are being formed with in a patterning processes simultaneously, its needs single exposure (1Mask) technique i.e., therefore its preparation technology is simple, efficiency is high; Meanwhile, because the gate insulation layer of its array base palte does not exceed above grid and grid line, therefore its pixel electrode place does not have gate insulation layer, therefore gate insulation layer can not to light through having an impact, transmitance is high.
Embodiment 2:
The present embodiment provides a kind of preparation method of array base palte, and as shown in Fig. 2 to Figure 19, it comprises the following steps:
S101, in substrate 9, form transparent conductive material layer 1, insulation material layer 3, semiconductor material layer 4 successively, and be coated with photoresist layer 8 on semiconductor material layer 4.
Preferably, between transparent conductive material layer 1 and insulation material layer 3, also can form grid metal level 2.
Wherein, transparent conductive material layer 1 is formed by the material of transparent and electrically conductive, such as tin indium oxide (ITO), and it is for the formation of pixel electrode 11, grid 21, grid line 22.
Grid metal level 2 is made up of the metal or alloy such as molybdenum, aluminium usually, is mainly used in jointly forming grid 21, grid line 22 with transparent conductive material layer 1, thus improves the electric conductivity of grid 21, grid line 22.
Obviously, owing to having transparent conductive material layer 1, therefore also can not form grid metal level 2 in theory, and directly form grid 21, grid line 22 with transparent conductive material layer 1.If should be appreciated that in this step and do not form grid metal level 2, then in subsequent step, the operation of " removing grid metal level 2 " is also no longer carried out accordingly.
Insulation material layer 3 can be silicon nitride or silica etc., and it is mainly used in forming gate insulation layer 31, thus makes grid 21 and semiconductor layer 41 insulate and form the moving interface of charge carrier.
Semiconductor material layer 4 is formed by semi-conducting material, and it is mainly used in forming semiconductor layer 41.Preferably, described semiconductor layer 41 (semiconductor material layer 4) is made up of metal-oxide semiconductor (MOS), such as, be oxidized gallium indium zinc (IGZO).
Wherein, substrate 9 also can be pre-formed with the known structure such as resilient coating; Each layer also can adopt other known materials; The method forming each layer can be the known technique such as sputtering, evaporation, chemical vapour deposition (CVD), coating.Because the material, technique, parameter etc. of the various rete of above-mentioned formation are all known, therefore these contents are all not described in detail in the present embodiment.
S102, as shown in Figure 2 and Figure 3, photoresist layer 8 ladder is exposed and developed, the photoresist layer 8 of the first thickness is retained at gate location Q1, grid line position Q2 retains the photoresist layer 8 of the second thickness, pixel electrode position Q3 retains the photoresist layer 8 of the 3rd thickness, all the other positions Q4 is without photoresist layer 8, and wherein the first thickness is greater than the second thickness, and the second thickness is greater than the 3rd thickness.
That is, by carrying out exposure in various degree to the diverse location of photoresist layer 8, make the photoresist layer after development 8 be divided into three kinds of different thickness as shown in Figure 3, also have subregion in addition without photoresist layer 8.
Preferably, ladder exposure realizes by grayscale mask plate or intermediate tone mask plate.
S103, removing, without semiconductor material layer 4, insulation material layer 3, grid metal level 2, the transparent conductive material layer 1 in photoresist region, obtain structure as shown in Figure 4, Figure 5.
That is, by methods such as etchings, removing is without semiconductor material layer 4, insulation material layer 3, grid metal level 2, the transparent conductive material layer 1 of photoresist region Q4 successively, thus is separated with the transparent conductive material layer 1 in other regions by the transparent conductive material layer 1 of pixel electrode area Q1.
Wherein, etching can adopt known method to carry out, and according to the difference of layers of material and etching technics, can be remove multiple rete in once etching, also can be each etching only removing rete simultaneously; Because etching technics, etching parameters etc. are all known, therefore these contents are all not described in detail in the present embodiment.
The photoresist layer 8 of S104, removing the 3rd thickness, makes the semiconductor material layer 4 of pixel electrode position Q3 expose, obtains structure as shown in Figure 6, Figure 7.
That is, by the photoresist layer 8 of ashing (Ashing) technique according to thickness difference removing the 3rd thickness of photoresist layer 8, the photoresist layer 8 of such pixel electrode position Q3 is completely removed, its semiconductor material layer 4 exposes, and the photoresist layer 8 of gate location Q1 and grid line position Q2 is just corresponding thinning, thus obtain structure as shown in Figure 6, Figure 7.
Wherein, due to the characteristic of cineration technics, therefore the photoresist layer 8 area reality of gate location Q1 and grid line position Q2 also can reduce a little, but can not produce materially affect because of it to the structure of final products, therefore not shown.
S105, as shown in Figure 8, Figure 9, semiconductor material layer 4, insulation material layer 3, the grid metal level 2 of removing pixel electrode position Q3, form the figure of pixel electrode 11.
Now, because the photoresist layer 8 of pixel electrode position Q3 is removed, therefore semiconductor material layer 4, insulation material layer 3, the grid metal level 2 of this position is removed successively by etching technics, transparent conductive material layer 1 is exposed, forms the figure of transparent pixels electrode 11.
S106, removing thickness equal the photoresist layer 8 of grid line position Q2 remaining photoresist layer 8 thickness, the semiconductor layer 41 of grid line position Q2 is exposed, obtains structure as shown in Figure 10, Figure 11.
That is, by the remaining photoresist layer 8 (its thickness can equal the second thickness and deduct the 3rd thickness) of cineration technics removing grid line position Q2, the semiconductor layer 41 at this place is exposed, simultaneously, the photoresist layer 8 of gate location Q1 continues thinning, thus obtains structure as shown in Figure 10, Figure 11.
The semiconductor material layer 4 of S107, removing grid line position Q2, and preferably remove the insulation material layer 3 of this position simultaneously, form the figure of grid line 22, obtain structure as shown in Figure 12 and Figure 13.
That is, by semiconductor material layer 4, the insulation material layer 3 of etching technics removing grid line position Q2, grid metal level 2 is exposed, form the figure of grid line 22.
Wherein, in this step, the insulation material layer 3 of grid line position Q2 is also eliminated together, thus there is no gate insulation layer 31 above grid line 22 in final products, the graphs coincide of gate insulation layer 31 and semiconductor layer 41, and be all only positioned at above grid 21; The advantage of this technique is, certain corrosive agent can be selected directly once semiconductor material layer 4 and insulation material layer 3 to be removed, thus Simplified flowsheet.
But, should be appreciated that if in this step, only the semiconductor material layer 4 of removing grid line position Q2, and to retain insulation material layer 3 be also feasible; Like this, in the final product, still have gate insulation layer 31 (but semiconductor layer 41 is only positioned at above grid 21) above grid line 22, this gate insulation layer 31 can increase grid line 22 and data wire spacing, thus the coupling capacitance between both reductions.
Wherein, the present embodiment is what to have the situation of grid metal level 2 be example, and namely its grid line 22 is made up of jointly grid metal level 2 and transparent conductive material layer 1, thus improves the electric conductivity of grid line 22; But should be appreciated that then now grid line position Q2 only remains transparent conductive material layer 1 if do not form grid metal level 2 in step S101, namely grid line 22 also can be directly made up of transparent conductive material.
S108, as shown in Figure 14, Figure 15, remove whole remaining photoresist layer 8, form the figure of grid 21, gate insulation layer 31, semiconductor layer 41.
That is, peel off whole remaining photoresist layer 8 (i.e. the photoresist layer 8 of gate location Q1), semiconductor layer 41 is exposed, form the figure of grid 21, gate insulation layer 31, semiconductor layer 41.
Visible, in the present embodiment, only just prepared the figure of grid line 22/ grid 21, gate insulation layer 31, semiconductor layer 41, pixel electrode 11 by single exposure, therefore its exposure frequency obviously reduces, preparation method is simple, efficiency is high simultaneously.
Meanwhile, in the array base palte of the present embodiment, gate insulation layer 31 does not exceed the top of grid 21 and grid line 22, and namely its pixel electrode 11 place does not have gate insulation layer 31, therefore gate insulation layer 31 can not to light through having an impact, transmitance is high.
S109, as shown in figure 16, forms separator, and forms the source electrode via hole 51 and drain via 52 that are connected with semiconductor layer 41 in the isolation layer, and the first via hole 53 be connected with pixel electrode.
Preferably, described separator can be planarization layer 5, planarization layer 5 is made up of materials such as resins usually, it is except buffer action, the section difference that also structures such as thin-film transistor can be caused " is filled and led up ", make the surface integral of array base palte is tending towards smooth, so that follow-up alignment films even film layer is formed, and be beneficial to the uniform scratch of friction orientation technique.
Certainly, if separator is not planarization layer 5, it also can be the etching barrier layer for preventing semiconductor layer 41 to be etched, or is other structures such as the passivation layer for insulating; Etching barrier layer, passivation layer etc. are formed primarily of the inorganic material such as silicon nitride, silica, and their Thickness Ratio planarization layer 5 is thin, therefore usually do not play a part to eliminate section difference, and only for source electrode 71, drain electrode 72 etc. are separated with other structures.
Concrete, above-mentioned each via hole is formed by patterning processes, can be coated with photoresist on planarization layer 5, carries out successively afterwards exposing, develops, etches, photoresist lift off etc.
Because planarization layer 5 is generally the materials such as resin, and the semiconductor layer 41, pixel electrode 11 etc. below it is the inorganic material such as semiconductor, conductor, the etching selection gender gap of the two is very large, although therefore the hole depth excessively of diverse location is different, also can not produce the destruction to semiconductor layer 41, pixel electrode 11 etc. during etching.
But preferred, also can be that planarization layer 5 is inherently made up of photosensitive material, then now can not be coated with photoresist, but directly planarization layer 5 be exposed, developed, thus form via hole wherein.
In a word, the method forming via hole in planarization layer 5 is known, is not described in detail at this.
S110, formation source and drain metal level 7.
Source and drain metal level 7 is made up of the conducting metal such as molybdenum, aluminium or alloy, for the formation of source electrode 71 and drain electrode 72.
Wherein, due to planarization layer 5 having via hole, therefore source and drain metal level 7 nature can be connected with semiconductor layer 41 with drain via 52 by source electrode via hole 51, and is connected with pixel electrode 11 by the first via hole 53.
S111, form photoresist layer 8 exposing, retain photoresist layer 8 at separated source electrode position Q71 and drain locations Q72, all the other positions are without photoresist layer 8; Wherein, source electrode position Q71 comprises source electrode via hole 51, drain locations Q72 and comprises drain via 52 and the first via hole 53; Obtain the structure as shown in Figure 17,18.
That is, only at the position reservation photoresist layer 8 that finally will form source electrode 71, drain electrode 72, and the photoresist layer 8 of all the other positions is removed, wherein source electrode position Q71 and drain locations Q72 is separated from each other, and source electrode position Q71 is contained source electrode via hole 51, drain locations Q72 and is then contained drain via 52 and the first via hole 53.
Typically, because data wire needs to be connected with source electrode 71, and public electrode wire is parallel and non-intersect with data wire, therefore, preferably can make data wire and public electrode wire and source electrode 71, draining 72 is synchronously formed; Namely when removing photoresist layer 8, also the photoresist layer 8 of linear position data (being connected with source electrode position Q72) is retained, and the photoresist layer 8 of public electrode line position (independent position), thus form data wire and public electrode wire in follow-up etch step simultaneously.
Of course it is to be understood that data wire and/or public electrode wire also can be formed by independent patterning processes in subsequent step, do not limit at this.
The source and drain metal level 7 that S112, removing cover without photoresist, then removes remaining photoresist layer 8, form data wire, public electrode wire (not shown), source electrode 71 and drain 72 figure, obtain structure as shown in figure 19.
That is, the source and drain metal level 7 that etching removing exposes, thus residue two pieces of source and drain metal levels 7 separated, wherein one piece is electrically connected with semiconductor layer 41, is source electrode 71, and semiconductor layer 41 and pixel electrode 11 link together, for draining 72 by another block.
Certainly, if also remain the photoresist layer 8 of linear position data and public electrode line position in S111 step, then can form data wire and public electrode wire in this step simultaneously.
S113, continuation form the structures such as alignment film (not shown), complete the preparation of array base palte.
Embodiment 3:
As shown in Fig. 2 to 19, the present embodiment provides a kind of array base palte, and it comprises grid 21, grid line 22, gate insulation layer 31, semiconductor layer 41, pixel electrode 11, source electrode 71, drain electrode 72, separator.
As shown in figure 19, in the array base palte of the present embodiment, grid 21, grid line 22 comprise transparent conductive material layer 1.
That is, grid 21, the grid line 22 of the array base palte of the present embodiment can be made up of the material of pixel electrode 11, therefore they synchronously can be formed with pixel electrode 11, thus simplify preparation technology.
Preferably, grid 21, grid line 22 also comprise the grid metal level 2 be positioned on transparent conductive material layer 1, and namely grid 21, grid line 22 jointly can be made up of transparent conductive material layer 1 and grid metal level 2, thus strengthen its electric conductivity.
Certainly, can there is no grid metal level 2 in theory yet, and directly form grid 21, grid line 22 with transparent conductive material layer 1.
Wherein, gate insulation layer 31 does not exceed on grid 21 and grid line 22; Therefore, its pixel electrode 11 place does not have gate insulation layer 31, and transmitance is high.
Preferably, gate insulation layer 31 is identical with semiconductor layer 41 figure, and is only positioned at above grid 21.
Because gate insulation layer 31 is identical with semiconductor layer 41 figure, therefore they can be formed in once etching simultaneously, and preparation efficiency is high.
Certainly, gate insulation layer 31 also can be different from semiconductor layer 41 figure, and above grid line 22, also have distribution (semiconductor layer 41 is only positioned at above grid 21), can increase the distance between grid line 22 and data wire like this, the coupling capacitance between both reductions.
Preferably, semiconductor layer 41 is made up of metal oxide semiconductor material.
Wherein, separator cover gate 21, gate insulation layer 31, semiconductor layer 41, grid line 22, pixel electrode 11.
Preferably, separator is planarization layer 5, and namely it is except isolating, the section difference that also can be used for thin-film transistor etc. to cause " is filled and led up ", make the surface integral of array base palte is tending towards smooth, so that follow-up alignment films even film layer is formed, and be beneficial to the uniform scratch of friction orientation technique.
Preferably, above-mentioned planarization layer 5 is made up of photosensitive material, thus need not make with photoresist etc. when forming via hole thereon, and technique is simple.
Preferably, separator also can be the etching barrier layer for preventing semiconductor layer 41 to be etched, or is other structures such as the passivation layer for insulating; Etching barrier layer, passivation layer etc. are formed primarily of the inorganic material such as silicon nitride, silica, and their Thickness Ratio planarization layer 5 is thin, therefore usually do not play a part to eliminate section difference, and only for source electrode 71, drain electrode 72 etc. are separated with other structures.
Source electrode 71, drain electrode 72 are positioned at above planarization layer 5 and (are preferably directly arranged on planarization layer 5), and be electrically connected with semiconductor layer 41 respectively by the source electrode via hole 51 in planarization layer 5 and drain via 52; Meanwhile, drain electrode 72 is also electrically connected with pixel electrode 11 by the first via hole 53 in planarization layer 5, thus semiconductor layer 41 and pixel electrode 11 is linked together.
Certainly, in the array base palte of the present embodiment, also should have other known structure such as data wire, public electrode wire, alignment film (not shown), these structures can be arranged on relevant position as required, as long as data wire finally can be realized to be electrically connected with source electrode, public electrode wire is electrically connected with the public electrode on color membrane substrates, and the present embodiment is not described in detail it.
Embodiment 4:
The present embodiment provides a kind of display unit, and it comprises above-mentioned array base palte.
Display unit due to the present embodiment comprises above-mentioned array base palte, and therefore its preparation technology is simple, efficiency is high, transmitance is high.
The display unit of the present embodiment can be: any product or parts with Presentation Function such as display panels, OLED display panel, Electronic Paper, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
Be understandable that, the illustrative embodiments that above execution mode is only used to principle of the present invention is described and adopts, but the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (9)
1. an array base palte preparation method, is characterized in that, comprising:
Step 1: by using the patterning processes of ladder exposure to form the figure comprising grid line, grid, gate insulation layer, semiconductor layer, pixel electrode in substrate; Wherein, gate insulation layer does not exceed the top of grid line and grid;
Step 2: form separator in the substrate completing abovementioned steps, forms the source electrode via hole and drain via that are connected with semiconductor layer in the isolation layer, and the first via hole be connected with pixel electrode;
Step 3: formed the figure comprising source electrode, drain electrode in the substrate completing abovementioned steps by patterning processes; Wherein, source electrode, draining is electrically connected with semiconductor layer respectively by source electrode via hole, drain via, drains to be electrically connected with pixel electrode by the first via hole.
2. array base palte preparation method according to claim 1, is characterized in that, described step 1 specifically comprises:
Step 11, in substrate, form transparent conductive material layer, insulation material layer, semiconductor material layer, photoresist layer successively;
Step 12, photoresist layer ladder exposed and develops, gate location is made to retain the photoresist layer of the first thickness, grid line position retains the photoresist layer of the second thickness, pixel electrode position retains the photoresist layer of the 3rd thickness, all the other positions are without photoresist layer, wherein the first thickness is greater than the second thickness, and the second thickness is greater than the 3rd thickness;
Step 13, removing are without semiconductor material layer, insulation material layer, the transparent conductive material layer in photoresist region;
The photoresist layer of step 14, removing the 3rd thickness, makes the semiconductor material layer of pixel electrode position expose;
Semiconductor material layer, the insulation material layer of step 15, removing pixel electrode position, form the figure of pixel electrode;
Step 16, removing thickness equal the photoresist layer of grid line position remaining photoresist layer thickness, and the semiconductor layer of grid line position is exposed;
The semiconductor material layer of step 17, removing grid line position, forms the figure of grid line;
Step 18, remove remaining photoresist layer, form the figure of grid, gate insulation layer, semiconductor layer.
3. array base palte preparation method according to claim 2, is characterized in that, described step 17 specifically comprises:
The semiconductor material layer of removing grid line position, and remove the insulation material layer of grid line position, form the figure of grid line.
4. array base palte preparation method according to claim 2, is characterized in that,
Described step 11 also comprises: form grid metal level at transparent conductive material layer and insulating material interlayer;
Described step 13 also comprises: remove the grid metal level without photoresist region;
Described step 15 also comprises: the grid metal level of removing pixel electrode position.
5. array base palte preparation method according to claim 2, is characterized in that,
Described ladder exposure is realized by grayscale mask plate or intermediate tone mask plate.
6. array base palte preparation method according to claim 1, is characterized in that,
Described separator is any one in planarization layer, passivation layer, etching barrier layer.
7. array base palte preparation method according to claim 6, is characterized in that,
Described separator is planarization layer, and is made up of photosensitive material.
8. array base palte preparation method according to claim 1, is characterized in that,
Described semiconductor layer is made up of metal oxide semiconductor material.
9. array base palte preparation method as claimed in any of claims 1 to 8, is characterized in that, described step 3 specifically comprises:
Step 31, formation source and drain metal level;
Step 32, form photoresist layer exposing, retain photoresist layer in separated source electrode position and drain locations, all the other positions are without photoresist layer; Wherein, source electrode position comprises source electrode via hole, and drain locations comprises drain via and the first via hole;
Step 33, removing without the source and drain metal level in photoresist layer region, then remove photoresist layer, the figure of formation source electrode and drain electrode.
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| CN104133313A (en) * | 2014-06-18 | 2014-11-05 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and liquid crystal display device |
| CN105047608B (en) * | 2015-08-26 | 2018-04-03 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
| CN107121832A (en) * | 2017-07-05 | 2017-09-01 | 深圳市华星光电技术有限公司 | Liquid crystal display |
| CN109768070A (en) * | 2019-01-16 | 2019-05-17 | 深圳市华星光电半导体显示技术有限公司 | OLED display panel and preparation method thereof |
| CN109817578A (en) * | 2019-02-27 | 2019-05-28 | 深圳市华星光电半导体显示技术有限公司 | The production method of Organic Light Emitting Diode backboard |
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| CN102842587A (en) * | 2012-09-24 | 2012-12-26 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device |
| CN103137558A (en) * | 2013-02-06 | 2013-06-05 | 京东方科技集团股份有限公司 | Twisted nematic (TN) type array substrate and manufacturing method thereof and display device thereof |
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| CN102842587A (en) * | 2012-09-24 | 2012-12-26 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device |
| CN103137558A (en) * | 2013-02-06 | 2013-06-05 | 京东方科技集团股份有限公司 | Twisted nematic (TN) type array substrate and manufacturing method thereof and display device thereof |
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