CN103390647A - 一种功率mos器件结构 - Google Patents

一种功率mos器件结构 Download PDF

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CN103390647A
CN103390647A CN2012101427490A CN201210142749A CN103390647A CN 103390647 A CN103390647 A CN 103390647A CN 2012101427490 A CN2012101427490 A CN 2012101427490A CN 201210142749 A CN201210142749 A CN 201210142749A CN 103390647 A CN103390647 A CN 103390647A
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metal
ldmos
power mos
mos device
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章舒
何延强
罗泽煌
吴孝嘉
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Wuxi CSMC Semiconductor Co Ltd
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Wuxi CSMC Semiconductor Co Ltd
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Priority to CN2012101427490A priority Critical patent/CN103390647A/zh
Priority to PCT/CN2013/075268 priority patent/WO2013166957A1/zh
Priority to US14/130,483 priority patent/US9356137B2/en
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Abstract

本发明公开了一种功率MOS器件结构，包括多个LDMOS基本单元和多个焊接垫；所述多个LDMOS基本单元并联，并与所述多个焊接垫通过金属电连接，以引出所述多个LDMOS基本单元的栅端、源端、漏端及衬底；其中，所述多个焊接垫正下方设有LDMOS基本单元；所述多个焊接垫包括厚度为3.5um至4.5um、线宽为1.5um至2.5um的单层金属。本发明将功率MOS器件中焊接垫以下的芯片面积充分利用，在不增加芯片总面积的前提下，增加了并联LDMOS基本单元的数量，可有效降低导通电阻。

Description

一种功率 MOS 器件结构
技术领域
本发明涉及一种功率MOS（Power Metal-Oxide-Semiconductor Field-Effect Transistor）的器件结构，尤其涉及一种低导通电阻的功率MOS器件结构，属于半导体器件制造领域。
背景技术
功率MOS器件工作时的漏源导通电阻决定了它的应用功率，当导通电阻很小时，器件就会提供一个很好的开关特性，会有较大的输出电流，从而可以具有更强的驱动能力。尽可能地降低导通电阻，是功率MOS器件所追求的目标。
由导通电阻的计算公式
Figure 713029DEST_PATH_IMAGE001
可得，沟道宽度W越大，导通电阻R越低。因此，功率MOS器件可采用多个LDMOS（Lateral Double-diffused MOS）基本单元并联的方式，实现增加总的沟道宽度，以降低导通电阻。
现有的多个LDMOS基本单元并联的功率MOS器件包括芯片内部器件和芯片外部器件，其中芯片内部器件为多个LDMOS基本单元并联组成；芯片外部器件为位于芯片外部的焊接垫（Bonding PAD）区域。焊接垫是用于对芯片内部器件进行外部连接的部件，通常焊接垫制作在芯片以外区域，其材质可以是铝铜等导电金属，在芯片管芯中所占的面积达到5~20%。图1为现有技术中多个LDMOS基本单元并联的功率MOS器件的版图设计示意图，条状区域代表多个LDMOS基本单元，块状区域代表焊接垫区域。现有的设计中，考虑到封装打线时应力大，容易损伤焊接垫下面的器件，通常不在焊接垫下面放置器件。图2为对应图1的多个LDMOS基本单元并联的功率MOS器件纵向剖面示意图，主要包括多个LDMOS基本单元100和焊接垫区域101，其中上层金属103未被钝化层102覆盖的区域作为焊接垫。
为了进一步降低导通电阻，需要增加LDMOS基本单元的数量，由于现有的方法在Bonding PAD下面不放置器件， LDMOS基本单元的数量越多，器件占用的芯片面积越大，因此成本会越高。
有鉴于此，本发明将提供一种新的功率MOS器件结构，将焊接垫区域面积加以利用，从而可有效降低导通电阻，维持芯片面积不变，也即维持成本不变。
发明内容
本发明要解决的技术问题在于提供一种功率MOS器件结构，可有效降低器件的导通电阻。
为了解决上述技术问题，本发明采用如下技术方案：
一种功率MOS器件结构，包括多个LDMOS基本单元和多个焊接垫；所述多个LDMOS基本单元并联，并与所述多个焊接垫通过金属电连接，以引出所述多个LDMOS基本单元的栅端、源端、漏端及衬底；其特征在于：
所述多个焊接垫正下方设有LDMOS基本单元；所述多个焊接垫包括厚度为3.5um至4.5um、线宽为1.5um至2.5um的单层金属。
作为本发明的优选方案，所述多个焊接垫与所述多个LDMOS基本单元之间设有第一金属层，所述多个LDMOS基本单元、所述第一金属层与所述多个焊接垫之间通过金属栓电连接。
作为本发明的优选方案，所述多个焊接垫包括栅极焊接垫、源极焊接垫、漏极焊接垫以及衬底焊接垫以分别引出并联的所述多个LDMOS基本单元的栅端、源端、漏端及衬底。
作为本发明的优选方案，所述单层金属为铝铜金属或者铝硅铜金属。
作为本发明的优选方案，所述多个焊接垫还包括位于单层金属之下的阻挡层。所述阻挡层包括钛层和氮化钛层，该钛层的厚度为300Å~600Å，该氮化钛层的厚度为300Å~800Å。
作为本发明的优选方案，所述多个焊接垫还包括位于单层金属之上的抗反射层。所述抗反射层包括钛层和氮化钛层，该钛层的厚度为100Å~400Å，该氮化钛层的厚度为250Å~400Å。
作为本发明的优选方案，所述功率MOS器件结构表面覆盖有钝化层，所述钝化层上设有开口以将所述多个焊接垫露出。所述钝化层从下至上依次包括：厚度为1kÅ至2kÅ等离子体富硅氧化膜层、厚度为10kÅ至20kÅ的高密度等离子体二氧化硅膜层以及厚度为7kÅ至11kÅ的等离子体氮化硅膜层。
本发明的有益效果在于：本发明将功率MOS器件中焊接垫以下的芯片面积充分利用，在不增加芯片总面积的前提下，增加了并联LDMOS基本单元的数量，可有效降低导通电阻。其中采用厚金属结构的工艺制作线宽2um下约4um厚的焊接垫，可以缓解应力，避免焊压工艺对器件性能造成影响，保证了器件性能的可靠性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中多个LDMOS基本单元并联的功率MOS器件的版图设计示意图。
图2为现有技术中多个LDMOS基本单元并联的功率MOS器件的局部纵向剖面示意图。
图3为本发明实施例中功率MOS器件的版图设计示意图。
图4为本发明实施例中功率MOS器件的局部纵向剖面示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
正如背景技术部分所述， 现有的功率MOS器件设计中，考虑到封装打线时应力大，容易损伤焊接垫下面的器件，通常不在焊接垫下面放置器件，而是牺牲芯片面积，增加LDMOS基本单元数量，以达到降低导通电阻的目标。然而这种方法制作的功率MOS器件芯片面积大，成本较高。为了减小芯片面积，有效降低导通电阻，发明人设计了一种新的功率MOS器件结构。该结构可充分利用焊接垫下面的芯片面积增加LDMOS基本单元数量，有效降低器件的导通电阻，缩小芯片面积，并且可以保证器件性能的可靠性。下面对该器件结构及相关工艺进行详细的描述。
本发明提供的功率MOS器件结构，包括多个LDMOS基本单元和多个焊接垫；所述多个LDMOS基本单元并联，并与所述多个焊接垫通过金属电连接，以引出所述多个LDMOS基本单元的栅端、源端、漏端及衬底。其中，在所述多个焊接垫的正下方设有LDMOS基本单元；所述多个焊接垫包括厚度为3.5um至4.5um、线宽为1.5um至2.5um的单层金属。
请参考图3所示的版图设计示意图，其中条状区域代表多个LDMOS基本单元，块状区域代表焊接垫区域，在该功率MOS器件结构的设计中，可见与现有的设计（图1所示）不同，在焊接垫的正下方也设有LDMOS基本单元，这样可以利用焊接垫以下的面积增加LDMOS基本单元的数量，降低导通电阻。
请参考图4所示的功率MOS器件的局部纵向剖面示意图。其中标号201为LDMOS基本单元，其上方设有第一金属层202、第二金属层203，第二金属层203上，即该功率MOS器件结构的表面，覆盖有钝化层204，钝化层204上设有开口将第二金属层203的部分区域露出，用作为焊接垫。多个LDMOS基本单元201、第一金属层202与多个焊接垫（第二金属层203）之间通过金属栓205电连接；其中，在焊接垫正下方的LDMOS的各端（源、漏、栅、衬底）,先由202引出到焊接垫以外区域，再由205和203 分别引出到各个焊接垫。通过设计第一金属层202、第二金属层203的图形以及金属栓205的具***置，可以实现所需电路的金属互连，从而并联多个LDMOS基本单元201并引出并联的多个LDMOS基本单元的栅端、源端、漏端及衬底，此为本领域技术人员习知的技术，故此处不再赘述。优选地，所述多个焊接垫可以包括栅极焊接垫、源极焊接垫、漏极焊接垫以及衬底焊接垫以分别引出并联的多个LDMOS基本单元的栅端、源端、漏端及衬底。当然，图4所示的双层金属工艺仅是本发明的一个优选实施例，根据设计的需要也可以采用单层或更多层的金属工艺来实现器件的电路金属互连。
作为本发明的优选方案，用以形成焊接垫的单层金属可以为铝铜金属或者铝硅铜金属。且该焊接垫还可以包括位于该单层金属之下的阻挡层和位于单层金属之上的抗反射层，以提高器件性能。优选地，所述阻挡层可以包括钛层和氮化钛层，该钛层的厚度优选为300Å~600Å，该氮化钛层的厚度优选为300Å~800Å。所述抗反射层可以包括钛层和氮化钛层，该钛层的厚度优选为100Å~400Å，该氮化钛层的厚度优选为250Å~400Å。优选地，所述钝化层从下至上可以依次包括：厚度为1kÅ至2kÅ等离子体富硅氧化膜层、厚度为10kÅ至20kÅ的高密度等离子体二氧化硅膜层以及厚度为7kÅ至11kÅ的等离子体氮化硅膜层。
制作上述功率MOS器件结构可包括如下步骤：
首先制作下层器件单元。采用扩散、薄膜、光刻、腐蚀工艺制作多个LDMOS基本单元。例如，制作NLDMOS基本单元，沟道长度L=1.5+/-0.3um，漂移区长度C=0.8+/-0.2um，栅与漂移区交叠区B=0.5+/-0.1um。下层器件制作完成后，采用金属工艺制作第一金属层、第二金属层、金属栓以形成所需电路。LDMOS基本单元的栅端、源端、漏端及衬底的引出由金属栓连接到第一金属层，再通过金属层间的金属栓和第二金属层连接到外部，如外部的测试衬垫（PAD）上。第二金属层包括用于形成多个焊接垫的部分。在第二金属层上形成钝化层，通过在钝化层上开口使焊接垫露出。
其中第二金属层的制作方法，包括：
厚金属沉积步骤，先后沉积阻挡层、单层金属层和抗反射层，所述单层金属层的厚度为3.5um至4.5um，所述抗反射层包括钛层、氮化钛层；
金属图形化步骤，在所述抗反射层上涂布光刻胶层；利用掩模对所述光刻胶层进行曝光，使所述掩模上的镂空图形对应区域上的光刻胶发生变质；刻蚀去除变质的光刻胶；以剩余光刻胶层为掩模在所述单层金属层上刻蚀出具有凹凸结构的特征尺寸为1.5um至2um的表面图形；
钝化步骤，在上述具有凹凸结构的单层金属层表面制作钝化层，该钝化层半满填充在所述单层金属层的凹凸结构中。
优选地，所述厚金属沉积步骤包括：
在芯片表面先制作阻挡层，所述阻挡层包括钛层和氮化钛层，该钛层的厚度为300Å~600Å，该氮化钛层的厚度为300Å~800Å；在上述阻挡层上制作单层金属层，所述单层金属层为铝铜层或者铝硅铜层；在上述单层金属层上制作抗反射层，所述抗反射层包括钛层和氮化钛层，该钛层的厚度为100Å~400Å，该氮化钛层的厚度为250Å~400Å。
优选地，所述钝化层的制作步骤包括：
在具有凹凸结构的单层金属层表面采用等离子体沉积工艺沉积厚度为1kÅ至2kÅ的等离子体富硅氧化膜层；利用高密度等离子体沉积工艺在上述等离子体富硅氧化膜层表面沉积厚度为10kÅ至20kÅ的高密度等离子体二氧化硅膜层；在上述高密度等离子体二氧化硅膜层上采用等离子体沉积工艺沉积厚度为7kÅ至11kÅ的等离子体氮化硅膜层。
为了验证本方案的可行性，对制作的器件结构进行了测试：
将引出至外部测试PAD的衬底（Sub）和源（Source）端接地，漏端（Drain） 上加0.2V电压，栅端（Gate）从0V扫描到6V，步长为0.1V；测试芯片内漏极焊接垫（Drain）和源极焊接垫（Source）分别接电压V1和V2，外部测试PAD的 Drain端电流为Id。
计算栅端电压Vg=3.6V时器件的导通电阻：。
数据如表1所示，可见明实施例器件结构的导通电阻比现有技术器件结构的导通电阻低23.3%。
Figure 543899DEST_PATH_IMAGE003
综上，本发明的功率MOS器件结构，可以在Bonding PAD下面放置LDMOS基本单元，有效实现芯片面积不变，功率MOS器件结构尺寸不变，Rdson降低23.3%；或者维持导通电阻不变，芯片面积缩小30.4%。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (10)

1.一种功率MOS器件结构，包括多个LDMOS基本单元和多个焊接垫；所述多个LDMOS基本单元并联，并与所述多个焊接垫通过金属电连接，以引出所述多个LDMOS基本单元的栅端、源端、漏端及衬底，其特征在于：
所述多个焊接垫正下方设有LDMOS基本单元；所述多个焊接垫包括厚度为3.5um至4.5um、线宽为1.5um至2.5um的单层金属。
2.根据权利要求1所述的功率MOS器件结构，其特征在于：所述多个焊接垫与所述多个LDMOS基本单元之间设有第一金属层，所述多个LDMOS基本单元、所述第一金属层与所述多个焊接垫之间通过金属栓电连接。
3.根据权利要求1所述的功率MOS器件结构，其特征在于：所述多个焊接垫包括栅极焊接垫、源极焊接垫、漏极焊接垫以及衬底焊接垫以分别引出并联的所述多个LDMOS基本单元的栅端、源端、漏端及衬底。
4.根据权利要求1所述的功率MOS器件结构，其特征在于：所述单层金属为铝铜金属或者铝硅铜金属。
5.根据权利要求1所述的功率MOS器件结构，其特征在于：所述多个焊接垫还包括位于单层金属之下的阻挡层。
6.根据权利要求5所述的功率MOS器件结构，其特征在于：所述阻挡层包括钛层和氮化钛层，该钛层的厚度为300Å~600Å，该氮化钛层的厚度为300Å~800Å。
7.根据权利要求1所述的功率MOS器件结构，其特征在于：所述多个焊接垫还包括位于单层金属之上的抗反射层。
8.根据权利要求7所述的功率MOS器件结构，其特征在于：所述抗反射层包括钛层和氮化钛层，该钛层的厚度为100Å~400Å，该氮化钛层的厚度为250Å~400Å。
9.根据权利要求1所述的功率MOS器件结构，其特征在于：所述功率MOS器件结构表面覆盖有钝化层，所述钝化层上设有开口以将所述多个焊接垫露出。
10.根据权利要求9所述的功率MOS器件结构，其特征在于：所述钝化层从下至上依次包括：厚度为1kÅ至2kÅ等离子体富硅氧化膜层、厚度为10kÅ至20kÅ的高密度等离子体二氧化硅膜层以及厚度为7kÅ至11kÅ的等离子体氮化硅膜层。
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