CN103367411A - 功率半导体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000002093 peripheral effect Effects 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 239000012212 insulator Substances 0.000 abstract 2
- 230000005684 electric field Effects 0.000 description 25
- 238000004088 simulation Methods 0.000 description 5
- 239000012141 concentrate Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000006378 damage Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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Abstract
本发明提供一种功率半导体装置。按照一个实施方式,功率半导体装置设置有半导体衬底、基底层、元件部、保护环和绝缘物质。半导体衬底具有第1导电型的漂移层。基底层具有第2导电型,选择性地形成在漂移层的表面。元件部形成在基底层和漂移层的表面。保护环具有第2导电型,设置了多个保护环,选择性地形成在元件部的周围的漂移层的表面。绝缘物质埋设在保护环中的至少1个保护环中。
Description
本申请基于2012年3月26日申请的先前的日本国专利申请2012-068629号的优先权的利益,并要求该利益,在这里通过引用来包含其全部内容。
技术领域
在此说明的实施方式涉及功率半导体装置。
背景技术
近年来,作为具有高耐压且控制大电流的半导体装置,广泛地使用了IGBT(Insulated Gate Bipolar Transistor,绝缘栅双极型晶体管)。由于IGBT作为开关元件来利用,故需要与用途相对应的耐压。为了得到规定耐压,在将终端部作成保护环状结构的情况下,存在若要提高终端效率就要加长终端长度的问题。此外,为了得到更高的耐压,已知有如下半导体元件:在终端部的上下的面上设置的电极间形成以互相对置的方式在内部延伸的槽栅,以防止耗尽层朝向对置电极的延伸。但是,在终端部设置槽栅结构的半导体元件存在如下问题:结构变得复杂、不容易制造。
发明内容
本发明的目的在于提供能够用更简单的结构得到充分的耐压且制造也容易的半导体元件。
按照一个实施方式,功率半导体装置设置有半导体衬底、基底层、元件部、保护环和绝缘物质。半导体衬底具有第1导电型的漂移层。基底层具有第2导电型,选择性地形成在漂移层的表面。元件部形成在基底层和漂移层的表面。保护环具有第2导电型,设置了多个保护环,选择性地形成在元件部的周围的漂移层的表面。在保护环中的至少一个保护环中埋设有绝缘物质。
本发明能够提供能用更简单的结构得到充分的耐压、制造也容易的半导体元件。
附图说明
图1是第1实施方式的IGBT的俯视图。
图2是沿图1的单点划线A-A′的部分剖面图。
图3是表示IGBT元件的终端部的模拟结构的部分剖面图。
图4是表示图3中表示的IGBT元件的电流ICE(A)的电压-电流特性图。
图5是图3中表示的IGBT元件内部的等电场图。
图6是图3中表示的IGBT元件内部的电流分布图。
图7是表示使槽底面与保护环底面的间隔L发生变化时的IGBT元件的耐压的变化的图。
图8是表示第2实施方式的IGBT元件的概略构成的部分剖面图。
图9是表示第3实施方式的IGBT元件的概略构成的部分剖面图。
具体实施方式
以下一边参照附图一边说明更多的实施例。在附图中,同一符号表示相同或类似的部分。
关于第1实施方式的功率半导体装置,参照附图进行说明。图1是表示除去了作为电力用开关元件的IGBT(绝缘栅双极型晶体管)的发射极电极等电极的衬底表面的图案的概略的俯视图。
如图1所示,对于IGBT11来说,在大致矩形的半导体衬底的中央部形成了矩形的元件部12,在元件部12的周围形成了终端部13。在元件部12内,平行地设置了多条细长的槽栅14。在终端部13中,多条槽栅14形成在元件部12的周围。在终端部13的最外周部,EQPR(Equivalent Potential Ring,等电位环)层16形成为环状。
图2是沿图1的单点划线A-A′的部分剖面图。如图2所示,元件部12是图2的单点划线B-B′的右侧的部分。半导体衬底由p+型集电极层21、n+型缓冲层22和n-型漂移层23构成。依次层叠地形成了p+型集电极层21、n+型缓冲层22和n-型漂移层23。半导体衬底在表面侧具备n-型漂移层23。在n-型漂移层23的表面选择性地形成了p型基底层24。在p型基底层24内形成了从其表面向衬底的深度方向贯通p型基底层24而到达n-型漂移层23内的多个槽栅25。在p型基底层24和n-型漂移层23的表面选择性地形成了元件部12。p+型集电极层21的杂质浓度比p型基底层24高。n+型缓冲层22的杂质浓度比n-型漂移层23高。
槽栅25是在形成在p型基底层24内的槽25-1内经由薄的栅绝缘膜25-2形成了由多晶硅等构成的栅电极25-3而成的。在槽栅25的两侧的p型基底层24的表面,选择性地形成了n型发射极层26。在p型基底层24的表面,设置了与n型发射极层26连接的发射极电极27。在槽栅25的上端部分别配置有绝缘膜28,对槽栅25与发射极电极27进行了绝缘。发射极电极27连接到发射极电极端子E,衬底的最下层的p+型集电极层21连接到集电极电极端子C。各槽栅25的栅电极25-3相互连接而连接到栅电极端子G(未图示)。
终端部13是图2的单点划线B-B′的左侧的部分,设置有保护环31、保护环32和保护环33。保护环31连接到元件部12的p型基底层24,是在元件部12的周围形成为环状的p型的最内周的保护环。保护环32是在保护环31的外侧形成为环状的p型的外周的保护环。保护环33是在保护环32的外侧的最外周形成为环状的p型的最外周的保护环。在保护环31、保护环32和保护环33中,例如利用RIE(Reactive Ion Etching,反应离子刻蚀)分别形成了至少一条以上的槽31-1、槽31-2、槽32-1和槽33-1。在保护环31中设置的槽31-1、槽31-2配置在保护环31的两端部附近。在保护环32中设置的槽32-1配置在保护环32的内周侧的端部附近。在保护环33中设置的槽33-1配置在保护环33的内周侧的端部附近。
在槽31-1、槽31-2、槽32-1和槽33-1中埋置了利用热氧化和CVD(Chemical Vapor Deposition,化学汽相淀积)法形成的由氧化硅膜构成的绝缘物质50。在此,使用了氧化硅膜作为绝缘物质50,但也可以代替地使用非掺杂多晶硅膜、非掺杂非晶硅膜、绝缘性有机膜(例如,聚酰亚胺膜)等。在该情况下,优选在槽的侧面和底面部设置对硅衬底进行热氧化而形成的热氧化硅膜。用绝缘膜34覆盖了形成有保护环31、保护环32和保护环33的n-型基底层23的表面。绝缘膜34在保护环31的附近将发射极电极27与保护环31分离开,在保护环32、保护环33和EQPR层16的上端面除去其一部分,露出保护环33和EQPR层16的上端面。在露出部分分别设置了场板电极35。场板电极35例如是未设定电位的浮动电极。保护环31在没有形成绝缘膜34的部分经由p型基底层24连接到发射极电极27。
如上所述,在保护环31、保护环32和保护环33中分别设置了槽31-1、槽31-2、槽32-1和槽33-1,在槽31-1、槽31-2、槽32-1和槽33-1中分别埋设了绝缘物质50。因此,在本实施方式的IGBT11中,在对集电极-发射极间施加反向偏压时,能够使槽底部周边的电场上升,能够使电场集中点分散,谋求元件耐压的提高。
在本实施方式中,关于元件耐压的提高,通过模拟进行计算,并确认了效果。以下,参照图3至图6说明其细节。
图3是表示IGBT元件的终端部的模拟结构的部分剖面图。图3的A表示以往结构,图3的B表示本实施方式的结构。在图3的A和图3的B中,对于与图2中示出的元件的终端部的结构对应的部分附以对应的符号,省略其详细的说明。
如图3的A和图3的B所示,在IGBT元件的周端部的模拟结构中,从半导体衬底的下侧起,依次层叠地形成了p+型集电极层21、n+型缓冲层22和n-型漂移层23。在n-型漂移层23的表面,在元件部12的周围设置了保护环31、保护环32a、保护环32b和保护环33。保护环31是形成为环状的p型的最内周的保护环。保护环32a和保护环32b是在保护环31的外侧形成为环状的p型的外周的保护环。保护环33是在保护环32a和保护环32b的外侧的最外周形成为环状的最外周的保护环。但是,图3的A和图3的B所示的IGBT元件的周端部的模拟结构与图2所示的IGBT元件的结构相比,其左右都是相反的,在图3的A和图3的B中,右侧为终端部,左侧为元件部(未图示)。
在图3的A所示的IGBT元件的周端部的模拟结构中,在保护环31、保护环32a、保护环32b和保护环33的哪一个中都没有设置图2所示的槽31-1、槽31-2、槽32-1和槽33-1。
在图3的B所示的IGBT元件的周端部的模拟结构中,在保护环31中形成了埋设有绝缘物质的槽31-1和槽31-2(与图2所示的最内周的保护环是同样的)。在保护环32a、保护环32b和保护环33中没有设置槽。
图4是表示IGBT元件的电流ICE(A)的电压-电流特性图。详细地说,是表示在IGBT元件的发射极电极27与p+型集电极层21间(在图3的A和图3的B中表示)施加了反极性的电压VCE(V)的情况下的电流ICE(A)的变化的特性图(电压VCE(V)-电流ICE(A)特性)。虚线A是具有图3的A所示的终端部的IGBT元件的VCE-ICE特性图。实线B是具有图3的B所示的终端部的IGBT元件的VCE-ICE特性图。在用虚线A和实线B表示的电压VCE(V)-电流ICE(A)特性中,随着VCE(V)的增加,ICE(A)也逐渐增加,但若VCE(V)超过元件耐压,则ICE(A)急剧地增加。
从图4示出的特性可知,具有图3的B所示的本实施方式的终端部的IGBT元件与具有图3的A所示的以往的终端部的IGBT元件相比,其耐压提高了。具体地说,在本实施方式的情况下,耐压是758V,与此相对,在以往的情况下,耐压是740V。
图5是图3中示出的IGBT元件内部的等电场图。图5的A是通过模拟求出在对图3的A中示出的IGBT元件施加了与耐压相等的反极性的VCE电压(发射极电极27与p+型集电极层21之间的电压)的状态下、即即将产生雪崩前的状态下的元件内部的电场分布并对其进行了图表化的等电场图。同样,图5的B是通过模拟求出图3的B中示出的即将产生雪崩前的状态下的元件内部的电场分布并对其进行了图表化的等电场图。在图5的A和图5的B中,只示意性地示出了IGBT元件的保护环31、保护环32a、保护环32b和保护环33,在说明方面省略了其它的结构。在图5的A和图5的B中,关于电位,上方是低电位,朝向下方变化为高电位。
若比较图5的A与图5的B,则图5的A的保护环31的底面下方的等电场线集中于保护环31的两端部,在这些部分中形成了电场的峰值,而在中央部分中在底面大致平行地形成。与此相对,图5的B的保护环31的底面下方的等电场线,除了保护环31的两端部以外,
等电场线集中于槽31-1以及槽31-2的正下方,在这些部分中形成了电场的峰值。
图5的C是表示与图5的A以及图5的B对应的电场分布的图。图5的C的纵轴表示电场强度(V/cm2),横轴表示沿IGBT元件的剖面的距离(μm)。图5的C的虚线A是图3的A中示出的以往的IGBT元件的电场分布。图5的C的实线B是图3的B中示出的本实施方式的IGBT元件的电场分布。
如虚线A和实线B所示,在保护环31的底面的两端部,本实施方式的IGBT元件(图3的B中表示)的电场与以往的IGBT(图3的A中表示)的电场相比下降了。而且,在2个槽31-1和槽31-2的正下方形成了电场的峰值。
因而,对本实施方式的IGBT元件(图3的B中表示)来说,通过在保护环31内设置槽31-1和槽31-2,从而使保护环31下方的电场的峰值不仅分散到保护环底面的两端部,而且还分散到中央部。其结果,如图4所示,作为整体,能够提高元件的耐压。在图5的C中示出的电场分布的图中,由表示电场分布的曲线与图的横轴和纵轴所包围的面积表示耐压。在此,若比较由虚线A与图的横轴和纵轴所包围的面积和由实线B与图的横轴和纵轴所包围的面积,则实线B的情况的面积较大。
图6是IGBT元件内部(图3的A中表示)的电流分布图。图6的A是通过模拟求出在施加了与IGBT元件(图3的A中表示)的耐压相等的反极性的VCE电压(发射极电极27与p+型集电极层21之间的电压)的状态下、即即将产生雪崩前的状态下的元件内部的电流分布并对其进行了图表化的电流分布图。同样,图6的B是通过模拟求出施加反极性的VCE电压时的元件内部(图3的B中表示)的电流分布并对其进行了图表化的电流分布图。图6的A和图6的B与图5的A和图5的B同样地,只示意性地示出了IGBT元件的保护环31、保护环32a、保护环32b和保护环33,在说明方面省略了其它的结构。
若比较图6的A和图6的B,则在以往(图6的A中表示)的情况下,集电极-发射极间电流ICE集中于保护环31的外周侧端部。与此相对,在本实施方式(图6的B中表示)的情况下,分散在保护环31的从内周侧端部到中央部的区域。因而,在本实施方式中,电流不集中于一点而是分散,故能够抑制元件的破坏,能够提高元件的耐压。
根据上述的模拟结果,在本实施方式中,通过在保护环中设置埋设了绝缘物质50的槽,从而能够使槽下部周边的电位上升,能够使电场集中点分散,故能够提高耐压。
图7是表示IGBT元件的耐压的变化的图。图7的A是表示对使图7的B所示的槽71的底面与保护环72的底面的间隔L发生变化时的IGBT元件的耐压的变化进行了模拟的结果的图。在图7的A中,实线C是间隔L为0μm时的结果,实线D是间隔L为1μm时的结果,实线E是没有槽的保护环结构时的结果,实线F是间隔L为2μm时的结果。
如图7的A中所示,在间隔L大于等于2μm的情况下,与没有槽的保护环结构(实线E)相比较,IGBT元件的耐压提高,但在小于等于2μm的情况下,IGBT元件的耐压下降了。
关于第2实施方式的功率半导体装置,参照附图进行说明。图8是表示IGBT元件的概略构成的部分剖面图。再有,在图8中,对于与图2示出的第1实施方式的IGBT元件的构成部分对应的构成部分附以同一符号,省略其详细的说明。
如图8所示,在本实施方式的IGBT元件中,在保护环31中设置了槽31-1和槽31-2,但在其它的保护环32和保护环33中没有设置槽。其他的构成与第1实施方式是同样的。
关于第3实施方式的功率半导体装置,参照附图进行说明。图9是表示IGBT元件的概略构成的部分剖面图。再有,在图9中,对于与图2示出的第1实施方式的IGBT元件的构成部分对应的构成部分附以同一符号,省略其详细的说明。
如图9所示,在本实施方式的IGBT元件中,在保护环31中没有设置槽,但在其它的保护环32和保护环33中,设置了槽32-1和槽33-1。其他的构成与第1实施方式是同样的。
在具有上述的实施方式的保护环结构的半导体装置终端中,其特征在于,通过在保护环的内部形成埋入了绝缘物质的槽,从而能够使电场集中点分散,提高耐压,但显然,为了达到这样的目的,也能够使用以上叙述的实施例以外的组合。
在上述的实施方式中,作为功率半导体装置,关于IGBT元件进行了说明,但本发明不限于此,作为功率半导体装置也可适用于功率MOSFET或包含通常的功率半导体装置的MOS型半导体装置。
已说明了本发明的几个实施方式,但这些实施方式是作为例子来提示的,并不打算以此来限定发明的范围。这些新的实施方式可以用其它的各种各样的方式来实施,在不脱离发明的要旨的范围内,能够进行各种省略、替换、变更。这些实施方式及其变形包含在发明的范围或要旨内,同时包含在权利要求书中记载的发明和其均等的范围内。
Claims (14)
1.一种功率半导体装置,其特征在于,具备:
半导体衬底,具有第1导电型的漂移层;
第2导电型的基底层,选择性地形成在上述漂移层的表面;
元件部,形成在上述基底层和上述漂移层表面;
第2导电型的多个保护环,选择性地形成在上述元件部的周围的上述漂移层的表面;以及
绝缘物质,埋设在上述保护环中的至少1个保护环中。
2.如权利要求1中所述的功率半导体装置,其特征在于:
在上述保护环中设置有槽,在上述槽中埋设有上述绝缘物质。
3.如权利要求2中所述的功率半导体装置,其特征在于:
上述槽的底面与上述保护环的底面的距离至少大于等于2μm。
4.如权利要求3中所述的功率半导体装置,其特征在于:
上述多个保护环包括:与上述元件部接近地配置的最内周保护环;配置在上述最内周保护环的外侧的至少1个外周保护环;以及配置在上述外周保护环的外侧的最外周保护环,
在上述最内周保护环中,与径向并行地在两端附近设置有上述槽。
5.如权利要求4中所述的功率半导体装置,其特征在于:
在上述外周保护环和最外周保护环中,分别与径向并行地在内周侧的端部附近设置有上述槽。
6.如权利要求3中所述的功率半导体装置,其特征在于:
上述多个保护环包括:与上述元件部接近地配置的最内周保护环;配置在上述最内周保护环的外侧的至少1个外周保护环;以及配置在上述外周保护环的外侧的最外周保护环,
在上述外周保护环和最外周保护环中,分别与径向并行地在内周侧的端部附近设置有上述槽。
7.如权利要求1中所述的功率半导体装置,其特征在于:
上述保护环比上述基底层深。
8.如权利要求1中所述的功率半导体装置,其特征在于:
在上述多个保护环的外周设置有EQPR层。
9.如权利要求8中所述的功率半导体装置,其特征在于:
上述EQPR层、配置在最内周保护环的外侧的至少1个外周保护环和配置在上述外周保护环的外侧的最外周保护环连接于未设定电位的浮动状态的场电极。
10.如权利要求9中所述的功率半导体装置,其特征在于:
上述最内周保护环与上述基底层相接,经由上述基底层连接于发射极电极。
11.如权利要求2中所述的功率半导体装置,其特征在于:
上述绝缘物质是氧化硅膜、非掺杂多晶硅膜、非掺杂非晶硅膜和绝缘性有机膜中的某一种。
12.如权利要求11中所述的功率半导体装置,其特征在于:
在上述槽的侧面和底面设置有热氧化硅膜。
13.如权利要求1中所述的功率半导体装置,其特征在于:
上述功率半导体装置是功率MOSFET。
14.如权利要求1中所述的功率半导体装置,其特征在于:
上述功率半导体装置是在上述漂移层的与上述基底层相对的面的一侧还具备第1导电型的缓冲层和第2导电型的集电极层的IGBT。
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