CN103366824B - Non-volatility memorizer reading speed test circuit - Google Patents
Non-volatility memorizer reading speed test circuit Download PDFInfo
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- CN103366824B CN103366824B CN201210092948.5A CN201210092948A CN103366824B CN 103366824 B CN103366824 B CN 103366824B CN 201210092948 A CN201210092948 A CN 201210092948A CN 103366824 B CN103366824 B CN 103366824B
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Abstract
The invention discloses a kind of test circuit testing non-volatility memorizer, comprising: an address production electric circuit, under the driving of outside input clock, produce the address scan signal of non-volatility memorizer, read non-volatility memorizer continuously; A selection circuit, selects certain a data signal as benchmark to data-signal Dm ~ D0 that described non-volatility memorizer exports, and forms square-wave signal, the reading speed of test non-volatility memorizer; One programmable frequency divider, the square-wave signal that the data-signal that contraposition selection circuit is selected is formed, carries out frequency division according to the frequency dividing ratio of setting, and then exports with low frequency signal.Present invention eliminates the delay time error of each control circuit in test circuit, can realize the accurate test of non-volatility memorizer reading speed, measuring accuracy is high; And by the selection of control data position, the speed difference of each data bit can be compared.
Description
Technical field
The present invention relates to SIC (semiconductor integrated circuit) and manufacture field, particularly relate to a kind of non-volatility memorizer NVM (Non-VolatileMemory) reading speed test circuit.
Background technology
Current non-volatility memorizer reading speed test circuit adopts the structure shown in Fig. 1, address production electric circuit produces the reference address An ~ A0 of non-volatility memorizer under the driving of external clock (being inputted by pin PAD), the output data Dm ~ D0 of preset reference data and nonvolatile memory is compared by comparator circuit, and draws comparative result.This test circuit, owing to introducing the delayed impact of comparator circuit, therefore introduces test error.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of non-volatility memorizer reading speed test circuit, accurately can test the reading speed of non-volatility memorizer, and can not introduce the delay equal error of test circuit.
For solving the problems of the technologies described above, non-volatility memorizer reading speed test circuit of the present invention, comprising:
One address production electric circuit, produces the address scan signal of non-volatility memorizer, reads non-volatility memorizer continuously under the driving of outside input clock;
A selection circuit, selects certain a data signal as benchmark to data-signal Dm ~ D0 that described non-volatility memorizer exports, and forms square-wave signal, the reading speed of test non-volatility memorizer;
One programmable frequency divider, to the square-wave signal of the data-signal formation that institute's rheme selection circuit is selected, carries out frequency division according to the frequency dividing ratio of setting, and then exports with low frequency signal;
According to identical every address date in described non-volatility memorizer, the contrary form of neighbor address data step-by-step carries out data pre-storage storage, according to the address saltus step outputting data signals Dm ~ D0 of described address scan signal.
Adopt non-volatility memorizer reading speed test circuit of the present invention, the saltus step speed of address scan signal is directly proportional to outside input clock frequency, and the saltus step speed of described address scan signal and frequency dividing ratio (K) are all that system pre-sets, if reading non-volatility memorizer that therefore can be correct, the frequency of the low frequency signal waveform that programmable frequency divider exports is learnt in advance, thus can test the reading speed of non-volatility memorizer by the saltus step speed controlling address scan signal.
Present invention eliminates the delay time error of each control circuit in test circuit, can realize the accurate test of non-volatility memorizer reading speed, measuring accuracy is high; And by the selection of control data position, the speed difference of each data bit can be compared.
Test mode of the present invention is simple, and according to the frequency of outside input clock, observation output signal frequency just can draw non-volatility memorizer reading speed.
Circuit structure of the present invention is simple, is easy to realize, and cost is low.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is existing non-volatility memorizer reading speed test circuit figure;
Fig. 2 is non-volatility memorizer reading speed test circuit one embodiment schematic diagram of the present invention.
Embodiment
Shown in composition graphs 2, in one embodiment of this invention, wide for outputs data bits is that the FLASH of 16 bits is described.Described non-volatility memorizer reading speed test circuit, comprising: an address production electric circuit, a selection circuit, a programmable frequency divider.According to identical every address date in described non-volatility memorizer, the contrary form of neighbor address data step-by-step carries out data pre-storage storage, according to the address saltus step outputting data signals Dm ~ D0 of described address scan signal.As address 0 stores 0xAAAA, address 1 stores 0x5555, by that analogy.
Described address production electric circuit produces the address scan signal of non-volatility memorizer under the driving of the outside input clock (clock) inputted by input pin PAD2, reads non-volatility memorizer continuously.Such as add 1 with simple address and realize address scan.
Data-signal Dm ~ D0 that non-volatility memorizer exports selects through institute's rheme selection circuit, such as, select D0 as benchmark, and form the input signal of square-wave signal as programmable frequency divider, the reading speed of test non-volatility memorizer.
Described programmable frequency divider carries out frequency division according to the frequency dividing ratio of setting to input signal, thus with low frequency signal through exporting through output pin PAD1.
The saltus step speed of described address scan signal is determined by the outside input clock frequency v inputted from input pin PAD2, and the frequency dividing ratio k of described programmable frequency divider pre-sets; If therefore non-volatility memorizer can accurately read, the low frequency signal frequency exported by output pin PAD1 is determined by function f (v, k): f (v, k)=v/ (2 × k).
The frequency improving the outside input clock inputted by input pin PAD2 can measure the maximum reading speed of non-volatility memorizer; The data-signal that in the data-signal Dm ~ D0 selecting non-volatility memorizer to export by institute's rheme selection circuit, different bit data signals inputs as programmable frequency divider, repeats to test the speed difference that can draw between each data bit signal.
Non-volatility memorizer reading speed test circuit structure of the present invention can combine with the build-in self-test (BIST) of the existing non-volatility memorizer generally adopted, and realizes effectively controlling test.Wherein, address production electric circuit is produced by BIST; The primary data of non-volatility memorizer has been operated by BIST; Position selection circuit and frequency dividing ratio k can realize in BIST circuit; Input pin PAD2 and output pin PAD1 can the port of multiplexing BIST.
Below through the specific embodiment and the embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (3)
1. a non-volatility memorizer reading speed test circuit, is characterized in that, comprising:
One address production electric circuit, produces the address scan signal of non-volatility memorizer, reads non-volatility memorizer continuously under the driving of outside input clock;
A selection circuit, selects certain a data signal as benchmark to data-signal Dm ~ D0 that described non-volatility memorizer exports, and forms square-wave signal, the reading speed of test non-volatility memorizer;
One programmable frequency divider, to the square-wave signal of the data-signal formation that institute's rheme selection circuit is selected, carries out frequency division according to the frequency dividing ratio of setting, and then exports with low frequency signal;
According to identical every address date in described non-volatility memorizer, the contrary form of neighbor address data step-by-step carries out data pre-storage storage, according to the address saltus step outputting data signals Dm ~ D0 of described address scan signal;
The saltus step speed of described address scan signal is determined by outside input clock frequency v, and the frequency dividing ratio k of described programmable frequency divider pre-sets; The low frequency signal frequency that this programmable frequency divider exports is determined by function f (v, k), f (v, k)=v/ (2 × k).
2. circuit as claimed in claim 1, is characterized in that: the frequency improving outside input clock can measure the maximum reading speed of non-volatility memorizer.
3. circuit as claimed in claim 1, it is characterized in that: the signal that in the data-signal Dm ~ D0 selecting non-volatility memorizer to export by institute's rheme selection circuit, different bit data signals inputs as programmable frequency divider, repeat to test the speed difference that can draw between each data bit signal.
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| CN201210092948.5A CN103366824B (en) | 2012-03-31 | 2012-03-31 | Non-volatility memorizer reading speed test circuit |
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| CN201210092948.5A CN103366824B (en) | 2012-03-31 | 2012-03-31 | Non-volatility memorizer reading speed test circuit |
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| CN103366824B true CN103366824B (en) | 2016-02-10 |
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| CN106297893B (en) * | 2016-08-01 | 2019-04-09 | 上海华虹宏力半导体制造有限公司 | The clock circuit and its design method of memory measuring circuit |
| CN111696617B (en) * | 2020-05-28 | 2023-10-20 | 上海华虹宏力半导体制造有限公司 | Nonvolatile memory reading speed test circuit and test method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101937721A (en) * | 2010-08-04 | 2011-01-05 | 武汉天喻信息产业股份有限公司 | Method for testing memory device |
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| KR100624576B1 (en) * | 2004-06-11 | 2006-09-19 | 삼성전자주식회사 | Method of testing memory module having a hub and a hub of memory module for testing the same |
| TW200937438A (en) * | 2008-02-20 | 2009-09-01 | Inventec Corp | A memory writing interference test system and method thereof |
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| CN101937721A (en) * | 2010-08-04 | 2011-01-05 | 武汉天喻信息产业股份有限公司 | Method for testing memory device |
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