CN103310070A - Hierarchical simulation method for three-dimensional chip power supply ground network - Google Patents
Hierarchical simulation method for three-dimensional chip power supply ground network Download PDFInfo
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Abstract
The invention provides a hierarchical simulation method for a three-dimensional chip power supply ground network. The method comprises the following steps: inputting an original three-dimensional chip power supply ground network; decoupling the original three-dimensional chip power supply ground network so as to divide the original three-dimensional chip power supply ground network into a plurality of independent power supply ground networks with the number as same as the layer number; extracting a port equivalent model of each independent power supply ground network; establishing a new three-dimensional chip power supply ground network according to all the port equivalent models; solving the new three-dimensional chip power supply ground network to obtain port voltage and current of each layer of network; obtaining the internal node voltage of each layer of network according to the port voltage and current of each layer of network. According to the method provided by the invention, simulating calculation can be performed on each layer in parallel, so that the calculating efficiency is improved and the simulating complexity is reduced.
Description
Technical field
The present invention relates to Electronic Design and technical field of automation, particularly a kind of layering emulation mode for the three-dimensional chip power ground network.
Background technology
Along with the technique progress, traditional two-dimentional chip design meeting runs into some bottlenecks, interconnected delay and leakage power consumption etc. on the sheet such as continuous increase.Three dimensional integrated circuits (3D IC) is by introducing in vertical direction the through hole (Through-Silicon-Via that passes silicon, TSV), traditional two-dimentional chip is stacked up in vertical direction, can reduce the length of interconnection line on the sheet, increase the I/O port number of chip chamber, improve data transfer bandwidth.In addition, three dimensional integrated circuits also has the integrated and less advantages such as physical dimension of the isomery of support, becomes gradually the developing direction of integrated circuit of future generation.
Characteristic dimension and supply voltage constantly reduce, and it is more and more crucial that the design of power ground network becomes in the chip design flow process.Specifically be carried in the supply voltage of circuit terminal, can be to the performance index of circuit, such as circuit power consumption and signal delay etc. produces great impact.Yet the analysis of power ground network is a very challenging task, may have millions of power supply ground nodes in present chip, and the simulation analysis of the network that they form can take a large amount of time and resource.Fig. 2 A is the electrical block diagram of power ground network in the two-dimentional chip, and the power supply ground metal wire is modeled as the series connection of inductance L seg and resistance R seg, and decoupling capacitor is Cd on the sheet, and the distribution of current of functional circuit is the Is among the figure.The electric power system of three-dimensional chip has been introduced power supply ground TSV on the basis of two-dimentional chip, the power ground network with each layer chip connects into an integral body in vertical direction, shown in Fig. 2 B.
The simulation analysis of power ground network is divided into dc analysis and transient analysis two parts substantially.In dc analysis, ignore electric capacity and inductance in the circuit, power ground network comprises resistance, current source and voltage source device, and the fundamental purpose of direct current emulation is the magnitude of voltage that obtains each power supply ground node under the static condition; In transient analysis, power ground network is modeled as a completely RLC network, and the fundamental purpose of Transient is to obtain each power supply ground node voltage over time curve and transient noise.
In current chip design, the interstitial content in the power ground network may be up to tens, so the solution procedure of matrix equation group can very consuming time and expensive source.Power ground network for two-dimentional chip, consider huge interstitial content, a large amount of work has been done at it by academia above the high efficiency simulating method, for example algebraic multigrid is done the conjugate gradient method (AMG-PCG) of pre-condition, mix multiple grid method (HMD) and class multiple grid method (Multigrid-like) etc., in addition, Min Zhao, Rajendran V.Panda, Sachin S.Sapatnekar, and David Blaauw " Hierarchical Analysis of Power Distribution Networks ", IEEE transactions on computer-aided design of integrated circuits and systems, VOL.21, NO.2, Pages:159-168, FEBRUARY2002 has proposed a kind of by different level emulation mode that is suitable for the power ground network of two-dimentional chip, and the method overcomes the challenge that simulation scale is brought with macro model.
In the power ground network of three-dimensional chip, TSV is as the vertical interconnect line, with the power ground network of stacking chip connect into an integral body, the Electric source coupling of chip chamber is closer, network size also is the several times under the two-dimensional case, these features are all so that the emulation of three-dimensional power ground network is more challenging, and the emulation mode that research is suitable for three-dimensional power ground network seems and is necessary very much.
There has been part to pay close attention to modeling and the rapid simulation method of three-dimensional power ground network in academia, the physical model modeling of for example compacting (compact physical model) and frequency-domain model dimensionality reduction (Model Order Reduction, the method such as MOR), yet, these methods are looked the power ground network of three-dimensional chip as a whole, the number of the unknown quantity among the system of equations Gx=I that sets up, be the power supply ground node number sum of each layer chip in the three-dimensional chip, this has increased the complexity of emulation greatly.
In addition; such as article Xiang Hu; Thomas Toms; Riko Radojcic; Matt Nowak; Nick Yu and Chung-Kuan Cheng; " Enabling Power Distribution Network Analysis Flows for3D ICs " 3D Systems Integration Conference (3D IC); 2010IEEE International; pp1-4; 2010 described, when the chip of each layer of three dimensional integrated circuits during from different manufacturer, can have contradiction between the data sharing demand of each layer chip chamber and the property right protection demand of different vendor.
Summary of the invention
The present invention is intended to solve at least one of technical matters that exists in the prior art.
For this reason, the object of the invention is to propose a kind ofly can carry out simulation calculation to each layer concurrently, improve counting yield, reduce the layering emulation mode that is used for the three-dimensional chip power ground network of the complexity of emulation.
To achieve these goals, embodiments of the invention provide a kind of layering emulation mode for the three-dimensional chip power ground network, may further comprise the steps: input original three-dimensional chip power ground network; Described original three-dimensional chip power ground network is carried out decoupling zero, described original three-dimensional chip power ground network is divided into a plurality of independent current source zone networks that equate with the number of plies; Extract the port equivalent model of each independent current source zone network; Set up new three-dimensional chip power ground network according to all port equivalent models; Described new three-dimensional chip power ground network is found the solution to obtain port voltage and the electric current of each layer network; And the internal node voltages that obtains each layer network according to port voltage and the electric current of described each layer network.
The layering emulation mode that is used for the three-dimensional chip power ground network according to the embodiment of the invention adopts the layering simulation flow, uses the three-dimensional chip from industry member to carry out Accuracy Verification.Work previously in three-dimensional power ground network aspect is compared, and the emulation mode of the embodiment of the invention can independent parallel ground be processed each layer network of three-dimensional chip.And the port equivalent model has been hidden the details of each layer network; can protect on the one hand the trade secret of chip supplier; guaranteed again on the other hand the electrology characteristic of port; provide convenience for the chip designer carries out collaborative simulation to the shielded chip from different vendor, relaxed to a certain extent the contradiction that exists between the property right protection demand of the data sharing demand of each layer chip chamber and different vendor.In addition, method of the present invention is incorporated into " local characteristics " in the power supply status network simulation of three-dimensional chip, and " local characteristics " of electric power network can be used for simplifying the port equivalent model of each layer network, thereby further reduces the complexity of layering emulation.It is pointed out that method of the present invention both can be applied to the direct current emulation of power ground network, also can be applied to Transient.
In addition, the layering emulation mode for the three-dimensional chip power ground network according to the above embodiment of the present invention can also have following additional technical characterictic:
In some instances, described original three-dimensional chip power ground network comprises the size of power/ground of silicon number of openings, each layer network of the number of plies, each layer network and the power ground network parameter of each layer network.
The mode of in some instances, described original three-dimensional chip power ground network being carried out decoupling zero is: remove in the original three-dimensional chip silicon through hole between the different layers chip to disconnect the connection between each layer network in the described original three-dimensional chip power ground network.
In some instances, the step of the port equivalent model of each independent current source zone network of described extraction specifically comprises: interconnection line resistance and the distribution of current of extracting every layer independent current source zone network of decoupling zero; All of the port ground connection with every layer independent current source zone network, set up concurrently according to described interconnection line resistance and distribution of current each layer the independent current source zone network the matrix equation group and find the solution, to obtain flowing into from each port the electric current of the independent current source zone network of each layer, wherein, described electric current is the electric current unknown quantity in the port equivalent model of respective layer; With the port of the independent current source zone network of each layer successively order position voltage source, upgrade described matrix equation group and find the solution, and according to every delegation of the Current calculation Jacobian matrix that flows into each port, to obtain the complete port equivalent model of described each independent current source zone network.
In some instances, the described step of setting up new three-dimensional chip power ground network according to all port equivalent models, further comprise: the silicon through hole that is removed is inserted in the corresponding port equivalent model, with each layer port equivalent model that will connect as described new three-dimensional chip power ground network.
In some instances, also comprise: the internal node voltages of described each layer network of output.
Additional aspect of the present invention and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Of the present invention and/or additional aspect and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is the process flow diagram that is used for according to an embodiment of the invention the layering emulation mode of three-dimensional chip power ground network;
Fig. 2 A is the electrical block diagram of power ground network in the two-dimentional chip;
Fig. 2 B is the power delivery system structural representation of three-dimensional chip;
Fig. 3 is the citation form schematic diagram according to the matrix equation group of the foundation of the layering emulation mode that is used for the three-dimensional chip power ground network of the embodiment of the invention;
Fig. 4 is the mathematic(al) representation according to the port equivalent model of the layering emulation mode that is used for the three-dimensional chip power ground network of the embodiment of the invention;
Fig. 5 is the schematic diagram according to the port equivalent model of the layering emulation mode that is used for the three-dimensional chip power ground network of the embodiment of the invention;
Fig. 6 is that the port number according to the layering emulation mode that is used for the three-dimensional chip power ground network of the embodiment of the invention is the circuit structure of 2 port equivalent model.
Embodiment
The below describes embodiments of the invention in detail, and the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or the element with identical or similar functions from start to finish.Be exemplary below by the embodiment that is described with reference to the drawings, only be used for explaining the present invention, and can not be interpreted as limitation of the present invention.On the contrary, embodiments of the invention comprise spirit and interior all changes, modification and the equivalent of intension scope that falls into additional claims.
In description of the invention, it will be appreciated that, term " first ", " second " etc. only are used for describing purpose, and can not be interpreted as indication or hint relative importance.In description of the invention, need to prove, unless clear and definite regulation and restriction are arranged in addition, term " links to each other ", " connection " should do broad understanding, for example, can be to be fixedly connected with, and also can be to removably connect, or connects integratedly; Can be mechanical connection, also can be to be electrically connected; Can be directly to link to each other, also can indirectly link to each other by intermediary.For the ordinary skill in the art, can concrete condition understand above-mentioned term concrete meaning in the present invention.In addition, in description of the invention, except as otherwise noted, the implication of " a plurality of " is two or more.
Describe and to be understood in the process flow diagram or in this any process of otherwise describing or method, expression comprises module, fragment or the part of code of the executable instruction of the step that one or more is used to realize specific logical function or process, and the scope of preferred implementation of the present invention comprises other realization, wherein can be not according to order shown or that discuss, comprise according to related function by the mode of basic while or by opposite order, carry out function, this should be understood by the embodiments of the invention person of ordinary skill in the field.
Below in conjunction with the layering emulation mode that be used for three-dimensional chip power ground network of accompanying drawing description according to the embodiment of the invention.
Fig. 1 is the process flow diagram that is used for according to an embodiment of the invention the layering emulation mode of three-dimensional chip power ground network.As shown in Figure 1, the layering emulation mode that is used for the three-dimensional chip power ground network according to the embodiment of the invention may further comprise the steps:
Step S101: input original three-dimensional chip power ground network.
Wherein, original three-dimensional chip power ground network comprises the size of power/ground of silicon number of openings, each layer network of the number of plies, each layer network and the power ground network parameter of each layer network.That is to say, original three-dimensional chip power ground network comprises the parameters such as distribution of current of functional circuit on the size of silicon through hole (TSV) number, power/ground of its number of plies, each layer network and the chip, and can calculate the electrical parameters such as resistance of interconnection line.
Step S102: original three-dimensional chip power ground network is carried out decoupling zero, original three-dimensional chip power ground network is divided into a plurality of independent current source zone networks that equate with the number of plies.
The mode of particularly, original three-dimensional chip power ground network being carried out decoupling zero is: remove in the original three-dimensional chip silicon through hole between the different layers chip to disconnect the connection between each layer network in the original three-dimensional chip power ground network.Namely remove the TSV of each layer, original three-dimensional chip power ground network is divided into several networks (independent current source zone network) independently that equate with the number of plies.
Step S103: the port equivalent model that extracts each independent current source zone network.Specifically, for each layer network (independent current source zone network) of separating after being coupled, independent parallel ground extracts the port equivalent model of every one deck.The power ground network of supposing certain layer of chip links to each other with the chip of adjacent layer by M TSV, defines this M tie point and is the port of this layer network, and the mathematic(al) representation of its port equivalent model as shown in Figure 4 so.Wherein, I ∈ R
M * 1The current vector that flows into this layer network through defined port, J ∈ R
M * MBe that dimension is the Jacobian matrix of M, reflected dependence inherent between each port, V ∈ R
M * 1The voltage vector of each port, S ∈ R
M * 1That the driving source of this layer network inside is at the current vector of port generation, I
1The electric current that flows into network via port one, V
1The voltage of port one,
To flow into the electric current of network to the partial differential of the voltage of port one via port one.The structural representation of port equivalent model as shown in Figure 5.
In one embodiment of the invention, extract the step of the port equivalent model of each independent current source zone network, specifically comprise:
1) extracts interconnection line resistance and the distribution of current of every layer independent current source zone network of decoupling zero.
2) with all of the port ground connection of every layer independent current source zone network, set up concurrently according to interconnection line resistance and distribution of current each layer the independent current source zone network the matrix equation group and find the solution, to obtain flowing into from each port the electric current of the independent current source zone network of each layer, wherein, electric current is the electric current unknown quantity in the port equivalent model of respective layer.
3) with the port of the independent current source zone network of each layer successively order position voltage source, to upgrade the matrix equation group and to find the solution, and according to every delegation of the Current calculation Jacobian matrix that flows into each port, to obtain the complete port equivalent model of each independent current source zone network.
The below illustrates the process of finding the solution Jacobian matrix J and current vector S take M=2 as example:
Steps A according to the power ground network parameter of this layer of inputting, is extracted its interconnection line resistance and distribution of current, utilizes MNA to improve nodal method and sets up matrix equation group Gx=I, and its matrix equation group as shown in Figure 3.
Step B, with all of the port ground connection (M=2 represents to have two ports) of this layer, also be the mathematic(al) representation middle port voltage vector V=0 among Fig. 5, utilize Cholesky to decompose and find the solution the system of equations of setting up among the A, extraction flows into the electric current of network from each port, this result is exactly current vector S to be asked;
Step C adds a unit voltage source at the port one place, and port 2 ground connection also are V
1=1.0, V
2=0, find the solution the electric current that flows into each port according to the matrix equation among the A, and deduct and obtain the S vector among the B, this result is exactly the first row of Jacobian matrix J:
Step D adds a unit voltage source at port 2 places, and port one ground connection also is V
2=1.0, V
1=0, find the solution the electric current that flows into a port according to the matrix equation among the A, and deduct the S vector that obtains among the B, this result is exactly the second row of Jacobian matrix J:
It is to be noted, the above finds the solution the process steps B of Jacobian matrix J and current vector S～step D, only in step B, the matrix G that sets up is done matrix decomposition one time, only need to carry out the back substitution operation of matrix in the step afterwards, the complexity of matrix back substitution operation is linear, is far smaller than the complexity O(N of matrix decomposition
3).In addition, above-mentioned port equivalent model Jacobian matrix J reflection be the port identity of power ground network inherence, in the Transient process of fixed step size, remain unchanged.Therefore, when the layering emulation mode was applied to Transient, each time point only need to upgrade the current vector S of port equivalent model, and its complexity is linear, the model modification cost is little, and the layering emulation mode also can be applied to the Transient of three-dimensional chip power ground network.
Like this, during port number M=2, by the port equivalent model that calculates above, just can substitute with circuit shown in Figure 6 the power ground network of this layer.When M increased, the computation process of port equivalent model only needed to add the unit voltage source in each port successively and gets final product to top similar, can obtain row of Jacobian matrix at every turn.In addition, the computation process of each row of Jacobian matrix J is fully independently, can parallel computation.
Step S104: set up new three-dimensional chip power ground network according to all port equivalent models.
Particularly, set up the step of new three-dimensional chip power ground network according to all port equivalent models, further comprise: the silicon through hole that is removed is inserted in the corresponding port equivalent model, with each layer port equivalent model that will connect as new three-dimensional chip power ground network.Namely substitute the power ground network of respective layer with the circuit (Fig. 6) of the port equivalent model of each layer that obtains among the step S103, the TSV that is removed among the step S101 is put back in the network again, the port equivalent model of each layer is connected into an integral body.Interstitial content in the network that newly obtains (new three-dimensional chip power ground network) only equals the port number of each layer, and its solving complexity is far smaller than the primitive network (original three-dimensional chip power ground network) of input.
Step S105: port voltage and the electric current of new three-dimensional chip power ground network being found the solution to obtain each layer network.Be the new circuit (new three-dimensional chip power ground network) that obtains among the solution procedure S104, obtain port voltage and the electric current of each layer network.
Step S106: the internal node voltages that obtains each layer network according to port voltage and the electric current of each layer network.Particularly, port voltage and electric current with every one deck of obtaining among the step S105 are updated in the matrix equation group of this layer of setting up in the steps A, obtain the voltage of this layer internal node.
After obtaining the voltage of every layer of internal node, also comprise: the internal node voltages of exporting each layer network.
By analysis, when step S103 finds the solution every one deck port equivalent model in the above, if port number M is too huge, the TSV that also namely is used for the interlayer vertical interconnect is very intensive, then resulting port equivalent electrical circuit is understood the corresponding very complex that becomes, the number of voltage-controlled current source can sharply increase in the equivalent electrical circuit as shown in Figure 6, and its number becomes square to increase progressively relation with M.This can increase the complexity of solving circuit among the step S105.
In order to address this problem, the present invention is incorporated into " local characteristics " of power ground network in the emulation of three-dimensional power ground network, this characteristic is based on such fact: in the power ground network of flip-chip (flip-chip), power supply ground pad frequently is evenly distributed on the network, the electric current that a certain node produces on the network is most of can to flow away along contiguous pad, current value is decayed fast along with crossing over some pads, and the coverage in network has local feature.This means, among the step S103, in the process of finding the solution Jacobian matrix J, when port number M was very large, the coverage that is added in the unit voltage source of a port can be limited to very much, substantially can not be affected from the electric current of the distant port of this port.When neglecting after the dependence between distant port, Jacobian matrix J can be very sparse, and accordingly, the number of finding the solution voltage-controlled current source in the port equivalent electrical circuit that obtains can reduce greatly, simplify port equivalent model circuit, and then reduced the emulation complexity.
Table 1 is three from the test result on the three-dimensional chip of industry member, and the result shows that the layering emulation mode can keep precision (port voltage maximum relative error approximately 10
-12) situation under, compare traditional direct solving method, two-layer at three-dimensional chip 3D-μ P(), 3D-μ PD(is two-layer) and three layers of 3D_TxRx() on, can obtain respectively approximately 2.14 times, 1.95 times and 2.38 times of acceleration, the unit peak memory takies 0.628 times, 0.633 times and 0.882 times that is respectively the latter simultaneously.In a word, use the unit resource that the layering emulation mode of port equivalent model can be less, simulation velocity faster obtains the static direct current result of high accuracy three-dimensional power ground network.
Table 1
Table 2 is the experimental results to another three-dimensional chip, and circuit parameter extracts under 45nm technique, and in this test sample, each layer network comprises 1,000,000 nodes.In this experiment, progressively increased the port number (from 10x10 to 48x48) of interlayer, result's demonstration, the layering emulation mode can obtain to surpass 2 times speed-up ratio in time than direct solution, when port number is less, can reach 2.85 times acceleration.In addition, when port number increases, do not consider that the layering emulation mode of " local characteristics " can take a large amount of internal memories, when considering after " local characteristics ", when port number was 48x48, the peak memory of the layering emulation mode of simplification only was original about 1/5.
Table 2
Table 3 is the experimental results of a three layers chip 3D-TxRx of industry member being carried out the Transient test.The result shows that the speed-up ratio that the layering emulation mode is compared traditional direct solving method can descend gradually along with the increasing of time point number, and the number of plies is that the limit of 3 o'clock speed-up ratio approximately is 1.5..This is because use the layering emulation mode to carry out Transient, cost in each time point meeting inlet port equivalent model renewal, this cost can accumulate along with the increase of emulation duration, the parallel income that partial offset layering emulation mode obtains, thereby reduced available speed-up ratio, speed-up ratio is k/2 with the ultimate value that the Transient duration changes, and k is the chip number of plies.
Table 3
The layering emulation mode that is used for the three-dimensional chip power ground network according to the embodiment of the invention adopts the layering simulation flow, uses the three-dimensional chip from industry member to carry out Accuracy Verification.Work previously in three-dimensional power ground network aspect is compared, and the emulation mode of the embodiment of the invention can independent parallel ground be processed each layer network of three-dimensional chip.And the port equivalent model has been hidden the details of each layer network; can protect on the one hand the trade secret of chip supplier; guaranteed again on the other hand the electrology characteristic of port; provide convenience for the chip designer carries out collaborative simulation to the shielded chip from different vendor, relaxed to a certain extent the contradiction that exists between the property right protection demand of the data sharing demand of each layer chip chamber and different vendor.In addition, method of the present invention is incorporated into " local characteristics " in the power supply status network simulation of three-dimensional chip, and " local characteristics " of electric power network can be used for simplifying the port equivalent model of each layer network, thereby further reduces the complexity of layering emulation.
In the description of this instructions, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means to be contained at least one embodiment of the present invention or the example in conjunction with specific features, structure, material or the characteristics of this embodiment or example description.In this manual, the schematic statement of described term not necessarily referred to identical embodiment or example.And the specific features of description, structure, material or characteristics can be with suitable mode combinations in any one or more embodiment or example.In the present invention, term " a plurality of " refers to two or more.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification to these embodiment, scope of the present invention is by claims and be equal to and limit.
Claims (6)
1. a layering emulation mode that is used for the three-dimensional chip power ground network is characterized in that, may further comprise the steps:
Input original three-dimensional chip power ground network;
Described original three-dimensional chip power ground network is carried out decoupling zero, described original three-dimensional chip power ground network is divided into a plurality of independent current source zone networks that equate with the number of plies;
Extract the port equivalent model of each independent current source zone network;
Set up new three-dimensional chip power ground network according to all port equivalent models;
Described new three-dimensional chip power ground network is found the solution to obtain port voltage and the electric current of each layer network; And
The internal node voltages that obtains each layer network according to port voltage and the electric current of described each layer network.
2. method according to claim 1 is characterized in that, described original three-dimensional chip power ground network comprises the size of power/ground of silicon number of openings, each layer network of the number of plies, each layer network and the power ground network parameter of each layer network.
3. method according to claim 1, it is characterized in that, the mode that described original three-dimensional chip power ground network is carried out decoupling zero is: remove in the original three-dimensional chip silicon through hole between the different layers chip to disconnect the connection between each layer network in the described original three-dimensional chip power ground network.
4. method according to claim 1 is characterized in that, the step of the port equivalent model of each independent current source zone network of described extraction specifically comprises:
Extract interconnection line resistance and the distribution of current of every layer independent current source zone network of decoupling zero;
All of the port ground connection with every layer independent current source zone network, set up concurrently according to described interconnection line resistance and distribution of current each layer the independent current source zone network the matrix equation group and find the solution, to obtain flowing into from each port the electric current of the independent current source zone network of each layer, wherein, described electric current is the electric current unknown quantity in the port equivalent model of respective layer;
With the port of the independent current source zone network of each layer successively order position voltage source, to upgrade described matrix equation group and to find the solution, and according to every delegation of the Current calculation Jacobian matrix that flows into each port, to obtain the complete port equivalent model of described each independent current source zone network.
5. method according to claim 1 is characterized in that, the described step of setting up new three-dimensional chip power ground network according to all port equivalent models further comprises:
The silicon through hole that is removed is inserted in the corresponding port equivalent model, with each layer port equivalent model that will connect as described new three-dimensional chip power ground network.
6. method according to claim 1 is characterized in that, also comprises:
The internal node voltages of described each layer network of output.
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| CN105447242A (en) * | 2015-11-17 | 2016-03-30 | 西安华芯半导体有限公司 | Method for analyzing state of power supply network of integrated circuit in real time |
| CN111796199A (en) * | 2020-07-30 | 2020-10-20 | 上海兆芯集成电路有限公司 | Power supply network uniformity and power consumption testing method |
| CN113468837A (en) * | 2021-05-10 | 2021-10-01 | 浙江大学 | Method and system for estimating salient fast current of chip power supply network |
| WO2022242002A1 (en) * | 2021-05-20 | 2022-11-24 | 长鑫存储技术有限公司 | Modelling method and apparatus, computer device, and storage medium |
| CN116108779A (en) * | 2022-12-26 | 2023-05-12 | 北京华大九天科技股份有限公司 | Power ground network reduction method and system |
| CN116108779B (en) * | 2022-12-26 | 2024-07-30 | 北京华大九天科技股份有限公司 | Power ground network reduction method and system |
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| CN105447242B (en) * | 2015-11-17 | 2019-01-15 | 西安紫光国芯半导体有限公司 | A kind of method of real-time analysing integrated circuits electric power network state |
| CN111796199A (en) * | 2020-07-30 | 2020-10-20 | 上海兆芯集成电路有限公司 | Power supply network uniformity and power consumption testing method |
| CN111796199B (en) * | 2020-07-30 | 2022-12-27 | 上海兆芯集成电路有限公司 | Power supply network uniformity and power consumption testing method |
| CN113468837A (en) * | 2021-05-10 | 2021-10-01 | 浙江大学 | Method and system for estimating salient fast current of chip power supply network |
| CN113468837B (en) * | 2021-05-10 | 2023-11-03 | 浙江大学 | Method and system for estimating current of chip power supply network bump |
| WO2022242002A1 (en) * | 2021-05-20 | 2022-11-24 | 长鑫存储技术有限公司 | Modelling method and apparatus, computer device, and storage medium |
| CN116108779A (en) * | 2022-12-26 | 2023-05-12 | 北京华大九天科技股份有限公司 | Power ground network reduction method and system |
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