CN103260125A - Chip packaging structure and manufacturing method thereof - Google Patents
Chip packaging structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN103260125A CN103260125A CN2013101277676A CN201310127767A CN103260125A CN 103260125 A CN103260125 A CN 103260125A CN 2013101277676 A CN2013101277676 A CN 2013101277676A CN 201310127767 A CN201310127767 A CN 201310127767A CN 103260125 A CN103260125 A CN 103260125A
- Authority
- CN
- China
- Prior art keywords
- substrate
- chip
- line layer
- substrate surface
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
Landscapes
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
- Electrostatic, Electromagnetic, Magneto- Strictive, And Variable-Resistance Transducers (AREA)
Abstract
Disclosed are a chip packaging structure and a manufacturing method of the chip packaging structure. The chip packaging structure comprises a substrate, an electro-acoustic wave chip, a cover structure, and a sealing rubber body. The substrate comprises a first substrate surface, a second substrate surface, and a sound bore, wherein the first substrate surface is opposite to the second substrate surface. The first substrate surface is provided with a line layer. The electro-acoustic wave chip is configured on the first substrate surface of the substrate and electrically connected to the line layer. An active face of the electro-acoustic wave chip faces towards the sound bore. The cover structure is configured on the first substrate surface of the substrate and is provided with a containing space used for containing the electro-acoustic wave chip. The sealing rubber body wraps the cover structure and the line layer outside the cover structure. One of the substrate and the sealing rubber body is provided with an electric conduction penetrating hole. The electric conduction penetrating hole is directly contacted with the line layer and electrically connected to the electro-acoustic wave chip through the line layer.
Description
Technical field
The invention relates to a kind of chip-packaging structure and manufacture method thereof, and particularly relevant for a kind of silicon microelectromechanicgyroscope microphone (silicon MEMS microphone) chip-packaging structure and manufacture method thereof.
Background technology
General micro-electro-mechanical microphone packaging part be with micro-electro-mechanical microphone chip and other chips for example ASIC(Application Specific Integrated Circuit) (ASIC), read integrated circuit (IC) chip etc. and be configured in single substrate, and the shade that utilization has an accommodation space covers all chips.Wherein different chips are to utilize routing (trace) to be electrically connected to each other.Yet this micro-electro-mechanical microphone packaging part has big size, therefore is unfavorable for being applied to micro device, and use value and elasticity are restricted.
Summary of the invention
The present invention is relevant for a kind of chip-packaging structure and manufacture method thereof.Chip-packaging structure has small size.
According to an embodiment, a kind of chip-packaging structure is proposed, it comprises a substrate, an electroacoustic wave chip (acoustic transducer chip), a lid structure (cap) and an adhesive body.Substrate has one first relative substrate surface, one second substrate surface and a hole.Has a line layer on first substrate surface.The electroacoustic wave chip configuration and is electrically connected to line layer on first substrate surface of substrate.One active surface of electroacoustic wave chip is towards the sound hole.The lid structure is configured on first substrate surface of substrate, and has an accommodation space in order to ccontaining electroacoustic wave chip.Adhesive body coats and covers structure and the line layer that covers the structure outside.One of them has several conduction perforation substrate and adhesive body.The conduction perforation directly contacts with line layer, and be electrically connected to the electroacoustic wave chip via line layer.
According to an embodiment, a kind of chip-packaging structure is proposed, it comprises a substrate, an electroacoustic wave chip and a shade.Substrate has one first relative substrate surface, one second substrate surface, hole and several and extends in conduction perforation between first substrate surface and second substrate surface.Have a line layer on first substrate surface and be electrically connected to the conduction perforation.The electroacoustic wave chip configuration and is electrically connected to line layer on first substrate surface of substrate.One active surface of electroacoustic wave chip is towards the sound hole.Shade is configured on first substrate surface of substrate, and has an accommodation space in order to ccontaining electroacoustic wave chip.
According to an embodiment, a kind of manufacture method of chip-packaging structure is proposed, it may further comprise the steps.One substrate is provided.Substrate has one first relative substrate surface, one second substrate surface and a hole.Has a line layer on first substrate surface.Dispose an electroacoustic wave chip on first substrate surface of substrate, and be electrically connected to line layer.One active surface of electroacoustic wave chip is towards the sound hole.Configuration one is covered structure on first substrate surface of substrate, and has an accommodation space in order to ccontaining electroacoustic wave chip.Utilize an adhesive body to coat and cover structure and the line layer that covers the structure outside.Form several conduction perforation at substrate and adhesive body in one of them.The conduction perforation directly contacts with line layer, and be electrically connected to the electroacoustic wave chip via line layer.
For there is better understanding above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Description of drawings
Fig. 1 illustrates according to the chip-packaging structure among the embodiment.
Fig. 2 illustrates according to looking schematic diagram on the embodiment chips encapsulating structure.
Fig. 3 illustrates according to the chip-packaging structure among the embodiment.
Fig. 4 illustrates according to looking schematic diagram on the embodiment chips encapsulating structure.
Fig. 5 illustrates according to looking schematic diagram on the embodiment chips encapsulating structure.
Fig. 6 illustrates according to the chip-packaging structure among the embodiment.
Fig. 7 illustrates according to the chip-packaging structure among the embodiment.
Fig. 8 illustrates according to the chip-packaging structure among the embodiment.
Fig. 9 A to Fig. 9 J illustrates the manufacture method according to the chip-packaging structure of an embodiment.
Figure 10 A to Figure 10 F illustrates the manufacture method according to the chip-packaging structure of an embodiment.
Figure 11 A to Figure 11 D illustrates the manufacture method according to the chip-packaging structure of an embodiment.
Figure 12 A to Figure 12 D illustrates the manufacture method according to the chip-packaging structure of an embodiment.
Symbol description:
102,202,302,402,502～chip-packaging structure; 104～substrate; 106～electroacoustic wave chip; 108～lid structure; 110～adhesive body; 112～the first substrate surfaces; 114～the second substrate surfaces; 116～line layer; 118～insulating barrier; 120,121～opening; 122～sound hole; 124～active surface; 126～conductive pad; 128～conductive projection; 130～vibrating diaphragm; 132～resonator chamber; 134,134A～conducting resinl; 138,138A～accommodation space; 140,140A, 140B～conduction perforation; 142～surface; 144,144A～conductive pad; 146,146A～solder ball; 147～upper surface; 148,150,150A, 150B～lead; 152～shade; 154～accommodation space; 156,156A, 156B～perforation.
Embodiment
Please refer to Fig. 1, it illustrates according to an embodiment chips encapsulating structure 102, comprises a substrate 104, an electroacoustic wave chip (acoustic transducer chip) 106, one lid structure (cap) 108 and an adhesive body 110.
Several conducting resinls separated from each other 134 are configured in the opening 121 of insulating barrier 118, and are electrically connected to the line layer 116 that opening 121 exposes.
Can be in the surface of adhesive body 110 142 configurations other contact structures with conduction perforation 140 electric connections, for example conductive pad shown in Figure 1 144 and solder ball 146, but its physical connection of chip-packaging structure 102 mats and be electrically connected to other signal ends or apparatus structure.In an embodiment, for instance, lid structure 108 is the earth terminals that are electrically connected to an outside by conducting resinl 134, line layer 116, conduction perforation 140, conductive pad 144 and solder ball 146, and lid structure 108 can be used as Electromagnetic Interference (Electromagnetic Interference, EMI) protective action.
Please refer to Fig. 2, its illustrate as shown in Figure 1 chip-packaging structure 102 on look schematic diagram.Line layer 116 comprises several leads 148 and lead 150.Conductive projection 128 on the electroacoustic wave chip 106 is to be electrically connected to conduction perforation 140 via lead 148.The position in the opening 121 of insulating barrier 118 and the conducting resinl 134 that is spot distribution be to be electrically connected to conduction perforation 140 via lead 150, lid structure 108 is because directly contacting with conducting resinl 134, just can be electrically connected to conduction perforation 140 with lead 150 via conducting resinl 134, conduction perforation 140 for example is electrically connected to an external ground power supply, covers structure 108 and the electric connection of external ground power supply and make.
Please refer to Fig. 3, it illustrates according to an embodiment chips encapsulating structure 202.Difference between the chip-packaging structure 202 of Fig. 3 and the chip-packaging structure 102 of Fig. 1 is, part conducting resinl 134A is the upper surface 147 that is configured in insulating barrier 118, and the conducting resinl 134A of another part is filled in the opening 121 of insulating barrier 118, makes by this to cover structure 108 and be electrically connected to the line layer 116 and conduction perforation 140 that opening 121 exposes.
Please refer to Fig. 4, its illustrate as shown in Figure 3 chip-packaging structure 202 in an embodiment on look schematic diagram.Line layer 116 comprises several leads 148 and lead 150A.Conductive projection 128 on the electroacoustic wave chip 106 is to be electrically connected to conduction perforation 140 via lead 148.The conducting resinl 134A of strip is the part via the upper surface 147 (Fig. 3) that is arranged at insulating barrier 118, is electrically connected to lead 150A and conduction perforation 140 on first substrate surface 112 of substrate 104 with part in the opening 121 of filling insulating barrier 118.Because conducting resinl 134A is a L type structure in the present embodiment, via increasing the contact area of covering structure 108 and conducting resinl 134A, reach the purpose of stable lid structure 108 physics and electrical characteristic.
Please refer to Fig. 5, its illustrate as shown in Figure 3 chip-packaging structure 202 in an embodiment on look schematic diagram.Difference between Fig. 5 and Fig. 4 is, conducting resinl 134A is configured to ring-type, and be the part via the upper surface 147 (Fig. 3) that is arranged at insulating barrier 118, bore a hole 140 to be electrically connected to lead 150B with conduction with the part in the opening 121 of filling insulating barrier 118, via increasing the contact area of covering structure 108 and conducting resinl 134A, reach the purpose of stable lid structure 108 physics and electrical characteristic.
The configuration of the conducting resinl of embodiment is not limited to the mode as Fig. 2, Fig. 4 and Fig. 5, and can be according to other physical condition demands (shape, manufacturing cost of for example covering structure 108 etc. considered) modulation suitably.
Please refer to Fig. 6, it illustrates according to an embodiment chips encapsulating structure 302.Difference between the chip-packaging structure 302 of Fig. 6 and the chip-packaging structure 202 of Fig. 3 is that substrate 104 has several conduction perforation 140A, and conduction perforation 140A is electrically connected to electroacoustic wave chip 106 and conducting resinl 134A via line layer 116.Conduction perforation 140A can comprise solder material.In some embodiment, conducting resinl 134A has as Fig. 4 or configuration shown in Figure 5.Conducting resinl 134A is not limited to different piece and is configured on the insulating barrier 118 and filling opening 121, and can dispose by corresponding opening 121 as shown in Figure 1, and has distribution as shown in Figure 2.
Please refer to Fig. 7, it illustrates according to an embodiment chips encapsulating structure 402.Difference between the chip-packaging structure 402 of Fig. 7 and the chip-packaging structure 102 of Fig. 1 is, has omitted insulating barrier 118 and conducting resinl 134.Moreover lid structure 108 is to be configured on the line layer 116, and direct and line layer 116 electric connections.
Please refer to Fig. 8, it illustrates according to an embodiment chips encapsulating structure 502.Difference between the chip-packaging structure 102 of Fig. 8 chip-packaging structure 502 and Fig. 1 is, has omitted insulating barrier 118 and conducting resinl 134.Moreover shade (lid) 152 is configured on first substrate surface 112 of substrate 104, and has an accommodation space 154 in order to ccontaining single electroacoustic wave chip 106 and line layer 116.The accommodation space 154 that is communicated with sound hole 122 can be used as the resonator chamber of electroacoustic wave chip 106.In an embodiment, for instance, the material of shade 152 comprises metal or other suitable electric conducting materials, and can be electrically connected to the earth terminal of an outside, as the Electromagnetic Interference protective action.Substrate 104 has several conduction perforation 140B, and conduction perforation 140B is electrically connected to electroacoustic wave chip 106 via line layer 116.Other contact structures that can electrically connect at 114 configurations of second substrate surface and the conduction perforation 140B of substrate 104, conductive pad 144A and solder ball 146A shown in Figure 8 for example, mat its with chip-packaging structure 502 physical connections and be electrically connected to other signal ends or apparatus structure.In other embodiment, the replaceable one-tenth of conduction perforation 140B is filled the formed structure of perforation by solder material as shown in Figure 6, and omits conductive pad 144A and solder ball 146A, and anti-is as the same.
In embodiment, chip-packaging structure is the encapsulating structure of chip-scale (chip-scale), have small size and can be applied to various apparatus systems, so the value height.
Fig. 9 A to Fig. 9 J illustrates the manufacture method according to the chip-packaging structure of an embodiment.
Please refer to Fig. 9 A, at first substrate surface, the 112 formation line layers 116 of substrate 104.Substrate 104 can comprise glass substrate, its have preferable insulation effect and cost low.Substrate 104 can wafer scale the technology manufacturing.In an embodiment, the formation method of line layer 116 is included in and forms conductive layer (comprising metal for example copper or other suitable electric conducting materials) on first substrate surface 112, and patterned conductive layer is to form line layer 116 then.Line layer 116 can comprise lead, conductive pad etc.
Please refer to Fig. 9 B, at first substrate surface 112 and the line layer 116 formation insulating barriers 118 of substrate 104.In an embodiment, the formation method of insulating barrier 118 is included on first substrate surface 112 and the line layer 116 and forms insulation film, and the patterning insulation film is to form opening 120, the opening 121 of exposed portions serve line layer 116 then.In certain embodiments, can be via the opening 120 of insulating barrier 118, the conductive pad that opening 121 defines line layer 116.
Please refer to Fig. 9 C, formation sound hole 122 in substrate 104 and insulating barrier 118.Can hole in sound hole 122 or etched mode forms, for example modes such as dark reactive ion etching, laser-induced thermal etching, wet chemical etch.In an embodiment, substrate 104 comprises silicon substrate, and the technology in its formation sound hole 122 (perforation) is simple.Substrate 104 can wafer scale the technology manufacturing.
Please refer to Fig. 9 D, can electroacoustic wave chip 106 be configured on first substrate surface 112 of substrate 104 via Flip Chip, and be electrically connected to line layer 116 by the conductive pad 126 on the active surface 124 and the conductive projection 128 of filling opening 120.
Please refer to Fig. 9 E, the mode of utilisation point glue, conducting resinl 134 is configured in the opening 121 of insulating barrier 118 with insulating barrier 118 on.Lid structure 108 is configured on first substrate surface 112 of substrate 104, and wherein electroacoustic wave chip 106 is to be contained in the accommodation space 138 that covers structure 108.In an embodiment, lid structure 108 is to be pasted to substrate 104 and to be electrically connected to line layer 116 via conducting resinl 134.
Please refer to Fig. 9 F, utilize adhesive body 110 cap structures 108 and the line layer 116 and insulating barrier 118 that cover structure 108 outsides.
Please refer to Fig. 9 G, in adhesive body 110 and insulating barrier 118, form the perforation 156 of exposing line layer 116.Perforation 156 can be holed or etched mode forms, for example modes such as dark reactive ion etching, laser-induced thermal etching, wet chemical etch.
Please refer to Fig. 9 H, utilize electric conducting material to fill perforation 156 to form conduction perforation 140, conduction perforation 140 is directly contacted with line layer 116.
Please refer to Fig. 9 I, can be at the conductive pad 144 and solder ball 146 of the surface of adhesive body 110 142 configurations with conduction perforation 140 electric connections.
Please refer to Fig. 9 J, carry out cutting step, so that several chip-packaging structure Unit 102 are separated.
Figure 10 A to Figure 10 F illustrates the manufacture method according to the chip-packaging structure of an embodiment.Previous step and Fig. 9 A to the 9B figure are similar, no longer describe in this.
Please refer to Figure 10 A, formation sound hole 122 in substrate 104 and insulating barrier 118.In addition, form the perforation 156A that exposes line layer 116 from second substrate surface 114 toward substrate 104.Perforation 156A can hole or etched mode forms, for example modes such as dark reactive ion etching, laser-induced thermal etching, wet chemical etch.In an embodiment, substrate 104 comprises silicon substrate, and the technology of its formation sound hole 122, perforation 156A is simple.In another embodiment, substrate 104 comprises glass substrate, its have preferable insulation effect and cost low.Substrate 104 is not limited to silicon substrate and glass substrate, and can comprise the substrate that other are suitable.Substrate 104 can wafer scale the technology manufacturing.
Please refer to Figure 10 B, can be via Flip Chip, electroacoustic wave chip 106 is configured on first substrate surface 112 of substrate 104, and is electrically connected to line layer 116 by the conductive pad 126 on electroacoustic wave chip 106 active surfaces 124 and the conductive projection 128 of filling opening 120.
Please refer to Figure 10 C, the mode of utilisation point glue, conducting resinl 134A is configured in the opening 121 of insulating barrier 118 with insulating barrier 118 on.Lid structure 108 is configured on first substrate surface 112 of substrate 104, and wherein electroacoustic wave chip 106 is to be contained in the accommodation space 138 that covers structure 108.In an embodiment, lid structure 108 is to be pasted to substrate 104 and to be electrically connected to line layer 116 via conducting resinl 134A.
Please refer to Figure 10 D, utilize adhesive body 110 cap structures 108 and the line layer 116 and insulating barrier 118 that cover structure 108 outsides.
Please refer to Figure 10 E, utilize solder material to fill perforation 156A, to form conduction perforation 140A.In other embodiment, solder material can replace by other suitable electric conducting materials, for example copper, aluminium etc.
Please refer to Figure 10 F, carry out cutting step, separate with the unit with several chip-packaging structures 202.
Figure 11 A to Figure 11 D illustrates the manufacture method according to the chip-packaging structure of an embodiment.
Please refer to Figure 11 A, at first substrate surface, the 112 formation line layers 116 of substrate 104.Formation sound hole 122 in substrate 104.Can electroacoustic wave chip 106 be configured on first substrate surface 112 of substrate 104 via Flip Chip, and be electrically connected to line layer 116 by the conductive pad 126 on electroacoustic wave chip 106 active surfaces 124 with conductive projection 128.Lid structure 108 is configured on first substrate surface 112 of substrate 104, and wherein electroacoustic wave chip 106 is to be contained among the accommodation space 138A that covers structure 108.
Please refer to Figure 11 B, utilize adhesive body 110 cap structures 108 and the line layer 116 that covers structure 108 outsides.
Please refer to Figure 11 C, in adhesive body 110, form the perforation 156 of exposing line layer 116.Moreover, utilize electric conducting material to fill perforation 156 to form conduction perforation 140.Can be at the conductive pad 144 and solder ball 146 of the surface of adhesive body 110 142 configurations with conduction perforation 140 electric connections.
Please refer to Figure 11 D, carry out cutting step, separate with the unit with several chip-packaging structures 402.
Figure 12 A to Figure 12 D illustrates the manufacture method according to the chip-packaging structure of an embodiment.
Please refer to Figure 12 A, at first substrate surface, the 112 formation line layers 116 of substrate 104.Formation sound hole 122 in substrate 104.Can electroacoustic wave chip 106 be configured on first substrate surface 112 of substrate 104 via Flip Chip, and be electrically connected to line layer 116 by the conductive pad 126 on electroacoustic wave chip 106 active surfaces 124 with conductive projection 128.
Please refer to Figure 12 B, in substrate 104, form the perforation 156B that exposes line layer 116.Perforation 156B can hole or etched mode forms, for example modes such as dark reactive ion etching, laser-induced thermal etching, wet chemical etch.Moreover, utilize electric conducting material to fill perforation 156B to form conduction perforation 140B.Conductive pad 144A and the solder ball 146A that can electrically connect at 114 configurations of second substrate surface and the conduction perforation 140B of substrate 104.
Please refer to Figure 12 C, carry out cutting step, so that several cellular constructions are separated.
Please refer to Figure 12 D, the shade 152 that will have accommodation space 154 is configured on first substrate surface 112 of substrate 104, and wherein electroacoustic wave chip 106 is to be contained in the accommodation space 154 with line layer 116.In another embodiment, also can the shade 152 with accommodation space 154 be configured on first substrate surface 112 of substrate 104 earlier, carry out cutting step again.
The chip-packaging structure of embodiment and manufacture method thereof can be applied to the encapsulation of wafer scale (wafer level).
In sum, though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (10)
1. chip-packaging structure comprises:
One substrate has one first relative substrate surface, one second substrate surface and a hole, has a line layer on this first substrate surface;
One electroacoustic wave chip is configured on this first substrate surface of this substrate, and is electrically connected to this line layer, and an active surface of this electroacoustic wave chip is towards this hole;
One lid structure is configured on this first substrate surface of this substrate, and has an accommodation space in order to ccontaining this electroacoustic wave chip; And
One adhesive body, coat this lid structure and this lid structure the outside this line layer,
Wherein this substrate and this adhesive body one of them have several conduction perforation, those conduction perforation directly contact with this line layer, and be electrically connected to this electroacoustic wave chip via this line layer.
2. chip-packaging structure as claimed in claim 1 more comprises an insulating barrier, is configured on this line layer, and this insulating barrier has several this line layers of opening exposed portions serve.
3. chip-packaging structure as claimed in claim 2, more comprise the conducting resinl that several are separated from each other, be configured in those openings of this insulating barrier, and be electrically connected to this line layer that those openings expose, wherein this lid structure is to be pasted to this substrate and to be electrically connected to this line layer via those conducting resinls.
4. chip-packaging structure as claimed in claim 2, more comprise at least one conducting resinl, be configured on this insulating barrier, and the part of this at least one conducting resinl be the position those openings one of at least in, and be electrically connected to this line layer that this at least one opening exposes, wherein this lid structure is to be pasted to this substrate and to be electrically connected to this line layer via this at least one conducting resinl.
5. chip-packaging structure as claimed in claim 1, wherein this lid structure is to be electrically connected to an earth terminal.
6. chip-packaging structure comprises:
One substrate, have one first relative substrate surface, one second substrate surface, hole and several and extend in conduction perforation between this first substrate surface and this second substrate surface, have a line layer on this first substrate surface and be electrically connected to those conduction perforation;
One electroacoustic wave chip is configured on this first substrate surface of this substrate, and is electrically connected to this line layer, and an active surface of this electroacoustic wave chip is towards this hole; And
One shade is configured on this first substrate surface of this substrate, and has an accommodation space in order to ccontaining this electroacoustic wave chip.
7. as claim 1 or the 6th described chip-packaging structure, this substrate comprises silicon substrate or glass substrate.
8. the manufacture method of a chip-packaging structure comprises:
One substrate is provided, and this substrate has one first relative substrate surface, one second substrate surface and a hole, has a line layer on this first substrate surface;
Dispose an electroacoustic wave chip on this first substrate surface of this substrate, and be electrically connected to this line layer, wherein an active surface of this electroacoustic wave chip is towards this hole;
Configuration one is covered structure on this first substrate surface of this substrate, and has an accommodation space in order to ccontaining this electroacoustic wave chip;
Utilize an adhesive body to coat this line layer in this lid structure and this lid structure outside; And
Form several conduction perforation at this substrate and this adhesive body in one of them, those conduction perforation directly contact with this line layer, and be electrically connected to this electroacoustic wave chip via this line layer.
9. the manufacture method of chip-packaging structure as claimed in claim 8 more comprises forming an insulating barrier on this line layer, and wherein this insulating barrier has several this line layers of opening exposed portions serve.
10. the manufacture method of chip-packaging structure as claimed in claim 9, more comprise configuration one conducting resinl, this conducting resinl at least a portion is to be configured in those openings of this insulating barrier at least one, and being electrically connected to this line layer, this lid structure is to be pasted to this substrate and to be electrically connected to this line layer via those conducting resinls.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310127767.6A CN103260125B (en) | 2013-04-12 | 2013-04-12 | Chip-packaging structure and its manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310127767.6A CN103260125B (en) | 2013-04-12 | 2013-04-12 | Chip-packaging structure and its manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103260125A true CN103260125A (en) | 2013-08-21 |
| CN103260125B CN103260125B (en) | 2017-06-06 |
Family
ID=48963770
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310127767.6A Active CN103260125B (en) | 2013-04-12 | 2013-04-12 | Chip-packaging structure and its manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103260125B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979298A (en) * | 2015-06-26 | 2015-10-14 | 江西芯创光电有限公司 | Package substrate and production process thereof |
| CN106608613A (en) * | 2015-10-24 | 2017-05-03 | 美律电子(深圳)有限公司 | Chip package of micro-electro-mechanical system and manufacturing method of chip package |
| CN110759311A (en) * | 2019-10-29 | 2020-02-07 | 太极半导体（苏州）有限公司 | Leadless MEMS chip packaging structure based on window type substrate and process thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101534465A (en) * | 2008-03-11 | 2009-09-16 | 佳世达科技股份有限公司 | Micro electronmechanical microphone and packaging method thereof |
| CN201846474U (en) * | 2010-10-12 | 2011-05-25 | 歌尔声学股份有限公司 | Silicon microphone |
| CN101325823B (en) * | 2007-06-11 | 2011-08-17 | 美律实业股份有限公司 | Encapsulation construction for silicon crystal microphone |
| US20120027234A1 (en) * | 2010-07-30 | 2012-02-02 | Analog Devices, Inc. | Reduced Footprint Microphone System with Spacer Member Having Through-Hole |
-
2013
- 2013-04-12 CN CN201310127767.6A patent/CN103260125B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101325823B (en) * | 2007-06-11 | 2011-08-17 | 美律实业股份有限公司 | Encapsulation construction for silicon crystal microphone |
| CN101534465A (en) * | 2008-03-11 | 2009-09-16 | 佳世达科技股份有限公司 | Micro electronmechanical microphone and packaging method thereof |
| US20120027234A1 (en) * | 2010-07-30 | 2012-02-02 | Analog Devices, Inc. | Reduced Footprint Microphone System with Spacer Member Having Through-Hole |
| CN201846474U (en) * | 2010-10-12 | 2011-05-25 | 歌尔声学股份有限公司 | Silicon microphone |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979298A (en) * | 2015-06-26 | 2015-10-14 | 江西芯创光电有限公司 | Package substrate and production process thereof |
| CN104979298B (en) * | 2015-06-26 | 2017-11-21 | 江西芯创光电有限公司 | A kind of package substrate and its manufacture craft |
| CN106608613A (en) * | 2015-10-24 | 2017-05-03 | 美律电子(深圳)有限公司 | Chip package of micro-electro-mechanical system and manufacturing method of chip package |
| CN110759311A (en) * | 2019-10-29 | 2020-02-07 | 太极半导体（苏州）有限公司 | Leadless MEMS chip packaging structure based on window type substrate and process thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103260125B (en) | 2017-06-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5763682B2 (en) | Miniaturized electrical device including MEMS and ASIC and method for manufacturing the same | |
| JP4698296B2 (en) | Manufacturing method of semiconductor device having through electrode | |
| JP5142742B2 (en) | Pressure sensor and manufacturing method thereof | |
| JP4766143B2 (en) | Semiconductor device and manufacturing method thereof | |
| US9595453B2 (en) | Chip package method and package assembly | |
| CN103508413B (en) | For manufacturing the method with the component of electric plating through-hole | |
| CN205442631U (en) | Packaged sensor assembly | |
| CN103569941A (en) | Apparatus comprising MEMS and method for manufacturing embedded MEMS device | |
| CN102244013A (en) | Semiconductor device and manufacturing method thereof | |
| JP5352534B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN104733422A (en) | Chip package and method for forming the same | |
| CN104900607A (en) | Chip package and method of fabricating the same | |
| JP4504024B2 (en) | Manufacturing method of electronic device | |
| CN105097744A (en) | Chip package and method for manufacturing the same | |
| CN102656673B (en) | Electrical coupling of wafer structures | |
| CN111170265A (en) | MEMS device and method of manufacturing the same | |
| CN104900616A (en) | Chip package and method of manufacturing the same | |
| US8921955B1 (en) | Semiconductor device with micro electromechanical system die | |
| CN103260125A (en) | Chip packaging structure and manufacturing method thereof | |
| CN105366628A (en) | Low profile transducer module | |
| CN203351587U (en) | Semiconductor device | |
| CN102398886B (en) | Packaged structure with micro-electromechanical device and manufacture method thereof | |
| KR20140040646A (en) | Electric circuit and method for manufacturing an electric circuit | |
| CN214270212U (en) | Wafer level packaging structure and device level packaging structure | |
| CN214544781U (en) | MEMS microphone packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |