CN203351587U - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
CN203351587U
CN203351587U CN2013202079292U CN201320207929U CN203351587U CN 203351587 U CN203351587 U CN 203351587U CN 2013202079292 U CN2013202079292 U CN 2013202079292U CN 201320207929 U CN201320207929 U CN 201320207929U CN 203351587 U CN203351587 U CN 203351587U
Authority
CN
China
Prior art keywords
conductive pole
semiconductor element
semiconductor
substrate
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN2013202079292U
Other languages
Chinese (zh)
Inventor
沈一权
俊谟具
P.C.马里穆图
林耀剑
林诗轩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Shanghai Co Ltd
Stats Chippac Pte Ltd
Original Assignee
Stats Chippac Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/800,807 external-priority patent/US9559039B2/en
Application filed by Stats Chippac Pte Ltd filed Critical Stats Chippac Pte Ltd
Application granted granted Critical
Publication of CN203351587U publication Critical patent/CN203351587U/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

A semiconductor device comprises a linear having a substrate having a plurality of conductive poles extending from the substrate, and the linear could be in wafer, panel or monomerized shape, and the conductive poles could be circular, rectangular, conical or narrowed in the central portion. A semiconductor pipe core is arranged between conductive poles through holes, and the semiconductor pipe core is extended on the upper surface of the conductive poles or arranged on the lower surface of the conductive poles. Sealant is deposited on the semiconductor pipe core and encircles the conductive poles, and a part of the substrate and the sealant is removed to electrically isolate the conductive poles. A mutually connected structure is formed on the semiconductor pipe core, the sealant and the conductive poles, and an insulating layer is formed on the semiconductor pipe core, the sealant and the conductive poles. A semiconductor is packed on the semiconductor pipe core and electrically connected to the conductive poles.

Description

Semiconductor device
Technical field
Present invention relates in general to semiconductor device, and relate more specifically to a kind of semiconductor device and form the method for vertical interconnecting structure with the substrate of the conductive pole that there is substrate and extend from substrate embedded die package.
Background technology
Usually can find that there is semiconductor device in modern electronic product.Semiconductor device changes on the quantity of electric parts and density.Discrete semiconductor device generally comprises a kind of electric parts, for example light-emitting diode (LED), small-signal transistor, resistor, capacitor, inductor and power metal oxide semiconductor field-effect transistor (MOSFET).Integrated-semiconductor device generally includes hundreds of to millions of electric parts.The example of integrated-semiconductor device comprises microcontroller, microprocessor, charge-coupled device (CCD), solar cell and Digital Micromirror Device (DMD).
Semiconductor device is carried out several functions, for example signal processing, supercomputing, transmits and receives electromagnetic signal, controls electronic device, sunlight conversion is become to electricity and generates visual projection for television indicator.The existence of semiconductor device is arranged in amusement, communication, power transfer, network, computer and consumer product area.The existence of semiconductor device is also arranged in Military Application, aviation, automobile, industrial control unit (ICU) and office equipment.
Semiconductor device utilizes the electrical characteristics of semi-conducting material.The structure of semi-conducting material allows by applying electric field or base current (base current) or handling (manipulated) its conductivity by doping process.Doping is incorporated in semi-conducting material impurity to handle and to control the conductivity of semiconductor device.
Semiconductor device comprises active and passive electrical structure.Active structure (comprising bipolar and field-effect transistor) is controlled flowing of electric current.By changing doped level and applying electric field or base current, transistor promotes or the flowing of Limited Current.Passive structures (comprising resistor, capacitor and inductor) produces the relation of carrying out between the necessary voltage and current of multiple Electricity Functional.Passive and active structure is electrically connected to form circuit, and described circuit can make semiconductor device carry out high speed operation and other useful function.
Usually utilize the manufacturing process of two complexity to manufacture semiconductor device, i.e. manufacture front end manufacture and rear end, and each may comprise hundreds of steps.The front end manufacture is included on the surface of semiconductor wafer and forms a plurality of tube cores.Each semiconductor element is usually identical and comprise by being electrically connected to circuit active and that passive component forms.Rear end is manufactured and to be comprised from the single semiconductor element of completed wafer singulation (singulating) and package die so that support structure and environment isolation to be provided.Term " semiconductor element " refers to odd number and the plural form of word as used herein, and therefore can refer to single semiconductor device and a plurality of semiconductor device.
A target of semiconductor manufacture is to make less semiconductor device.Less device usually consumes power still less, has higher performance and can be manufactured more efficiently.In addition, less semiconductor device has less footprint (footprint), and it is expected for less end product.Cause producing and there is less, more highdensity active and semiconductor element passive component and can realize less semi-conductor die size by improving front-end process.By improving electrical interconnection and encapsulating material, backend process can produce has the more semiconductor packages in reduced dimension space.
Semiconductor packages is often used conductive pole or through hole as passing for example perpendicular interconnection of the sealant around semiconductor element between end face interconnection structure and bottom surface interconnection structure.Usually by etching or laser drill and fill or the plated conductive material forms the through hole through sealant.The equipment that the formation of conductive through hole is consuming time and needs are expensive.
Summary of the invention
The needs of existence to the simple and cost-effective vertical interconnecting structure in embedded die package.Therefore, in one embodiment, the present invention is a kind of semiconductor device that comprises the substrate that comprises a plurality of conductive poles.Semiconductor element is arranged between conductive pole.Sealant be deposited on semiconductor element and conductive pole around.Interconnection structure is formed on semiconductor element, sealant and conductive pole.
In another embodiment, the present invention is a kind of semiconductor device that comprises the substrate that comprises a plurality of electric isolate conductive posts.Semiconductor element is arranged between electric isolate conductive post.Sealant be deposited on semiconductor element and electric isolate conductive post around.Interconnection structure is formed on semiconductor element, sealant and electric isolate conductive post.
In another embodiment, the present invention is a kind of semiconductor device that comprises a plurality of conductive poles, and described conductive pole is included in the fixed intervals between described conductive pole.Semiconductor element is arranged between conductive pole.Sealant be deposited on semiconductor element and conductive pole around.Interconnection structure is formed on semiconductor element and conductive pole.
The accompanying drawing explanation
Fig. 1 shows the printed circuit board (PCB) (PCB) with the dissimilar encapsulation that is installed to its surface;
Fig. 2 a-2c illustrates the more details of the typical semiconductor encapsulation that is installed to PCB;
Fig. 3 a-3c shows the semiconductor wafer with a plurality of semiconductor elements that separated by scribing block (saw street);
Fig. 4 shows the substrate of the wafer shape of the conductive pole that has substrate and extend from substrate;
Fig. 5 shows the tape substrates of the conductive pole that has substrate and extend from substrate;
Fig. 6 a-6c shows the substrate of the singulation of the conductive pole that has substrate and extend from substrate;
Fig. 7 a-7b shows the alternative embodiment of conductive pole;
Fig. 8 a-8t shows with the substrate with substrate and conductive pole and form the technique of vertical interconnecting structure in embedded die package;
Fig. 9 shows the embedded die package had as the conductive pole of vertical interconnecting structure; And
Figure 10 a-10b shows the PoP with embedded die package and arranges, this embedded die package has the conductive pole as perpendicular interconnection.
Embodiment
Below with reference in the description of accompanying drawing, with one or more embodiment, describing the present invention, the same or similar element of similar numeral in the accompanying drawings.Although describe the present invention according to being used for realizing the best mode of purpose of the present invention, but it will be appreciated by those skilled in the art that it is intended to cover substitute, modification and the equivalent can be contained in the spirit and scope of the present invention that limited by following open and claims that each figure supports and equivalent thereof.
Semiconductor device is manufactured by the manufacturing process of two kinds of complexity usually: manufacture front end manufacture and rear end.The front end manufacture is included on the surface of semiconductor wafer and forms a plurality of tube cores.Each tube core on wafer comprises active and passive electrical parts, and described active and passive electrical parts are electrically connected to form functional circuit.Active electric parts, for example transistor and diode, have the ability of controlling current flowing.The passive electrical parts, for example capacitor, inductor and resistor, produce the relation between the necessary voltage and current of executive circuit function.
Form passive and active parts by the series of process step that comprises doping, deposition, photoetching, etching and complanation on the surface of semiconductor wafer.Doping is incorporated into impurity in semi-conducting material by the technology of for example Implantation or thermal diffusion.Doping process is by dynamically changing in response to electric field or base current the conductivity that the semi-conducting material conductivity changes the semi-conducting material in active device.Transistor comprises the zone of vicissitudinous doping type and degree, and described zone is provided so that transistor can promote when applying electric field or base current or the flowing of Limited Current as required.
Form active and passive component by the layer with different electrical characteristics materials.Described layer can be by partly being formed by the multiple deposition technique of the type decided that is deposited material.For example, thin film deposition can comprise chemical vapor deposition (CVD), physical vapor deposition (PVD), metallide and electrodeless plating technique.Each layer is patterned to be formed with the each several part of the electrical connection between source block, passive component or parts usually.
Rear end is manufactured to refer to completed wafer cutting or monomer is changed into to single semiconductor element, and then semiconductor dies is isolated in order to support structure and environment.For the singulation semiconductor element, along the wafer non-functional area delineation that is called scribing block or line with disconnect described wafer.Carry out the singulation wafer with laser cutting instrument or saw blade.After singulation, single semiconductor element is installed to package substrate, and described package substrate comprises for pin or contact pad with other system unit interconnection.Then the contact pad be formed on semiconductor element is connected to the contact pad in encapsulation.Can utilize the incompatible making of solder projection, stud bumps (stud bump), conducting resinl or toe-in to be electrically connected to.It is upper so that physical support and electricity isolation to be provided that sealant or other moulding material are deposited to encapsulation.Then completed encapsulation is inserted in electric system and makes the function of semiconductor device can be used for other system unit.
Fig. 1 illustrates the electronic device 50 with chip carrier substrate or printed circuit board (PCB) (PCB) 52, and described chip carrier substrate or printed circuit board (PCB) (PCB) 52 has a plurality of its lip-deep semiconductor packages that are arranged on.Electronic device 50 can have a kind of semiconductor packages or multiple semiconductor packages, and this depends on application.For illustrative purposes, figure 1 illustrates dissimilar semiconductor packages.
Electronic device 50 can be to utilize semiconductor packages to carry out the autonomous system of one or more Electricity Functionals.Replacedly, electronic device 50 can be the subassembly of larger system.For example, electronic device 50 can be the part of cellular phone, PDA(Personal Digital Assistant), Digital Video (DVC) or other electronic communication device.Replacedly, electronic device 50 can be graphics card, network interface unit or other signal processing card be inserted in computer.Semiconductor packages can comprise microprocessor, memory, application-specific integrated circuit (ASIC) (ASIC), logical circuit, analog circuit, RF circuit, discrete device or other semiconductor element or electric parts.For the product that will be accepted by market, miniaturization and weight reduction are necessary.Distance between semiconductor device must be reduced to realize higher density.
In Fig. 1, PCB 52 provides common support structure and the electrical interconnection of substrate for being arranged on the semiconductor packages on PCB.Use evaporation, metallide, electrodeless plating, silk screen printing or other suitable metal deposition process conductive signal trace 54 to be formed on the surface of PCB 52 or in each layer.Signal traces 54 provides each semiconductor packages, is mounted the telecommunication between parts and other external system components.Trace 54 also provides the VDD-to-VSS connection for each semiconductor packages.
In certain embodiments, semiconductor device has two package levels.First order encapsulation is for semiconductor element is attached to the technology of intermediate carrier with machinery and electric means.Second level encapsulation comprises described intermediate carrier is attached to PCB with machinery and electric mode.In other embodiments, semiconductor device can only have first order encapsulation, and wherein tube core directly is installed to PCB with machinery and electric mode.
For illustrative purposes, several first order encapsulation, comprise joint line encapsulation 56 and flip-chip 58, is illustrated on PCB 52.In addition, the encapsulation of several second level, comprise ball grid array (BGA) 60, bump chip carrier (BCC) 62, dual in-line package (DIP) 64, Land Grid Array (land grid array, LGA) 66, multi-chip module (MCM) 68, four sides are illustrated and are arranged on PCB 52 without pin flat packaging (quad flat non-leaded package, QFN) 70 and four flat-sided flat encapsulation 72.According to system requirements, utilize any combination and other electronic unit of semiconductor packages of any combination configuration of first and second grades of packing forms, can be connected to PCB 52.In certain embodiments, electronic device 50 comprises single semiconductor packages of adhering to, and other embodiment requires many interconnect package.By the one or more semiconductor packages of combination on single substrate, manufacturer can be incorporated to the parts of making in advance in electronic device and system.Because semiconductor packages comprises sophisticated functions, so electronic device can be manufactured by not too expensive parts and streamline manufacturing process.The unlikely inefficacy of resulting device and manufacture the cost less, the user is caused to lower cost.
Fig. 2 a-2c illustrates exemplary semiconductor packages.Fig. 2 a illustrates the more details of the DIP 64 be arranged on PCB 52.Semiconductor element 74 comprises the active area that comprises the analog or digital circuit, and described analog or digital circuit is implemented as electrical design according to tube core and is formed in tube core and active device, passive device, conductive layer and the dielectric layer of electrical interconnection.For example, other interior circuit element of active area that circuit can comprise one or more transistors, diode, inductor, capacitor, resistor and be formed on semiconductor element 74.Contact pad 76 is one or more layers electric conducting materials, for example aluminium (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au) or silver (Ag), and be electrically connected to the circuit element be formed in semiconductor element 74.At the assembly process of DIP 64, utilize gold silicon eutectic layer or adhesion material (for example epoxy or the epoxy resin of heat) that semiconductor element 74 is installed to intermediate carrier 78.Packaging body comprises the insulation-encapsulated material, for example polymer or pottery.Lead wire of conductor 80 and joint line 82 provide the electric interconnection between semiconductor element 74 and PCB 52.It is upper by preventing that moisture and particle from entering, to encapsulate and to pollute semiconductor element 74 or joint line 82 carrys out protection of the environment that sealant 84 is deposited over encapsulation.
Fig. 2 b illustrates the more details of the BCC 62 be arranged on PCB 52.Semiconductor element 88 utilizes bottom filling material or epoxy resin adhesion material 92 to be installed on carrier 90.Joint line 94 provides first order packaging interconnection between contact pad 96 and 98.Moulding compound or sealant 100 are deposited on semiconductor element 88 and joint line 94 thinks that described device provides physical support and electricity isolation.Contact pad 102 utilizes suitable metal deposition process (for example metallide or electrodeless plating) to be formed on the surface of PCB 52 in case oxidation.Contact pad 102 is electrically connected to the one or more conductive signal trace 54 in PCB 52.Projection 104 is formed between the contact pad 102 of the contact pad 98 of BCC 62 and PCB 52.
In Fig. 2 c, utilize the first order encapsulation of flip-chip form that semiconductor element 58 is installed to intermediate carrier 106 face-down.The active area 108 of semiconductor element 58 comprises the analog or digital circuit, and described analog or digital circuit is implemented as active device, passive device, conductive layer and the dielectric layer according to the electrical design formation of tube core.For example, this circuit can comprise one or more transistors, diode, inductor, capacitor, resistor and other circuit element in active area 108.Semiconductor element 58 is electrically connected and is mechanically connected to carrier 106 by projection 110.
BGA 60 utilizes projection 112 to be electrically connected and to be mechanically connected to have the PCB 52 of BGA type second level encapsulation.Semiconductor element 58 is electrically connected to the conductive signal trace 54 in PCB 52 by projection 110, holding wire 114 and projection 112.Moulding compound or sealant 116 are deposited on semiconductor element 58 and carrier 106 thinks that described device provides physical support and electricity isolation.Flip-chip semiconductor device provides active device from semiconductor element 58 to the short-range missile power path of the conductive traces on PCB 52 in order to reduce the signal propagation distance, reduce electric capacity and improve total circuit performance.In another embodiment, semiconductor element 58 can be in the situation that do not have intermediate carrier 106 to utilize the encapsulation of the flip chip type first order to be directly connected to PCB 52 with machinery and electric mode.
Fig. 3 a shows has for example silicon, germanium, GaAs, indium phosphide or carborundum for the base substrate material 122(of support structure) semiconductor wafer 120.A plurality of semiconductor elements or parts 124 are formed on wafer 120, by the wafer area between non-active tube core or scribing block 126 separately, and as mentioned above.Scribing block 126 provides cutting zone so that semiconductor wafer 120 monomers are changed into to single semiconductor element 124.
Fig. 3 b illustrates the sectional view of the part of semiconductor wafer 120.Each semiconductor element 124 has rear surface 128 and comprises the active surperficial 130 of analog or digital circuit, and described analog or digital circuit is implemented as electric Design and Features according to tube core and is formed in tube core and active device, passive device, conductive layer and the dielectric layer of electrical interconnection.For example, this circuit can comprise one or more transistors, diode and be formed on other circuit element in active surperficial 130 to realize analog circuit or digital circuit, for example digital signal processor (DSP), ASIC, memory or other signal processing circuit.Semiconductor element 124 also can comprise integrated passive devices (IPD), and for example inductor, capacitor and resistor, process for the RF signal.
Utilize PVD, CVD, metallide, electrodeless plating technique or other suitable metal deposition process to form conductive layer 132 on active surperficial 130.Conductive layer 132 can be one or more layers Al, Cu, Sn, Ni, Au, Ag or other suitable electric conducting material.Conductive layer 132 is as the contact pad that is electrically connected to the circuit on active surperficial 130.The contact pad be arranged side by side that it is the first distance that conductive layer 132 can be formed from the edge of semiconductor element 124, as shown in Fig. 3 b.Replacedly, conductive layer 132 can be formed such contact pad: described contact pad is offset with multirow, making the first row contact pad be set to from the edge of tube core is the first distance, and with the second row contact pad that the first row replaces, to be set to from the edge of tube core be second distance.
In Fig. 3 c, use saw blade or laser cutting instrument 134 that semiconductor wafer 120 is changed into to single semiconductor element 124 via scribing block 126 monomers.
Fig. 4 shows the wafer-shaped substrate or inserts mechanism 140, and described substrate or insertion mechanism comprise substrate 142 and the multirow conductive pole extended from substrate or go between 144.In one embodiment, substrate 140 be use that lead frame manufacturing technology (for example punching press) makes not by the preformed of singulation or the laminated substrates of making in advance.Substrate 140 is included in a plurality of tube core perforates 146 between conductive pole 144, and described tube core perforate 146 has enough sizes and comes, by this perforate, semiconductor element is installed.
Fig. 5 shows panel or the tape substrates that comprises substrate 152 and the multirow conductive pole extended from described substrate or conductive lead wire 154 or inserts mechanism 150.In one embodiment, substrate 150 be use that lead frame manufacturing technology (for example punching press) makes not by the preformed of singulation or the laminated substrates of making in advance.Substrate 150 is included in a plurality of tube core perforates 156 between conductive pole 154, and described tube core perforate 156 has enough sizes and comes, by this perforate, semiconductor element is installed.
Fig. 6 a shows the substrate of the singulation that comprises substrate 162 and the multirow conductive pole extended from described substrate or conductive lead wire 164 or inserts mechanism 160.In one embodiment, substrate 160 is preformed or laminated substrates that make in advance of using lead frame manufacturing technology (for example punching press) to make.Substrate 140-160 can be gold, silver, nickel, platinum, copper, copper alloy (comprising one or more elements in nickel, iron, zinc, tin, chromium, silver and phosphorus) or other suitable electric conducting material.Substrate 160 is included in the perforate 166 between conductive pole 164, and described perforate has enough sizes and comes, by this perforate, semiconductor element is installed.
Fig. 6 b shows has substrate 162 and the multirow conductive pole extended from described substrate or sectional view that the 6b-6b of the line along Fig. 6 a of 164 the substrate 160 of going between obtains.Fig. 6 c shows the sectional view that has the substrate 160 of recess 168 with rigidity reinforced in order to reinforce in substrate 162.Conductive pole 164 can be rectangle, circle, hexagon or other geometry.In one embodiment, substrate 162 has the thickness of 100-200 micron (μ m), and post 164 has the height of 80-300 μ m, diameter or the cross-sectional width of 50-250 μ m, and the spacing of 100-500 μ m.Conductive pole 164 also can have the shape of taper, and as shown in Figure 7a, wherein narrow end is in the scope of 30-200 μ m, and thicker end is in the scope of 50-300 μ m.Fig. 7 b shows the post 164 with thinner mid portion.Due to the character of extending from substrate 162, conductive pole 164 has fixing interval between each post.Substrate 140 has the cross section similar with Fig. 7 a-7b with Fig. 6 b-6c with 150 substrate with post.
With respect to Fig. 1 and Fig. 2 a-2c, Fig. 8 a-8t shows with the substrate with substrate and conductive pole and form the technique of vertical interconnecting structure in embedded die package.Fig. 8 a shows and comprises that described sacrificial substrate material is for example silicon, polymer, beryllium oxide, glass, belt or other suitable rigid material cheaply for the carrier of the sacrificial substrate material of support structure or the vertical view of interim substrate 170.Carrier 170 can be wafer shape or rectangle.Viscous layer or be with 172 to be applied to carrier 170.Fig. 8 b shows the sectional view of carrier 170 and viscous layer 172.
In Fig. 8 c, with conductive pole 144, towards described carrier, substrate 140 is placed on carrier 170.Fig. 8 d shows the substrate that is installed to carrier 170 140 obtained along the line 8d-8d of Fig. 8 e, and wherein conductive pole 144 is fixed to viscous layer 172, and Fig. 8 e shows the vertical view of the substrate 140 that is installed to carrier 170.
In Fig. 8 f, utilize for example to pick up and place to operate will from the semiconductor element 124 of Fig. 3 c be installed to carrier 170 towards carrier by the perforate 146 in substrate 140 with active surperficial 130.Semiconductor element 124 also can pass through the perforate 156 in substrate 150, or is installed to carrier 170 by the perforate 166 in substrate 160.Fig. 8 g shows semiconductor element 124 and the rear surface 128 of the viscous layer 172 that is installed to the carrier 170 in the perforate 146 of substrate 140 and extends on substrate 140.Fig. 8 h shows alternate embodiment, and wherein semiconductor element 124 is installed to below the viscous layer 172 of the carrier 170 in the perforate 146 of substrate 140 and substrate 142 that rear surface 128 is arranged on substrate 140.Fig. 8 i shows the vertical view of the semiconductor element 124 that is installed to the carrier 170 in the perforate 146 of substrate 140.
In Fig. 8 j, use slurry printing, compression molding, transfer modling, fluid sealant molding, vacuum lamination, spin coating or other suitable applicator that sealant or moulding compound 174 are deposited to semiconductor element 124, substrate 140 and above carrier 170.Sealant 174 can be polymer composites, for example have filler epoxy resin, there is the epoxy acrylate of filler or there is the polymer of suitable filler.Sealant 174 is nonconducting and on environment, protects semiconductor device to avoid outer member and pollutant effects.The embodiment sealant 174 that Fig. 8 k shows according to Fig. 8 h is deposited on semiconductor element 124, substrate 140 and carrier 170.
In Fig. 8 l, carrier 170 and viscous layer 172 are removed by chemical etching, mechanical stripping, chemical-mechanical planarization (CMP), mechanical lapping, hot baked, UV light, laser scanning or wet stripping, to expose semiconductor element 124 and conductive pole 144.
In Fig. 8 m, use patterning and metal deposition process (for example sputter, metallide and electrodeless plating) that conductive layer or redistribution layer (RDL) 180 are formed on to semiconductor element 124, conductive pole 144 and above sealant 174.Conductive layer 180 can be one or more layers Al, Cu, Sn, Ni, Au, Ag or other suitable electric conducting material.The part of conductive layer 180 is electrically connected to conductive pole 144.Another part of conductive layer 180 is electrically connected to the conductive layer 132 of semiconductor element 124.The other parts of conductive layer 180 can common-battery or the isolation of quilt electricity according to the Design and Features of semiconductor element 124.
Use PVD, CVD, printing, spin coating, spraying, sintering or thermal oxidation will be insulated or passivation layer 182 is formed on semiconductor element 124, sealant 174 and conductive layer 180.Insulating barrier 182 comprises one or more layers silicon dioxide (SiO 2), silicon nitride (Si 3n 4), silicon oxynitride (SiON), tantalum pentoxide (Ta 2o 5), aluminium oxide (Al 2o 3) or other there is the material of similar insulation and architectural characteristic.The part of insulating barrier 182 is removed to expose conductive layer 180.
Use patterning and metal deposition process, for example sputter, metallide and electrodeless plating, be formed on conductive layer or RDL 184 on conductive layer 180 and insulating barrier 182.Conductive layer 184 can be one or more layers Al, Cu, Sn, Ni, Au, Ag or other suitable electric conducting material.The part of conductive layer 184 is electrically connected to conductive layer 180.The other parts of conductive layer 184 can common-battery or the isolation of quilt electricity according to the Design and Features of semiconductor element 124.
Use PVD, CVD, printing, spin coating, spraying, sintering or thermal oxidation will be insulated or passivation layer 186 is formed on insulating barrier 182 and conductive layer 184.Insulating barrier 186 comprises one or more layers SiO 2, Si 3n 4, SiON, Ta 2o 5, Al 2o 3, or other there is the material of similar insulation and architectural characteristic.The part of insulating barrier 186 is removed to expose conductive layer 184.
Conductive layer 180 and 184 and insulating barrier 182 and 186 constituted the assembling interconnection structure 188 be formed on semiconductor element 124, conductive pole 144 and sealant 174. Conductive layer 180 and 184 and insulating barrier 182 and 186 can comprise IPD, for example capacitor, inductor or resistor.
In Fig. 8 n, backing strip (backing tape) 190 is applied to assembling interconnection structure 188 and operates for grinding back surface.In Fig. 8 o, the part of the substrate 142 of substrate 140 and semiconductor element 124 and sealant 174 is removed by grinder 192.Fig. 8 p shows the assembly after grinding operation overleaf, and wherein conductive pole 144 is interior by the electricity isolation at sealant 174.Fig. 8 q shows the vertical view of the assembly after grinding operation overleaf, and wherein conductive pole 144 is interior by the electricity isolation at the sealant 174 around semiconductor element 124.
In Fig. 8 r, use PVD, CVD, printing, spin coating, spraying, sintering or thermal oxidation will be insulated or passivation layer 196 is formed on semiconductor element 124 and sealant 174.Insulating barrier 196 comprises one or more layers SiO 2, Si 3n 4, SiON, Ta 2o 5, Al 2o 3, or other there is the material of similar insulation and architectural characteristic.The part of insulating barrier 196 is used laser 198 to be removed to expose conductive pole 144 by the direct ablation of laser.Replacedly, the part of insulating barrier 196 is used etch process to be removed to expose conductive pole 144 by the photoresist layer of patterning.Can apply optional welding material or protective finish 199 on the conductive pole 144 exposed from insulating barrier 196.
In Fig. 8 s, backing strip 190 is removed.Use evaporation, metallide, electrodeless plating, globule or silk-screen printing technique by the conductive projection deposition of material on conductive layer 184.Bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), Bi, Cu, the scolder with optional flux solution, and combination.For example, bump material can be eutectic Sn/Pb, high kupper solder or lead-free solder.Use suitable adhere to or combined process is attached to conductive layer 184 by bump material.In one embodiment, more than bump material is heated to its fusing point, described bump material refluxes to form ball or projection 200.In some applications, projection 200 electrically contacting with improvement and conductive layer 184 by secondary back.In one embodiment, projection 200 be formed on there is soakage layer, on the UBM of barrier layer and viscous layer.Projection also can compressed combination or hot compression be attached to conductive layer 184.Projection 200 has represented a kind of interconnection structure that can be formed on conductive layer 184.This interconnection structure also can be used joint line, conductive paste, stud bumps, dimpling piece or other electrical interconnection.
In Fig. 8 t, use saw blade or laser cutting instrument 202, by the sealant 174 between conductive pole 144, semiconductor element 124 monomers are changed into to single embedded die package 204.Fig. 9 shows the embedded die package 204 after singulation.Semiconductor element 124 is electrically connected to conductive pole 144 by interconnection structure 188, and described conductive pole 144 provides vertical electrical interconnection for embedded tube core.By substrate 140-160 is placed on carrier 170 and by semiconductor element 124 and is arranged in the perforate in substrate conductive pole 144 is formed in sealant 174.The substrate of substrate is removed with electricity isolates described conductive pole.Assembling interconnection structure 188 is formed on semiconductor element 124 and sealant 174.
Figure 10 a-10b shows the embodiment that arranges Stacked semiconductor package with laminate packaging (PoP).In Figure 10 a, semiconductor packages 210 comprises semiconductor element or the parts 212 that use die attachment adhesive 216 to be installed to substrate 214.Substrate 214 comprises conductive trace 218.Semiconductor element or parts 220 are used die attachment adhesive 222 to be installed to semiconductor element 212.A plurality of joint lines 224 are connected between the conductive trace 218 of the active lip-deep contact pad that is formed on semiconductor element 212 and 220 and substrate 214.Sealant 226 is deposited on semiconductor element 212 and 220, substrate 214 and joint line 224.Projection 228 is formed on the conductive trace 218 relative with semiconductor element 212 and 220 of substrate 214.
Figure 10 b shows the semiconductor packages 210 be installed to from the embedded die package 204 of Fig. 5, and wherein projection 228 is incorporated into conductive pole 144 as laminate packaging (PoP) 230.
Although described one or more embodiment of the present invention in detail, it will be appreciated by those skilled in the art that in the situation that do not break away from the scope of the present invention of being set forth by following claim and can modify and adapt those embodiment.

Claims (15)

1. a semiconductor device comprises:
The substrate that comprises a plurality of conductive poles;
Be arranged on the semiconductor element between conductive pole;
Be deposited on semiconductor element and around the sealant of conductive pole; With
Be formed on the interconnection structure on semiconductor element, sealant and conductive pole.
2. semiconductor device as claimed in claim 1, is characterized in that, further comprises the insulating barrier be formed on semiconductor element, sealant and conductive pole.
3. semiconductor device as claimed in claim 1, is characterized in that, the shape that conductive pole is circle, rectangle or taper, or described conductive pole has wider two ends and narrower mid portion.
4. semiconductor device as claimed in claim 1, is characterized in that, further comprises the semiconductor packages that is arranged on semiconductor element and is electrically connected to conductive pole.
5. a semiconductor device comprises:
The substrate that comprises the conductive pole of a plurality of electricity isolation;
Be arranged on the semiconductor element between electric conductive pole of isolating;
Be deposited on semiconductor element and the sealant of the conductive pole of isolating around electricity; With
Be formed on the interconnection structure on semiconductor element, sealant and electric conductive pole of isolating.
6. semiconductor device as claimed in claim 5, is characterized in that, further comprises the insulating barrier on the conductive pole that is formed on semiconductor element, sealant and electricity isolation.
7. semiconductor device as claimed in claim 5, is characterized in that, semiconductor element extends or is arranged on below conductive pole on the conductive pole of electricity isolation.
8. semiconductor device as claimed in claim 5, is characterized in that, the shape that the conductive pole of electricity isolation is circle, rectangle or taper, or the conductive pole of described electricity isolation has wider two ends and narrower mid portion.
9. semiconductor device as claimed in claim 5, is characterized in that, further comprises the semiconductor packages that is arranged on semiconductor element and is electrically connected to the conductive pole of electricity isolation.
10. a semiconductor device comprises:
A plurality of conductive poles, the plurality of conductive pole has fixed intervals between conductive pole;
Be arranged on the semiconductor element between conductive pole;
Be deposited on semiconductor element and around the sealant of conductive pole; With
Be formed on the interconnection structure on semiconductor element and conductive pole.
11. semiconductor device as claimed in claim 10, wherein conductive pole is the electricity isolation.
12. semiconductor device as claimed in claim 10, is characterized in that, further comprises the insulating barrier be formed on semiconductor element, sealant and conductive pole.
13. semiconductor device as claimed in claim 10, is characterized in that, semiconductor element extends or is arranged on below conductive pole on conductive pole.
14. semiconductor device as claimed in claim 10, is characterized in that, the shape that conductive pole is circle, rectangle or taper, or described conductive pole has wider two ends and narrower mid portion.
15. semiconductor device as claimed in claim 10, is characterized in that, further comprises the semiconductor packages that is arranged on semiconductor element and is electrically connected to conductive pole.
CN2013202079292U 2012-09-17 2013-04-23 Semiconductor device Expired - Lifetime CN203351587U (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201261702171P 2012-09-17 2012-09-17
US61/702,171 2012-09-17
US13/800,807 2013-03-13
US13/800,807 US9559039B2 (en) 2012-09-17 2013-03-13 Semiconductor device and method of using substrate having base and conductive posts to form vertical interconnect structure in embedded die package

Publications (1)

Publication Number Publication Date
CN203351587U true CN203351587U (en) 2013-12-18

Family

ID=49751452

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2013202079292U Expired - Lifetime CN203351587U (en) 2012-09-17 2013-04-23 Semiconductor device

Country Status (1)

Country Link
CN (1) CN203351587U (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104851858A (en) * 2014-02-19 2015-08-19 嘉盛马来西亚公司 Stacked electronic packages
CN106409699A (en) * 2015-07-30 2017-02-15 商升特公司 Semiconductor Device and Method of Forming Small Z Semiconductor Package
CN107799493A (en) * 2016-08-29 2018-03-13 吴澄玮 Semiconductor packages
CN110233112A (en) * 2018-03-06 2019-09-13 矽品精密工业股份有限公司 Electronic packing piece and its preparation method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104851858A (en) * 2014-02-19 2015-08-19 嘉盛马来西亚公司 Stacked electronic packages
CN104851858B (en) * 2014-02-19 2019-01-08 嘉盛马来西亚公司 The electronic packing piece of stacking
CN106409699A (en) * 2015-07-30 2017-02-15 商升特公司 Semiconductor Device and Method of Forming Small Z Semiconductor Package
CN107799493A (en) * 2016-08-29 2018-03-13 吴澄玮 Semiconductor packages
CN107799493B (en) * 2016-08-29 2021-03-09 巴迪磊博公司 Semiconductor package
CN110233112A (en) * 2018-03-06 2019-09-13 矽品精密工业股份有限公司 Electronic packing piece and its preparation method

Similar Documents

Publication Publication Date Title
CN103681607A (en) Semiconductor device and method of manufacturing semiconductor device
CN102194717B (en) Semiconductor device and form the method for insulating barrier around semiconductor element
US9153544B2 (en) Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor die
CN102237281B (en) Semiconductor device and manufacturing method thereof
CN102194740B (en) Semiconductor device and method of forming the same
CN102244012B (en) Semiconductor device and manufacture method thereof
US9478486B2 (en) Semiconductor device and method of forming topside and bottom-side interconnect structures around core die with TSV
US9721925B2 (en) Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structure
CN102157391B (en) The method of the thin profile WLCSP of semiconductor devices and formation perpendicular interconnection
CN102543772B (en) In conjunction with method and the semiconductor device of wafer scale different size semiconductor element
CN102194718B (en) Semiconductor device and manufacture method thereof
CN101996895B (en) Semiconductor device and method for manufacturing the same
CN101996896B (en) Semiconductor device and manufacture method thereof
CN101989558B (en) Semiconductor device and method of producing the same
US8318541B2 (en) Semiconductor device and method of forming vertical interconnect in FO-WLCSP using leadframe disposed between semiconductor die
US10410988B2 (en) Single-shot encapsulation
CN102386113A (en) Semiconductor device and method of manufacturing same
CN103681368A (en) Semiconductor device and method of forming wire studs as vertical interconnect in FO-WLP
CN103681468A (en) Semiconductor device and method of forming dual-sided interconnect structures in Fo-WLCSP
CN102376595A (en) Method and semiconductor device of forming FO-WLCSP having conductive layers and conductive vias
CN103715108A (en) Semiconductor device and method of depositing encapsulant in embedded WLCSP
CN203351587U (en) Semiconductor device
CN203288584U (en) Semiconductor device
CN209929301U (en) Semiconductor packaging structure
CN203386745U (en) Semiconductor device having double-faced interconnect structure for Fo-WLCSP

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
C41 Transfer of patent application or patent right or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20131202

Address after: Singapore Singapore

Patentee after: STATS ChipPAC Pte. Ltd.

Patentee after: Stats Chippac (shanghai) Ltd.

Address before: Singapore Singapore

Patentee before: STATS ChipPAC Pte. Ltd.

CP01 Change in the name or title of a patent holder

Address after: Singapore City

Co-patentee after: Stats Chippac (shanghai) Ltd.

Patentee after: STATS ChipPAC Pte. Ltd.

Address before: Singapore City

Co-patentee before: Stats Chippac (shanghai) Ltd.

Patentee before: STATS ChipPAC Pte. Ltd.

CP01 Change in the name or title of a patent holder
TR01 Transfer of patent right

Effective date of registration: 20200103

Address after: 312000 No.500 Linjiang Road, Yuecheng District, Shaoxing City, Zhejiang Province

Co-patentee after: Stats Chippac (shanghai) Ltd.

Patentee after: Changdian integrated circuit (Shaoxing) Co.,Ltd.

Address before: Singapore City

Co-patentee before: Stats Chippac (shanghai) Ltd.

Patentee before: STATS ChipPAC Pte. Ltd.

TR01 Transfer of patent right
CX01 Expiry of patent term

Granted publication date: 20131218

CX01 Expiry of patent term