CN103078593B - Lower-power-supply-voltage high-conversion-gain passive mixer - Google Patents
Lower-power-supply-voltage high-conversion-gain passive mixer Download PDFInfo
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- CN103078593B CN103078593B CN201210591261.6A CN201210591261A CN103078593B CN 103078593 B CN103078593 B CN 103078593B CN 201210591261 A CN201210591261 A CN 201210591261A CN 103078593 B CN103078593 B CN 103078593B
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Abstract
The invention discloses a lower-power-supply-voltage high-conversion-gain passive mixer, which comprises an input transconductance amplification stage, a switch mixing stage and an output transimpedance amplification stage. The input transconductance amplification stage adopts a push-pull transconductance structure. In order to satisfy the requirement of 0.6V power supply voltage, a common-mode negative feedback circuit based on two stages of common-source amplifiers is provided to enable transconductance-stage common mode bias voltage to be equal to fixed grid-source voltage. The switch mixing stage is used for modulating radio-frequency current output by the transconductance amplification stage and outputting medium-frequency current signals through low-pass filtering. The output transimpedance amplification stage is used for absorbing the medium-frequency current output by the switch mixing stage and outputting a mirror, and finally medium-frequency output voltage is obtained on a load resistor. Moreover, a transimpedance amplifier under low power supply voltage is provided. The transimpedance amplifier is based on a negative feedback structure, the output of low input impedance within a medium frequency band is realized, and the current utilization efficiency and the port isolation are improved. The lower-power-supply-voltage high-conversion-gain passive mixer with the structure has the advantages of low power consumption, high conversion gain and good port isolation.
Description
Technical field
The present invention relates to a kind of frequency mixer, be specifically related to a kind of Lower-power-supply-vhigh-conversion-gainpassive high-conversion-gainpassive passive mixer.
Background technology
In rf signal reception link, the effect of frequency mixer input radio frequency signal is downconverted to intermediate frequency or base band so that subsequent module processes.Consider from whole receiver, frequency mixer should have higher conversion gain to suppress the noise of rear class intermediate frequency amplifier circuit and filter circuit on the impact of whole receiver noise factor.In addition, frequency mixer itself should have good interport isolation to reduce the local-oscillator leakage at intermediate frequency end.Along with the continuous progress of CMOS technology, supply voltage constantly reduces, and the design for frequency mixer constantly proposes complicated problem.In recent years, silicon solar cell is more and more applied in Circuits System, and silicon solar cell only provides 0.6 volt of supply voltage, so the frequency mixer of design low supply voltage high-gain is significant, silicon solar cell power supply circuits systematic difference will be expanded.
Frequency mixer can be divided into active mixer and passive frequency mixer; active mixer has the enlarging function to signal in the lump while providing mixing function; comparatively serious intermediate-frequency circuit noise can be restrained effectively; but active mixer itself has larger noise; especially in zero intermediate frequency reciver structure; its flicker noise can bring certain influence; passive frequency mixer does not then have quiescent current; its flicker noise also significantly reduces, and the linearity of passive frequency mixer usually can higher than active mixer.
In classical mixing structure, for when radio-frequency voltage being converted to radio-frequency current in transconductance stage, the signal accepted due to receiver is general very little, and the transconductance value of traditional transconductance stage circuit is only generally the transconductance value of input transistors in addition, under Low-bias Current, its transconductance value is limited, and conversion gain is on the low side.
Summary of the invention
Goal of the invention: for above-mentioned prior art Problems existing and deficiency, the object of this invention is to provide a kind of Lower-power-supply-vhigh-conversion-gainpassive high-conversion-gainpassive passive mixer, the transconductance value of transconductance stage circuit is strengthened greatly, reduces the input resistance of output stage trans-impedance amplifier as far as possible.
Technical scheme: for achieving the above object, the technical solution used in the present invention is a kind of Lower-power-supply-vhigh-conversion-gainpassive high-conversion-gainpassive passive mixer, comprises input mutual conductance amplifying stage, passive mixing Switch Controller and exports across resistance amplifying stage;
Wherein, input mutual conductance amplifying stage comprises the first NMOS tube as radio frequency mutual conductance pipe, second NMOS tube, first PMOS, second PMOS, first, second, 5th, 6th resistance, first to fourth electric capacity, for reading the 3rd resistance and the 4th resistance of output common mode level, 3rd NMOS tube of composition common mode feedback circuit first order current source loads common source amplifying circuit and the 3rd PMOS, 4th PMOS of composition common mode feedback circuit second level ohmic load common source amplifying circuit and the 8th resistance, and form the 7th resistance and the 5th electric capacity of RC compensating network,
Passive mixing Switch Controller comprises the 4th to the 7th NMOS tube, the 6th to the 8th electric capacity;
Export and comprise the 8th across resistance amplifying stage, 9th, 13, 14 NMOS tube, as the 5th of current source, 7th PMOS, with the 12 of the work of common grid mode the, 17 NMOS tube, 11, 14 resistance, form the 6th of the first order current source loads common source amplifying circuit of feedback arrangement the, 8th PMOS and be used as current source the tenth, 15 NMOS tube, form the 11 of the second level ohmic load common source amplifying circuit of feedback arrangement the, 16 NMOS tube and the tenth, 13 resistance, and the 9th of composition RC compensating network the, 12 resistance and the 9th, tenth electric capacity,
Wherein:
The top crown of the first electric capacity connects input radio frequency signal positive pole, and its bottom crown connects the grid of the first NMOS tube; The top crown of the second electric capacity connects input radio frequency signal negative pole, and its bottom crown connects the grid of the second NMOS tube; The grid of the first NMOS tube connects the negative terminal of the first resistance, and its drain electrode connects the anode of the 3rd resistance, its source ground; The grid of the second NMOS tube connects the negative terminal of the second resistance, and its drain electrode connects the anode of the 4th resistance, its source ground; The anode of the first resistance and the second resistance all connects the first bias voltage; The top crown of the 3rd electric capacity connects the grid of the first NMOS tube, and its bottom crown connects the grid of the first PMOS; The top crown of the 4th electric capacity connects the grid of the second NMOS tube, and its bottom crown connects the grid of the second PMOS; The grid of the first PMOS connects the negative terminal of the 5th resistance, and its drain electrode connects the anode of the 3rd resistance, and its source electrode connects supply voltage; The grid of the second PMOS connects the negative terminal of the 6th resistance, and its drain electrode connects the anode of the 4th resistance, and its source electrode connects supply voltage; The grid of the 3rd NMOS tube connects the negative terminal of the 3rd resistance and the 4th resistance, its source ground, and its drain electrode connects the drain electrode of the 3rd PMOS; The grid of the 3rd PMOS connects the second bias voltage, its source ground, and its drain electrode connects the grid of the 4th PMOS; The grid of the 4th PMOS connects the anode of the 7th resistance, and its source electrode connects supply voltage, and its drain electrode connects the anode of the 5th resistance and the 6th resistance; The drain electrode of positive termination the 4th PMOS of the 8th resistance, its negativing ending grounding; The top crown of the 5th electric capacity connects the negative terminal of the 7th resistance, its bottom crown ground connection; The top crown of the 6th electric capacity connects the drain electrode of the first NMOS tube, and its bottom crown connects the source electrode of the 4th, the 5th NMOS tube; The top crown of the 7th electric capacity connects the drain electrode of the second NMOS tube, and its bottom crown connects the source electrode of the 6th, the 7th NMOS tube; Four, the grid of the 7th NMOS tube connects the positive pole of local oscillation signal, and the grid of the 5th, the 6th NMOS tube connects the negative pole of local oscillation signal; Four, the drain electrode of the 6th NMOS tube connects the top crown of the 8th electric capacity, and the drain electrode of the 5th, the 7th NMOS tube connects the bottom crown of the 8th electric capacity; The grid of the 8th NMOS tube connects the negative terminal of the tenth resistance (R10), and its drain electrode connects the drain electrode of the 5th PMOS, its source ground; The grid of the 5th PMOS connects the 3rd bias voltage, and its drain electrode connects the grid of the 6th PMOS, and its source electrode connects supply voltage; The grid of the 6th PMOS connects the anode of the 9th resistance, and its drain electrode connects the drain electrode of the tenth NMOS tube, and its source electrode connects supply voltage; The grid of the tenth NMOS tube connects the 4th bias voltage, and its drain electrode connects the grid of the 11 NMOS tube, its source ground; The grid of the 11 NMOS tube connects the bottom crown of the 9th electric capacity, and its drain electrode connects the negative terminal of the tenth resistance, its source ground; The top crown of the 9th electric capacity connects the negative terminal of the 9th resistance, and its bottom crown connects the grid of the 11 NMOS tube; The positive termination supply voltage of the tenth resistance, its negative terminal connects the grid of the 9th NMOS tube; The grid of the 9th NMOS tube connects the grid of the 8th NMOS tube, and its drain electrode connects the source electrode of the 12 NMOS tube, its source ground; The grid of the 12 NMOS tube connects the 5th bias voltage, and its drain electrode connects output voltage anode, and its source electrode connects the drain electrode of the 9th NMOS tube; The positive termination supply voltage of the 11 resistance, its negative terminal connects output voltage anode; The grid of the 13 NMOS tube connects the negative terminal of the 13 resistance, and its drain electrode connects the drain electrode of the 7th PMOS, its source ground; The grid of the 7th PMOS connects the 3rd bias voltage, and its drain electrode connects the grid of the 8th PMOS, and its source electrode connects supply voltage; The grid of the 8th PMOS connects the anode of the 12 resistance, and its drain electrode connects the drain electrode of the 15 NMOS tube, and its source electrode connects supply voltage; The grid of the 15 NMOS tube connects the 4th bias voltage, and its drain electrode connects the grid of the 16 NMOS tube, its source ground; The grid of the 16 NMOS tube connects the bottom crown of the tenth electric capacity, and its drain electrode connects the negative terminal of the 13 resistance, its source ground; The top crown of the tenth electric capacity connects the negative terminal of the 12 resistance, and its bottom crown connects the grid of the 16 NMOS tube; The positive termination supply voltage of the 13 resistance, its negative terminal connects the grid of the 14 NMOS tube; The grid of the 14 NMOS tube connects the grid of the 13 NMOS tube, and its drain electrode connects the source electrode of the 17 NMOS tube, its source ground; The grid of the 17 NMOS tube connects the 5th bias voltage, and its drain electrode connects output voltage negative terminal, and its source electrode connects the drain electrode of the 14 NMOS tube; The positive termination supply voltage of the 14 resistance, its negative terminal connects output voltage negative terminal.
Further, described first, second, the 5th, the 6th resistance is biasing resistor, described 11, the 14 resistance is load resistance, and described first to fourth, the 6th, the 7th electric capacity is coupling capacitance, and described 8th electric capacity is filter capacitor.
Beneficial effect: compared with prior art, the present invention has following beneficial effect:
1. power electric is forced down.Under frequency mixer of the present invention can be operated in the low supply voltage of 0.6V.
2. conversion gain is high.The input mutual conductance amplifying stage of frequency mixer of the present invention adopts to recommend and amplifies mutual conductance enhancing structure, mutual conductance is strengthened greatly, thus improves frequency mixer conversion gain.
3. intermediate frequency-prevention at radio-frequency port isolation is high.Export across resistance amplifying stage based on negative feedback structure, input impedance across resistance amplifying stage is further reduced, thus make the voltage of intermediate frequency exported across resistance amplifying stage input fluctuate very little, which decrease the voltage feed-through of intermediate-freuqncy signal toward transconductance stage output, stabilize transconductance stage output voltage, improve current utilization efficiency and interport isolation.
In sum, under this 0.6V low supply voltage, transconductance-enhancing passive frequency mixer has low in energy consumption, that the mutual conductance of input mutual conductance amplifying stage is high, conversion gain is high, interport isolation is good feature.
Accompanying drawing explanation
Fig. 1 is transconductance-enhancing passive frequency mixer circuit theory diagrams under low supply voltage of the present invention;
Fig. 2 is the conversion gain simulation result figure of transconductance-enhancing passive frequency mixer under low supply voltage of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, illustrate the present invention further, these embodiments should be understood only be not used in for illustration of the present invention and limit the scope of the invention, after having read the present invention, the amendment of those skilled in the art to the various equivalent form of value of the present invention has all fallen within the application's claims limited range.
As shown in Figure 1, a kind of Lower-power-supply-vhigh-conversion-gainpassive high-conversion-gainpassive passive mixer of the present invention, comprises and has mutual conductance and increase powerful input mutual conductance amplifying stage, passive mixing Switch Controller, and exports across resistance amplifying stage.This frequency mixer adopts to recommend and amplifies mutual conductance enhancing structure, and mutual conductance is strengthened greatly; , exporting across hindering amplifying stage based on feedback arrangement meanwhile, the input impedance across resistance amplifying stage being further reduced, improve current utilization efficiency and interport isolation.The features such as this mixer architecture has low in energy consumption, and conversion gain is high, interport isolation is good.
Input mutual conductance amplifying stage comprises as radio frequency mutual conductance pipe first, second N-type MOS transistor (hereinafter referred to as NMOS tube) NM1, NM2 and first, 2nd P type MOS transistor (hereinafter referred to as PMOS) PM1, PM2, biasing resistor R1, R2, R5, R6, coupling capacitance C1, C2, C3, C4, for reading the 3rd of output common mode level, 4th resistance R3, R4, 3rd NMOS tube NM3 of composition common mode feedback circuit first order current source loads common source amplifying circuit and the 3rd PMOS PM3, 4th PMOS PM4 of composition common mode feedback circuit second level ohmic load common source amplifying circuit and the 8th resistance R8, and the 7th resistance R7 of composition RC compensating network and the 5th electric capacity C5, passive mixing Switch Controller comprises the 4th to the 7th NMOS tube NM4-NM7, input coupling capacitance C6, C7, output filter capacitor C8, export and comprise the 8th across resistance amplifying stage, 9th NMOS tube NM8, NM9 and the 13, 14 NMOS tube NM13, NM14, as the 5th of current source, 7th PMOS PM5, PM7, with the 12 of the work of common grid mode the, 17 NMOS tube NM12, NM17, load resistance R11 and R14, form the 6th of the first order current source loads common source amplifying circuit of feedback arrangement the, 8th PMOS PM6, PM8 and be used as current source the tenth, 15 NMOS tube NM10, NM15, form the 11 of the second level ohmic load common source amplifying circuit of feedback arrangement the, 16 NMOS tube NM11, NM16 and the tenth, 13 resistance R10, R13, and the 9th of composition RC compensating network the, 12 resistance R9, R12 and the 9th, tenth electric capacity C9, C10.
Input radio frequency signal positive pole connects the top crown of the first electric capacity C1, and the bottom crown of the first electric capacity C1 connects the grid of the first NMOS tube NM1; Input radio frequency signal negative pole connects the top crown of the second electric capacity C2, and the bottom crown of the second electric capacity C2 connects the grid of the second NMOS tube NM2.The grid of the first NMOS tube NM1 connects the negative terminal of biasing resistor R1, and its drain electrode connects the anode of the 3rd resistance R3, its source ground; The grid of the second NMOS tube NM2 connects the negative terminal of biasing resistor R2, and its drain electrode connects the anode of the 4th resistance R4, its source ground.The anode of biasing resistor R1 and R2 all connects the first bias voltage 1.The top crown of the 3rd electric capacity C3 connects the grid of the first NMOS tube NM1, and its bottom crown connects the grid of the first PMOS PM1; The top crown of the 4th electric capacity C4 connects the grid of the second NMOS tube NM2, and its bottom crown connects the grid of the second PMOS PM2.The grid of the first PMOS PM1 connects the negative terminal of biasing resistor R5, and its drain electrode connects the anode of the 3rd resistance R3, and its source electrode connects supply voltage; The grid of the second PMOS PM2 connects the negative terminal of biasing resistor R6, and its drain electrode connects the anode of the 4th resistance R4, and its source electrode connects supply voltage.The grid of the 3rd NMOS tube NM3 connects the negative terminal of the third and fourth resistance R3 and R4, its source ground, and its drain electrode connects the drain electrode of the 3rd PMOS PM3.The grid of the 3rd PMOS PM3 connects the second bias voltage 2, its source ground, and its drain electrode connects the grid of the 4th PMOS PM4.The grid of the 4th PMOS PM4 connects the anode of the 7th resistance R7, and its source electrode connects supply voltage, and its drain electrode connects the anode of the 5th resistance R5 and the 6th resistance R6.The drain electrode of positive termination the 4th PMOS PM4 of the 8th resistance R8, its negativing ending grounding.The top crown of the 5th electric capacity C5 connects the negative terminal of the 7th resistance R7, its bottom crown ground connection.The top crown of the 6th electric capacity C6 connects the drain electrode of the first NMOS tube NM1, and its bottom crown connects the source electrode of the 4th, the 5th NMOS tube NM4, NM5; The top crown of the 7th electric capacity C7 connects the drain electrode of the second NMOS tube NM2, and its bottom crown connects the source electrode of the 6th, the 7th NMOS tube NM6, NM7.Four, the grid of the 7th NMOS tube NM4, NM7 connects the positive pole of local oscillation signal, and the grid of the 5th, the 6th NMOS tube NM5, NM6 connects the negative pole of local oscillation signal.Four, the drain electrode of the 6th NMOS tube NM4, NM6 connects the top crown of the 8th electric capacity C8, and the drain electrode of the 5th, the 7th NMOS tube NM5, NM7 connects the bottom crown of the 8th electric capacity C8.The grid of the 8th NMOS tube NM8 connects the negative terminal of the tenth resistance R10, and its drain electrode connects the drain electrode of the 5th PMOS PM5, its source ground.The grid of the 5th PMOS PM5 connects the 3rd bias voltage 3, and its drain electrode connects the grid of the 6th PMOS PM6, and its source electrode connects supply voltage.The grid of the 6th PMOS PM6 connects the anode of the 9th resistance R9, and its drain electrode connects the drain electrode of the tenth NMOS tube NM10, and its source electrode connects supply voltage.The grid of the tenth NMOS tube NM10 connects the 4th bias voltage 4, and its drain electrode connects the grid of the 11 NMOS tube NM11, its source ground.The grid of the 11 NMOS tube NM11 connects the bottom crown of the 9th electric capacity C9, and its drain electrode connects the negative terminal of the tenth resistance R10, its source ground.The top crown of the 9th electric capacity C9 connects the negative terminal of the 9th resistance R9, and its bottom crown connects the grid of the 11 NMOS tube NM11.The positive termination supply voltage of the tenth resistance R10, its negative terminal connects the grid of the 9th NMOS tube NM9.The grid of the 9th NMOS tube NM9 connects the grid of the 8th NMOS tube NM8, and its drain electrode connects the source electrode of the 12 NMOS tube NM12, its source ground.The grid of the 12 NMOS tube NM12 connects the 5th bias voltage 5, and its drain electrode connects output voltage anode, and its source electrode connects the drain electrode of the 9th NMOS tube NM9.The positive termination supply voltage of the 11 resistance R11, its negative terminal connects output voltage anode.The grid of the 13 NMOS tube NM13 connects the negative terminal of the 13 resistance R13, and its drain electrode connects the drain electrode of the 7th PMOS PM7, its source ground.The grid of the 7th PMOS PM7 connects the 3rd bias voltage 3, and its drain electrode connects the grid of the 8th PMOS PM8, and its source electrode connects supply voltage.The grid of the 8th PMOS PM8 connects the anode of the 12 resistance R12, and its drain electrode connects the drain electrode of the 15 NMOS tube NM15, and its source electrode connects supply voltage.The grid of the 15 NMOS tube NM15 connects the 4th bias voltage 4, and its drain electrode connects the grid of the 16 NMOS tube NM16, its source ground.The grid of the 16 NMOS tube NM16 connects the bottom crown of the tenth electric capacity C10, and its drain electrode connects the negative terminal of the 13 resistance R13, its source ground.The top crown of the tenth electric capacity C10 connects the negative terminal of the 12 resistance R12, and its bottom crown connects the grid of the 16 NMOS tube NM16.The positive termination supply voltage of the 13 resistance R13, its negative terminal connects the grid of the 14 NMOS tube NM14.The grid of the 14 NMOS tube NM14 connects the grid of the 13 NMOS tube NM13, and its drain electrode connects the source electrode of the 17 NMOS tube NM17, its source ground.The grid of the 17 NMOS tube NM17 connects the 5th bias voltage 5, and its drain electrode connects output voltage negative terminal, and its source electrode connects the drain electrode of the 14 NMOS tube NM14.The positive termination supply voltage of the 14 resistance R14, its negative terminal connects output voltage negative terminal.
Transconductance-enhancing passive frequency mixer under above-mentioned low supply voltage, normally can work under 0.6V low supply voltage, and has higher conversion gain and good interport isolation.The current radio frequency signal that input mutual conductance amplifying stage exports is coupled to switch mixer stage, enters and export across resistance amplifying stage after the frequency conversion of mixing switch.In order to obtain higher conversion gain, input mutual conductance amplifying stage have employed to recommend and amplifies mutual conductance enhancing structure, coupling capacitance C3, C4 is utilized input radio frequency signal to be coupled to the grid of first, second PMOS PM1, PM2 from the grid of first, second NMOS tube NM1, NM2, and adopt common mode feedback loop to provide direct current biasing for first, second PMOS PM1, PM2, thus the transconductance value of input mutual conductance amplifying stage is made to rise to g
mn+ g
mp, wherein g
mnfor the transconductance value of first, second NMOS tube NM1, NM2, g
mpfor the transconductance value of first, second PMOS PM1, PM2.In order to obtain good interport isolation, export across resistance amplifying stage based on feedback arrangement, make to export the resistance that frequency range enters from the 8th, viewed from the drain terminal of the 13 NMOS tube NM8, NM13 very low, electric current of intermediate frequency mixing obtained all sucks load stage, eventually through the 9th NMOS tube NM9, to the 8th NMOS tube NM8 and the 14 NMOS tube NM14, the current mirror to the 13 NMOS tube NM13 copies, and output loading is formed intermediate frequency output voltage.When signal frequency is relatively low, and the 8th, the 13 NMOS tube NM8, NM13 extremely low equivalent inpnt resistance make mutual conductance amplifying stage output node be equivalent to AC earth to output low frequency signal, make the amplitude of oscillation of intermediate-freuqncy signal in this port as far as possible low to improve intermediate frequency-prevention at radio-frequency port isolation; For input radio frequency signal, the electric capacity C8 being connected on mixing output makes for radiofrequency signal, and transconductance stage output node is equivalent to AC deposition equally, reduces the radio-frequency voltage amplitude of oscillation of this Nodes, improves current utilization efficiency and the linearity.Meanwhile, connect C5, C6 between transconductance stage with mixer stage, blocks the impact of direct current signal; Mixer stage exports and meets C7, and after making mixing, high-frequency signal is filtered.
Illustrate that the present invention has the advantage of high-conversion-gain under 0.6V low supply voltage below by simulation comparison.Adopt
virtuoso simulation software carries out the emulation of frequency mixer conversion gain.Figure 2 shows that the conversion gain simulation result of transconductance-enhancing passive frequency mixer under 0.6V low supply voltage of the present invention, as can be seen from the figure, the conversion gain of this frequency mixer can reach more than 25dB.
Claims (2)
1. a Lower-power-supply-vhigh-conversion-gainpassive high-conversion-gainpassive passive mixer, is characterized in that: comprise input mutual conductance amplifying stage, passive mixing Switch Controller and export across resistance amplifying stage;
Wherein, input mutual conductance amplifying stage comprises the first NMOS tube (NM1) as radio frequency mutual conductance pipe, second NMOS tube (NM2), first PMOS (PM1), second PMOS (PM2), first, second, 5th, 6th resistance (R1, R2, R5, R6), first to fourth electric capacity (C1, C2, C3, C4), for reading the 3rd resistance (R3) and the 4th resistance (R4) of output common mode level, 3rd NMOS tube (NM3) of composition common mode feedback circuit first order current source loads common source amplifying circuit and the 3rd PMOS (PM3), 4th PMOS (PM4) of composition common mode feedback circuit second level ohmic load common source amplifying circuit and the 8th resistance (R8), and form the 7th resistance (R7) and the 5th electric capacity (C5) of RC compensating network,
Passive mixing Switch Controller comprises the 4th to the 7th NMOS tube (NM4, NM5, NM6, NM7), the 6th to the 8th electric capacity (C6, C7, C8);
Export and comprise the 8th across resistance amplifying stage, 9th, 13, 14 NMOS tube (NM8, NM9, NM13, NM14), as the 5th of current source, 7th PMOS (PM5, PM7), with the 12 of the work of common grid mode the, 17 NMOS tube (NM12, NM17), 11, 14 resistance (R11, R14), form the 6th of the first order current source loads common source amplifying circuit of feedback arrangement the, 8th PMOS (PM6, PM8) and be used as current source the tenth, 15 NMOS tube (NM10, NM15), form the 11 of the second level ohmic load common source amplifying circuit of feedback arrangement the, 16 NMOS tube (NM11, NM16) the and ten, 13 resistance (R10, R13), and the 9th of composition RC compensating network the, 12 resistance (R9, R12) the and nine, tenth electric capacity (C9, C10),
Wherein:
The top crown of the first electric capacity (C1) connects input radio frequency signal positive pole, and its bottom crown connects the grid of the first NMOS tube (NM1); The top crown of the second electric capacity (C2) connects input radio frequency signal negative pole, and its bottom crown connects the grid of the second NMOS tube (NM2); The grid of the first NMOS tube (NM1) connects the negative terminal of the first resistance (R1), and its drain electrode connects the anode of the 3rd resistance (R3), its source ground; The grid of the second NMOS tube (NM2) connects the negative terminal of the second resistance (R2), and its drain electrode connects the anode of the 4th resistance (R4), its source ground; The anode of the first resistance (R1) and the second resistance (R2) all connects the first bias voltage (1); The top crown of the 3rd electric capacity (C3) connects the grid of the first NMOS tube (NM1), and its bottom crown connects the grid of the first PMOS (PM1); The top crown of the 4th electric capacity (C4) connects the grid of the second NMOS tube (NM2), and its bottom crown connects the grid of the second PMOS (PM2); The grid of the first PMOS (PM1) connects the negative terminal of the 5th resistance (R5), and its drain electrode connects the anode of the 3rd resistance (R3), and its source electrode connects supply voltage; The grid of the second PMOS (PM2) connects the negative terminal of the 6th resistance (R6), and its drain electrode connects the anode of the 4th resistance (R4), and its source electrode connects supply voltage; The grid of the 3rd NMOS tube (NM3) connects the negative terminal of the 3rd resistance (R3) and the 4th resistance (R4), its source ground, and its drain electrode connects the drain electrode of the 3rd PMOS (PM3); The grid of the 3rd PMOS (PM3) connects the second bias voltage (2), its source ground, and its drain electrode connects the grid of the 4th PMOS (PM4); The grid of the 4th PMOS (PM4) connects the anode of the 7th resistance (R7), and its source electrode connects supply voltage, and its drain electrode connects the anode of the 5th resistance (R5) and the 6th resistance (R6); The drain electrode of the positive termination the 4th PMOS (PM4) of the 8th resistance (R8), its negativing ending grounding; The top crown of the 5th electric capacity (C5) connects the negative terminal of the 7th resistance (R7), its bottom crown ground connection; The top crown of the 6th electric capacity (C6) connects the drain electrode of the first NMOS tube (NM1), and its bottom crown connects the source electrode of the 4th, the 5th NMOS tube (NM4, NM5); The top crown of the 7th electric capacity (C7) connects the drain electrode of the second NMOS tube (NM2), and its bottom crown connects the source electrode of the 6th, the 7th NMOS tube (NM6, NM7); Four, the grid of the 7th NMOS tube (NM4, NM7) connects the positive pole of local oscillation signal, and the grid of the 5th, the 6th NMOS tube (NM5, NM6) connects the negative pole of local oscillation signal; Four, the drain electrode of the 6th NMOS tube (NM4, NM6) connects the top crown of the 8th electric capacity (C8), and the drain electrode of the 5th, the 7th NMOS tube (NM5, NM7) connects the bottom crown of the 8th electric capacity (C8); The grid of the 8th NMOS tube (NM8) connects the negative terminal of the tenth resistance (R10), and its drain electrode connects the drain electrode of the 5th PMOS (PM5), its source ground; The grid of the 5th PMOS (PM5) connects the 3rd bias voltage (3), and its drain electrode connects the grid of the 6th PMOS (PM6), and its source electrode connects supply voltage; The grid of the 6th PMOS (PM6) connects the anode of the 9th resistance (R9), and its drain electrode connects the drain electrode of the tenth NMOS tube (NM10), and its source electrode connects supply voltage; The grid of the tenth NMOS tube (NM10) connects the 4th bias voltage (4), and its drain electrode connects the grid of the 11 NMOS tube (NM11), its source ground; The grid of the 11 NMOS tube (NM11) connects the bottom crown of the 9th electric capacity (C9), and its drain electrode connects the negative terminal of the tenth resistance (R10), its source ground; The top crown of the 9th electric capacity (C9) connects the negative terminal of the 9th resistance (R9), and its bottom crown connects the grid of the 11 NMOS tube (NM11); The positive termination supply voltage of the tenth resistance (R10), its negative terminal connects the grid of the 9th NMOS tube (NM9); The grid of the 9th NMOS tube (NM9) connects the grid of the 8th NMOS tube (NM8), and its drain electrode connects the source electrode of the 12 NMOS tube (NM12), its source ground; The grid of the 12 NMOS tube (NM12) connects the 5th bias voltage (5), and its drain electrode connects output voltage anode, and its source electrode connects the drain electrode of the 9th NMOS tube (NM9); The positive termination supply voltage of the 11 resistance (R11), its negative terminal connects output voltage anode; The grid of the 13 NMOS tube (NM13) connects the negative terminal of the 13 resistance (R13), and its drain electrode connects the drain electrode of the 7th PMOS (PM7), its source ground; The grid of the 7th PMOS (PM7) connects the 3rd bias voltage (3), and its drain electrode connects the grid of the 8th PMOS (PM8), and its source electrode connects supply voltage; The grid of the 8th PMOS (PM8) connects the anode of the 12 resistance (R12), and its drain electrode connects the drain electrode of the 15 NMOS tube (NM15), and its source electrode connects supply voltage; The grid of the 15 NMOS tube (NM15) connects the 4th bias voltage (4), and its drain electrode connects the grid of the 16 NMOS tube (NM16), its source ground; The grid of the 16 NMOS tube (NM16) connects the bottom crown of the tenth electric capacity (C10), and its drain electrode connects the negative terminal of the 13 resistance (R13), its source ground; The top crown of the tenth electric capacity (C10) connects the negative terminal of the 12 resistance (R12), and its bottom crown connects the grid of the 16 NMOS tube (NM16); The positive termination supply voltage of the 13 resistance (R13), its negative terminal connects the grid of the 14 NMOS tube (NM14); The grid of the 14 NMOS tube (NM14) connects the grid of the 13 NMOS tube (NM13), and its drain electrode connects the source electrode of the 17 NMOS tube (NM17), its source ground; The grid of the 17 NMOS tube (NM17) connects the 5th bias voltage (5), and its drain electrode connects output voltage negative terminal, and its source electrode connects the drain electrode of the 14 NMOS tube (NM14); The positive termination supply voltage of the 14 resistance (R14), its negative terminal connects output voltage negative terminal; The top crown of the 8th electric capacity (C8) connects the drain electrode of the 8th NMOS tube (NM8), and the bottom crown of the 8th electric capacity (C8) connects the drain electrode of the 13 NMOS tube (NM13).
2. Lower-power-supply-vhigh-conversion-gainpassive high-conversion-gainpassive passive mixer according to claim 1, it is characterized in that: described first, second, the 5th, the 6th resistance (R1, R2, R5, R6) is biasing resistor, described 11, the 14 resistance (R11, R14) is load resistance, described first to fourth, the 6th, the 7th electric capacity (C1, C2, C3, C4, C6, C7) is coupling capacitance, and described 8th electric capacity (C8) is filter capacitor.
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| CN104702219B (en) * | 2015-03-18 | 2017-11-07 | 东南大学 | A kind of single ended input double balanced passive mixers |
| CN105245190B (en) * | 2015-10-27 | 2017-11-28 | 东南大学 | One kind is without inductance transconductance-enhancing passive frequency mixer |
| CN105356852B (en) * | 2015-11-24 | 2017-12-26 | 广州一芯信息科技有限公司 | A kind of CMOS up-conversions passive frequency mixer |
| CN105553492B (en) * | 2015-12-14 | 2018-01-16 | 东南大学 | A kind of low supply voltage double conversion receiver rf front-end |
| CN106026928B (en) * | 2016-05-13 | 2018-09-07 | 东南大学 | A kind of low-voltage singly balanced current multiplexing passive frequency mixer |
| CN106026930B (en) * | 2016-07-19 | 2018-07-17 | 东南大学 | A kind of low-power consumption high-conversion-gain passive frequency mixer |
| CN109120243B (en) * | 2018-07-23 | 2020-07-07 | 中国电子科技集团公司第二十四研究所 | Clock driving circuit |
| CN116723605B (en) * | 2023-08-10 | 2023-10-31 | 上海芯龙半导体技术股份有限公司 | Compensation circuit of LED power supply and LED power supply |
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