CN103229286B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN103229286B
CN103229286B CN201080070413.7A CN201080070413A CN103229286B CN 103229286 B CN103229286 B CN 103229286B CN 201080070413 A CN201080070413 A CN 201080070413A CN 103229286 B CN103229286 B CN 103229286B
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thickness
surface electrode
area
thickness area
semiconductor device
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CN103229286A (zh
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田中宏明
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Toyota Motor Corp
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Toyota Motor Corp
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Abstract

本说明书所公开的半导体装置具有：半导体基板，其具有形成有半导体元件的元件区域；表面电极，其被形成于半导体基板的元件区域的表面上。表面电极具备第一厚度区域、和与第一厚度区域相比较厚的第二厚度区域，键合线被接合于第二厚度区域。

Description

半导体装置
技术领域
本说明书所记载的技术涉及一种半导体装置。
背景技术
为了对被形成于半导体基板的表面上的表面电极和外部端子进行电连接，而在表面电极的表面上键合接合有键合线。由于在表面电极的键合接合部分处对键合线进行键合接合时所产生的应力，从而位于键合接合部分的下方的表面电极或半导体基板有时会发生破损。为了防止由在键合接合部分处所产生的应力而引起的表面电极或半导体基板的破损，例如，在日本特许公开公报平7-201908号（专利文献1）中，使形成有半导体元件的元件区域、和未形成有半导体元件的虚设元件区域并存，并将键合线接合于被形成在虚设元件区域的表面上的部分的表面电极上。由此，抑制了元件区域发生破损的情况。此外，在日本特许公开公报2002-222826号（专利文献2）中，增厚表面电极整体的厚度，从而缓和在键合接合部分处产生的应力。
在先技术文献
专利文献
专利文献1：日本特开平7-201908号公报
专利文献2：日本特开2002-222826号公报
发明内容
发明所要解决的课题
当如日本特许公开公报平7-201908号那样，为了进行键合接合而设置虚设元件区域时，元件区域相对于半导体基板的基板面积的比例将减小，从而导致半导体装置大型化。此外，当如日本特许公开公报2002-222826号那样，增厚表面电极整体的厚度时，由于表面电极和半导体基板的热膨胀率不同，因此在半导体装置的制造工序中，半导体晶片容易翘曲，从而容易成为产生不良的原因。
用于解决课题的方法
本说明书所公开的半导体装置具有：半导体基板，其具有形成有半导体元件的元件区域；表面电极，其被形成于半导体基板的元件区域的表面上。表面电极具备第一厚度区域、和与第一厚度区域相比较厚的第二厚度区域，键合线被接合于第二厚度区域。
在上述的半导体装置中，键合线被接合于表面电极的第二厚度区域，所述表面电极被形成于半导体基板的元件区域的表面上。由于第二厚度区域与第一厚度区域相比较厚，因此缓和了因对键合线进行接合而在第二厚度区域中产生的应力，从而抑制了半导体装置的破损。即使将键合线接合在被形成于元件表面上的表面电极上，也能够抑制半导体装置的破损。由于表面电极具备与第二厚度区域相比较薄的第一厚度区域，因此抑制了在半导体装置的制造工序中半导体晶片的翘曲的产生。
能够在第一厚度区域与第二厚度区域的边界处设置狭缝部，并且能够将狭缝部的表面电极设定为与第一厚度区域的表面电极相比较薄。当设置有狭缝部时，将能够通过狭缝部，而进一步对半导体装置的制造工序中的半导体晶片的翘曲的产生进行抑制。
附图说明
图1为实施例1的半导体装置的俯视图，并且图示了在表面电极上接合了键合线的状态。
图2为图1中的II-II线剖视图。
图3为表示表面电极的厚度与半导体装置的元件破坏耐性提高率之间的关系的图。
图4为表示实施例1的半导体装置的制造方法的图。
图5为表示实施例1的半导体装置的制造方法的图。
图6为改变例的半导体装置的剖视图。
具体实施方式
本说明书所公开的半导体装置具有：半导体基板，其具有形成有半导体元件的元件区域；表面电极，其被形成于半导体基板的元件区域的表面上。表面电极具备第一厚度区域和第二厚度区域。第二厚度区域的表面电极与第一厚度区域的表面电极相比较厚。键合线被接合于第二厚度区域的表面电极的表面中的至少一部分上。表面电极只要为在其表面上进行键合线的接合的电极则并不被特别地限定，既可以为被形成于半导体基板的主元件区域的表面上的电极，也可以为被设置在检测元件区域的表面上的电极。在半导体装置具有多个进行键合线的接合的表面电极时，优选为，进行键合线的接合的表面电极分别具备第一厚度区域和第二厚度区域。在俯视观察半导体装置时，只需表面电极和键合线相接合的接合区域被包含在第二厚度区域中即可。当表面电极具有多个第二厚度区域时，既可以在多个第二厚度区域中的至少一个第二厚度区域的表面上接合键合线，也可以在该所有的第二厚度区域的表面上接合键合线。键合线的形状既可以为金属线等的线状，也可以为带状或条状。半导体装置只需为将键合线接合在表面电极上的半导体装置即可，并不被形成于半导体基板上的半导体元件的种类（例如，IGBT（绝缘栅双极性晶体管）、MOS（金属氧化物半导体）、二极管）所限定。
实施例1
如图1及图2所示，半导体装置10具备半导体基板100、被形成于半导体基板100的表面上的表面电极121～123、和被形成于半导体基板100的背面上的背面电极130。表面电极121～123和背面电极130以金属为主要成分。半导体基板100具备多个形成有半导体元件的主元件区域111～113、和未形成有半导体元件的非元件区域102。表面电极121～123被形成于主元件区域111～113的表面上。表面电极121～123的一部分也可以延伸至非元件区域102的表面上。另外，虽然未图示，但在半导体装置10的表面上具备栅极衬垫，而且还可以具备检测衬垫等小信号衬垫。
如图2所示，在半导体基板100的主元件区域113中，形成有沟槽栅型的IGBT。在主元件区域113中，从其背面侧起具备有集电层11、漂移层12、体层13，并且在体层13的表面的一部分上形成有发射层14。体层13和发射层14与表面电极123电连接。沟槽栅极15从半导体基板100的表面侧起贯穿发射层14和体层13而到达漂移层12。在沟槽栅极15的内部填充有被绝缘膜所覆盖的栅电极。栅电极通过绝缘膜16而与表面电极123绝缘。另外，与主元件区域113相同地，在主元件区域111、112中也形成有沟槽栅型的IGBT。表面电极121～123为，各个主元件区域111～113的主发射电极。
表面电极121～123具备第二厚度区域121a～121d、122a～122d、123a～123d、和第一厚度区域121e、122e、123e。在第二厚度区域121a～121d、122a～122d、123a～123d的表面上分别键合接合有键合线221～226。键合线221～226为金属线。在俯视观察半导体装置时，第二厚度区域121a～121d、122a～122d、123a～123d为长方形。在第二厚度区域121a～121d、122a～122d、123a～123d的表面的中央部处接合有键合线221～226。键合线221被键合接合在位于其下方的第二厚度区域121a和第二厚度区域121c的表面上，并且在第二厚度区域121a与第二厚度区域121c之间的区域，向上方弯曲。键合线222～226也是同样地被键合接合在位于各自的下方的第二厚度区域121b、121d、122a～122d、123a～123d的表面上，并且在各个键合线所接合的第二厚度区域之间的区域，向上方弯曲。在第一厚度区域121e、122e、123e上未接合有键合线。第二厚度区域121的表面电极的厚度W2与第一厚度区域122的表面电极的厚度W1相比较厚（W2＞W1）。
图3图示了对表面电极的厚度与半导体装置的元件破坏耐性提高率之间的关系进行了研究后的结果。另外，作为表面电极而使用铝电极，并利用超声波接合技术而将键合线接合在被形成于半导体基板的元件区域的表面上的、表面电极的表面上。横轴表示表面电极的厚度，且表示相对于现有的表面电极的厚度之比。纵轴表示半导体装置的元件破坏耐性提高率。元件破坏耐性提高率用百分比来表示如下数值，即，在以预定的键合压实施了引线键合时，预定厚度的表面电极的半导体装置的元件被破坏的个数的比例，除以表面电极的厚度为现有的厚度的半导体装置的元件被破坏的个数的比例而得到的数值。如图3所示，表面电极的厚度越增厚，则半导体装置的元件破坏耐性提高率越提高。例如，在表面电极厚度为1.4倍时，元件破坏耐性提高率增高2%，在表面电极厚度为1.8倍时，元件破坏耐性提高率增高9%。可认为图3所示的结果示出了：表面电极的厚度越增厚，则对在如下区域中所产生的应力进行缓和的效果越高，从而半导体装置的元件破坏耐性提高率越进一步增高，所述区域为，将键合线键合接合在表面电极上的区域。
另一方面，当增厚表面电极整体的厚度时，由于表面电极和半导体基板的热膨胀率不同，因此在半导体装置的制造工序中，半导体晶片变得容易翘曲，容易成为产生不良的原因。近年来，半导体晶片被薄板化的倾向较为显著，例如有时会被薄板化至厚度为100～200μm的程度。半导体晶片的厚度越薄，则半导体晶片越容易翘曲。
在本实施例中，由于表面电极的第二厚度区域与表面电极的第一厚度区域相比较厚，因此缓和了在第二厚度区域中产生的应力。由于表面电极具备与第二厚度区域相比较薄的第一厚度区域，因此抑制了在半导体装置的制造工序中半导体晶片的翘曲的产生。能够在提高半导体装置的元件破坏耐性的同时，抑制半导体晶片的翘曲的产生。由于缓和了在半导体装置的第二厚度区域中产生的应力，因此能够将键合线键合接合在被形成于元件区域的表面上的表面电极上，从而能够使半导体装置小型化。
另外，在对键合线进行超声波接合时，为了提高键合的强度，W2/W1优选为大于等于1.2。此外，从表面电极的制造容易度的观点出发，W2/W1优选为小于等于2.0。
通过图4、图5所示的制造方法，从而能够容易地制造出表面电极123，所述表面电极123具备厚度为W2的第二厚度区域123a等和厚度为W1的第一厚度区域123e等。首先，如图4所示，在半导体基板100的表面上形成厚度同样为W2的表面电极膜323。接下来，形成抗蚀层330，所述抗蚀层330被图案形成为，对表面电极膜323的成为第二厚度区域123a等的部分的表面进行覆盖。当在该状态下进行蚀刻时，未被抗蚀层330覆盖的部分（成为第一厚度区域123e等的部分）的表面电极膜323将被去除。由此，如图5所示，能够形成厚度为W2的第二厚度区域123a等、和厚度为W1的第一厚度区域123e等。
（改变例）
如图6所示，也可以在第一厚度区域123e与第二厚度区域123a的边界处，设置狭缝部141。狭缝部141既可以被形成在第一厚度区域123e与第二厚度区域123a的边界的一部分上，也可以以包围第二厚度区域123a的周围的方式而被形成在第一厚度区域123e与第二厚度区域123a的整个边界上。通过设置狭缝部，从而提高了对半导体装置的制造工序中的晶片的翘曲进行缓和的效果。例如，如图6所示，能够通过使第二厚度区域123a与第一厚度区域123e的边界处的表面电极123的厚度与第一厚度区域123e相比薄W3，从而形成狭缝部141。在这种情况下，优选为，狭缝部141处的表面电极123的厚度（W1－W3）大于等于1μm。
另外，虽然在上述的实施例及改变例中，在俯视观察半导体装置时，第二厚度区域为长方形形状，但并不限于此，既可以为圆形、椭圆形、三角形、其他的多边形形状，也可以为不规则图形。此外，当在半导体装置的表面上还具备栅极衬垫、或检测衬垫等小信号衬垫时，栅极衬垫或小信号衬垫可以为具备本发明所涉及的第一厚度区域和第二厚度区域的表面电极，并且在该第二厚度区域上接合有键合线。此外，虽然在上述的实施例及改变例中，例示了在多个第二厚度区域的任意区域上均接合有键合线的情况而进行了说明，但也可以不在多个第二厚度区域的所有区域上接合有键合线。
以上，虽然对本发明的实施例进行了详细说明，但这些实施例只不过是示例，并不对权利要求的范围进行限定。在权利要求书中所记载的技术中包含对以上所例示的具体示例进行了各种各样的变形及变更后的技术。
本说明书或附图中所说明的技术要素是以单独或者各种组合的形式而发挥技术上的有用性的，其并不限定于申请时权利要求中所记载的组合。此外，本说明书或附图中所例示的技术是能够同时达成多个目的的技术，且达成其中一个目的本身也具有技术上的有用性。

Claims (3)

1.一种半导体装置，具有：
半导体基板，其具有形成有半导体元件的元件区域；
表面电极，其被形成于半导体基板的元件区域的表面上，
表面电极具备第一厚度区域、和与第一厚度区域相比较厚的第二厚度区域，
所述第一厚度区域的上表面低于所述第二厚度区域的上表面，键合线被接合于第二厚度区域，以及
在表面电极的第一厚度区域与第二厚度区域的边界处，设置有狭缝部。
2.如权利要求1所述的半导体装置，其中，
表面电极的狭缝部的厚度与第一厚度区域的厚度相比较薄。
3.如权利要求1或2所述的半导体装置，其中，
键合线通过超声波键合而被接合于表面电极。
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Family Cites Families (15)

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JPS6119136A (ja) 1984-07-05 1986-01-28 Toshiba Corp 半導体装置のワイヤボンデイング方法およびこれに用いるボンデイングパツド
JPS63141330A (ja) * 1986-12-03 1988-06-13 Nec Corp 半導体集積回路装置
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JPH06350379A (ja) * 1993-06-03 1994-12-22 Tdk Corp 弾性表面波素子リードワイヤ取付部構造
DE69321966T2 (de) 1993-12-24 1999-06-02 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno, Catania Leistungs-Halbleiterbauelement
JP2000323519A (ja) 1999-05-07 2000-11-24 Nec Ic Microcomput Syst Ltd 半導体集積回路装置
JP4221904B2 (ja) 2001-01-29 2009-02-12 富士電機デバイステクノロジー株式会社 半導体装置およびその製造方法
JP3719994B2 (ja) * 2001-12-28 2005-11-24 株式会社東芝 半導体装置
JP4060093B2 (ja) 2002-02-28 2008-03-12 Ｔｄｋ株式会社 除電装置
JP2004111885A (ja) 2002-07-23 2004-04-08 Toshiba Corp 半導体装置
JP4777899B2 (ja) * 2004-10-29 2011-09-21 スパンション エルエルシー 半導体装置
JP4533804B2 (ja) * 2005-06-02 2010-09-01 セイコーエプソン株式会社 半導体装置及びその製造方法
JP2007035909A (ja) 2005-07-27 2007-02-08 Seiko Epson Corp 電子デバイスおよび電子デバイスの製造方法
JP2010062362A (ja) 2008-09-04 2010-03-18 Toyota Motor Corp 半導体装置とその製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1988137A (zh) * 2005-12-19 2007-06-27 三菱电机株式会社 半导体装置

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CF01 Termination of patent right due to non-payment of annual fee