CN103178029A - 半导体芯片和具有其的堆叠半导体封装体 - Google Patents

半导体芯片和具有其的堆叠半导体封装体 Download PDF

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CN103178029A
CN103178029A CN2012104778658A CN201210477865A CN103178029A CN 103178029 A CN103178029 A CN 103178029A CN 2012104778658 A CN2012104778658 A CN 2012104778658A CN 201210477865 A CN201210477865 A CN 201210477865A CN 103178029 A CN103178029 A CN 103178029A
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dielectric layer
semiconductor chip
layer
air gap
electrode
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CN103178029B (zh
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孙晧荣
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Mimi Ip Co ltd
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Hynix Semiconductor Inc
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Abstract

本发明公开了一种半导体芯片和堆叠半导体封装体。该半导体芯片包括基板、穿过基板的贯通电极和形成在基板与贯通电极之间且具有介电常数减小结构的介电层。

Description

半导体芯片和具有其的堆叠半导体封装体
技术领域
本发明涉及半导体装置，更具体涉及半导体芯片以及具有其的堆叠半导体封装体。
背景技术
不断开发半导体装置的封装技术以满足小型化和高容量的要求。近来，在现有技术中提出了堆叠半导体封装体的各种技术，以改善小型化、容量和安装效率。
半导体工业中所称的术语“堆叠”是指垂直堆叠至少两个半导体芯片或封装体。在存储装置的情况下，通过堆叠半导体芯片或封装体能够实现的产品的存储容量大于通过半导体集成工艺获得的产品的存储容量，并且堆叠也可改善安装面积的利用效率。
作为堆叠半导体封装体的示例，已经提出采用贯通电极的结构。采用贯通电极的堆叠半导体封装体的优点在于，因为通过贯通电极形成电连接，所以可提高半导体装置的运行速度，并且小型化也是可能的。
然而，由于半导体芯片与贯通电极之间的寄生电容，信号传输速度下降，构成堆叠的半导体芯片之间的运行速度差异增加，并且功率噪声的增加，导致电特性劣化。
发明内容
本发明的实施例涉及半导体芯片，该半导体芯片适合于减小半导体芯片和贯通电极之间的寄生电容。
而且，本发明的实施例涉及采用半导体芯片的堆叠半导体封装体。
在本发明的一个实施例中，半导体芯片包括：基板；穿过基板的贯通电极；以及介电层，形成在基板和贯通电极之间且具有介电常数减小结构。
具有介电常数减小结构的介电层可包括空心型介电层，其具有限定在其中心部分中的空气间隙。空心型介电层的材料可包括选自氧化硅层、氮化硅层、氮氧化硅层、聚酰亚胺、BCB（苯并环丁烯）和聚对二甲苯中的任何一种。
具有介电常数减小结构的介电层可包括其中具有多个空气间隙的多孔介电层。多孔介电层的材料可包括氧化硅层、氮化硅层、氮氧化硅层、HSSQ（氢硅倍半氧烷）和MSSQ（甲基硅倍半氧烷）中的任何一种。
具有介电常数减小结构的介电层可包括空心型介电层和无空气间隙介电层的双层结构，空心型介电层具有限定在其中心部分中的空气间隙，无空气间隙介电层中没有空气间隙。空心型介电层和无空气间隙介电层的材料可包括选自氧化硅层、氮化硅层、氮氧化硅层、聚酰亚胺、BCB和聚对二甲苯中的任何一种。
具有介电常数减小结构的介电层可包括多孔介电层和无空气间隙介电层的双层结构，多孔介电层中具有多个空气间隙，无空气间隙介电层中没有空气间隙。多孔介电层的材料可包括选自氧化硅层、氮化硅层、氮氧化硅层、HSSQ和MSSQ中的任何一种，无空气间隙介电层的材料可包括选自氧化硅层、氮化硅层、氮氧化硅层、聚酰亚胺、BCB和聚对二甲苯中的任何一种。
具有介电常数减小结构的介电层可包括空心型介电层和多孔介电层的双层结构，空心型介电层具有限定在其中心部分中的空气间隙，多孔介电层中具有多个空气间隙。空心型介电层的材料可包括选自氧化硅层、氮化硅层、氮氧化硅层、聚酰亚胺、BCB和聚对二甲苯中的任何一种，而多孔介电层的材料可包括选自氧化硅层、氮化硅层、氮氧化硅层、HSSQ和MSSQ中的任何一种。
在本发明的另一个实施例中，堆叠半导体封装体包括：多个半导体芯片，其每一个都包括基板、穿过基板的贯通电极以及形成在基板与贯通电极之间且具有介电常数减小结构的介电层，并且堆叠为使得多个半导体芯片的贯通电极彼此连接。
堆叠半导体封装体还可包括：第一介电层，形成在多个堆叠半导体芯片当中的最下面的半导体芯片下方使得最下面的半导体芯片的贯通电极被暴露；重分配线，形成在第一介电层下方并且与最下面的半导体芯片的暴露的贯通电极电连接；以及第二介电层，形成在包括重分配线的第一介电层下方使得重分配线的一部分被暴露。此外，堆叠半导体封装体还可包括外部连接端子，其安装到重分配线的通过第二介电层暴露的部分。
堆叠半导体封装体还可包括结构体，其支撑半导体芯片且具有连接电极，该连接电极与多个堆叠半导体芯片当中的最下面的半导体芯片的贯通电极电连接。结构体可包括印刷电路板、***体和半导体封装体中的任何一种。
在半导体芯片当中，最下面的半导体芯片的具有介电常数减小结构的介电层可具有最高的介电常数，具有介电常数减小结构的介电层的介电常数可朝着最上面的半导体芯片逐渐减小，并且最上面的半导体芯片的具有介电常数减小结构的介电层可具有最低的介电常数。
半导体芯片可包括第一半导体芯片、堆叠在第一半导体芯片下方的第二半导体芯片以及堆叠在第二半导体芯片下方的第三半导体芯片；第一半导体芯片的介电层可包括其中具有多个空气间隙的多孔介电层和其中没有空气间隙的无空气间隙介电层的双层结构，第二半导体芯片的介电层可包括其中具有多个空气间隙的多孔介电层的单层结构，并且第三半导体芯片的介电层可包括具有限定在其中心部分中的空气间隙的空心型介电层的单层结构。
附图说明
图1是示出根据本发明第一实施例的半导体芯片的截面图。
图2是示出根据本发明第二实施例的半导体芯片的截面图。
图3是示出根据本发明第三实施例的半导体芯片的截面图。
图4是示出根据本发明第四实施例的半导体芯片的截面图。
图5是示出根据本发明第五实施例的半导体芯片的截面图。
图6是示出根据本发明第六实施例的堆叠半导体封装体的截面图。
图7是示出根据本发明第七实施例的堆叠半导体封装体的截面图。
图8是示出根据本发明第八实施例的堆叠半导体封装体的截面图。
图9是示出根据本发明第九实施例的堆叠半导体封装体的截面图。
图10是示出根据本发明第十实施例的堆叠半导体封装体的截面图。
图11是示出包括根据本发明实施例的半导体芯片的电子设备的立体图。
图12是示出包括根据本发明实施例的半导体芯片的电子***的示例的模块图。
具体实施方式
以下，将参考附图详细描述本发明的具体实施例。
这里应当理解的是，附图不必按比例，并且在某些情况下比例可被夸大，以更加清楚地示出本发明的某些特征。
图1是示出根据本发明第一实施例的半导体芯片的截面图。
参见图1，根据本发明第一实施例的半导体芯片10A包括基板100、贯通电极200和具有介电常数减小结构的介电层300。
基板100具有第一表面110、第二表面120和电路单元130。
第一表面110背对第二表面120，并且电路单元130形成在第一表面110上。电路单元130例如包括诸如晶体管、电容器和电阻器的元件，以存储和处理数据。
贯通电极200穿过基板100的第一表面110和第二表面120。每个贯通电极200都可具有从上面看的圆形截面形状。每个贯通电极200还可具有椭圆、四边形或五边形的截面形状。贯通电极200可由诸如铜或钨的材料制成。
具有介电常数减小结构的介电层300形成在基板100与贯通电极200之间。在本实施例中，具有介电常数减小结构的介电层300形成为空心型介电层310，该空心型介电层310具有限定在其中心部分中的空气间隙A。
空心型介电层310可由包括选自氧化硅,氮化硅、氮氧化硅层、聚酰亚胺、BCB（苯并环丁烯（benzocyclobutene））和聚对二甲苯（parylene）当中的任何一种的材料制成。
空心型介电层310可通过限定环形孔（其中该环形孔围绕每个贯通电极200）以及采用具有不好的台阶覆盖特性的沉积法沉积介电层而形成。例如，PECVD（等离子体增强化学气相沉积）法可用于沉积介电层，堵塞第一表面110和第二表面120中的孔的入口，但是不完全填充构成空心型介电层330的孔，而是使空气间隙A保留在空心型介电层330中使得环形孔围绕贯通电极200。
空气间隙A的介电常数为1.0，并且对应于介电常数为3.9的氧化硅的介电常数的约1/4。因此，空心型介电层310的介电常数低于实心氧化硅层的介电常数3.9，并且空心型介电层310的介电常数高于空气间隙A的介电常数1.0。由于空气间隙A填充空心型介电层310中较高百分比（%）的空间，空心型介电层310的介电常数降低。
图2是示出根据本发明第二实施例的半导体芯片的截面图。
根据本发明第二实施例的半导体芯片10B的构造中，具有介电常数减小结构的介电层300的形式不同于参考图1描述的第一实施例的半导体芯片10A的介电层300的形式。另外，除了具有介电常数减小结构的介电层300之外，根据本发明第二实施例的半导体芯片具有与根据第一实施例的半导体芯片10A基本相同的构造。因此，这里将省略相同构件部分的重复描述，并且相同的术语和相同的参考标号将用于表示相同的构件部分。
参见图2，在本实施例中，具有介电常数减小结构的介电层300形成为其中具有多个空气间隙A的多孔介电层320。
多孔介电层320可由包括氧化硅、氮化硅、氮氧化硅、HSSQ（氢硅倍半氧烷（hydro silsesquioxane））和MSSQ（甲基硅倍半氧烷（methylsilsesquioxane））中任何一种的材料制成。
图3是示出根据本发明第三实施例的半导体芯片的截面图。
根据本发明第三实施例的半导体芯片10C的构造中，具有介电常数减小结构的介电层300的结构与参考图1描述的第一实施例的半导体芯片10A的介电层300的形式不同。因此，除了具有介电常数减小结构的介电层300之外，根据本发明第三实施例的半导体芯片具有与根据第一实施例的半导体芯片10A基本相同的构造。因此，这里将省略相同构件部分的重复描述，并且相同的术语和相同的参考标号将用于表示相同的构件部分。
参见图3，在本实施例中，具有介电常数减小结构的介电层300具有多孔介电层320和无空气间隙介电层330的双层结构，多孔介电层320中具有多个空气间隙A，无空气间隙介电层330中没有空气间隙。
多孔介电层320可由包括氧化硅、氮化硅层、氮氧化硅层、HSSQ和MSSQ中任何一种的材料制成。无空气间隙介电层330可由包括选自氧化硅、氮化硅、氮氧化硅、聚酰亚胺、BCB和聚对二甲苯当中任何一种的材料制成。
图4是示出根据本发明第四实施例的半导体芯片的截面图。
根据本发明第四实施例的半导体芯片10D的构造中，具有介电常数减小结构的介电层300的形式与参考图1描述的第一实施例的半导体芯片10A的介电层300的形式不同。因此，除了具有介电常数减小结构的介电层300之外，根据本发明第四实施例的半导体芯片具有与根据第一实施例的半导体芯片10A基本相同的构造。因此，这里将省略相同构件部分的重复描述，并且相同的术语和相同的参考标号将用于表示相同的构件部分。
参见图4，在本实施例中，具有介电常数减小结构的介电层300具有空心型介电层310和无空气间隙介电层330的双层结构，空心型介电层310具有限定在其中心部分中的空气间隙A，无空气间隙介电层330中没有空气间隙。空气间隙A可形成环形孔，该环形孔围绕贯穿硅通路200和无空气间隙介电层330。
空心型介电层310和无空气间隙介电层330可由包括选自氧化硅、氮化硅、氮氧化硅、聚酰亚胺、BCB和聚对二甲苯当中的任何一种的材料制成。
图5是示出根据本发明第五实施例的半导体芯片的截面图。
根据本发明第五实施例的半导体芯片10E的构造中，具有介电常数减小结构的介电层300的结构与上面参考图1描述的第一实施例半导体芯片10A不同。因此，除了具有介电常数减小结构的介电层300之外，根据本发明第五实施例的半导体芯片具有与第一实施例的半导体芯片10A基本相同的构造。因此，这里将省略相同构件部分的重复描述，并且相同的术语和相同的参考标号将用于表示相同的构件部分。
参见图5，在本实施例中，具有介电常数减小结构的介电层300具有空心型介电层310和多孔介电层320的双层结构，空心型介电层310具有限定在其中心部分中的空气间隙A，多孔介电层320中具有多个空气间隙A，多孔介电层320中的空气间隙A可小于空心型介电层310内的空气间隙A。
空心型介电层310可由包括选自氧化硅层、氮化硅层、氮氧化硅层、聚酰亚胺、BCB和聚对二甲苯当中任何一种的材料制成。多孔介电层320可由包括氧化硅、氮化硅、氮氧化硅层、HSSQ和MSSQ的任何一种的材料制成。
以下，将描述包括上述半导体芯片的堆叠半导体封装体。
图6是示出根据本发明第六实施例的堆叠半导体封装体的截面图。在一个示例中，堆叠半导体封装体可包括基本类似于图1所示半导体芯片10A的半导体芯片。
参见图6，在制备了包括贯通电极200和具有介电常数减小结构的介电层300的半导体芯片10Ai-10Aiii之后，第二半导体芯片10Aii的贯通电极200借助于连接构件20连接到第一半导体芯片10Ai的贯通电极200。这样，多个半导体芯片10Ai-10Aiii，例如三个半导体芯片10Ai-10Aiii彼此上下堆叠。粘合剂构件30形成在堆叠的半导体芯片10Ai-10Aiii之间，以使第一半导体芯片10Ai和第二半导体芯片10Aii彼此粘合，并且使得第二半导体芯片10Aii和第三半导体芯片10Aiii彼此粘合。连接构件20可包括焊料，并且粘合剂构件30可包括非导电膏。
第一介电层40形成在位于堆叠的半导体芯片10Ai-10Aiii当中最下面的第三半导体芯片10Aiii的下表面下方，使得最下半导体芯片10Aiii的贯通电极200被暴露，并且与最下面的半导体芯片10Aiii的贯通电极200电连接的重分配线50形成在第一介电层40下方。第二介电层60形成在包括重分配线50的第一介电层40下方，使得重分配线50的一部分被暴露，并且外部连接端子70安装到重分配线50的通过第二介电层60暴露的部分。
图7是示出根据本发明第七实施例的堆叠半导体封装体的截面图。
参见图7，在制备包括贯通电极200和具有介电常数减小结构的介电层300的半导体芯片10Ai-10Aiii后，第一半导体芯片10Ai的贯通电极200和第二半导体芯片10Aii的贯通电极200借助于连接构件20彼此连接。类似地，第二半导体芯片10Aii的贯通电极200和第三半导体芯片10Aiii的贯通电极200也借助于连接构件20彼此连接。这样，多个半导体芯片10Ai-10Aiii，例如三个半导体芯片10Ai-10Aiii，彼此上下堆叠。粘合剂构件30形成在堆叠的半导体芯片10Ai和10Aii之间，并且粘合剂构件30也形成在堆叠的半导体芯片10Aii和10Aiii之间。连接构件20可包括焊料，并且粘合剂构件30可包括非导电膏。
堆叠的半导体芯片10Ai-10Aiii安装到结构体80使得位于堆叠的半导体芯片10Ai-10Aiii当中最下面的第三半导体芯片10Aiii的贯通电极200与结构体80的连接电极82连接。在本实施例中，结构体80由印刷电路板（PCB）构成。
第三半导体芯片10Aiii的贯通电极200和结构体80的连接电极82通过连接构件90彼此电连接。为了改善连接的可靠性，底填构件92填充在第三芯片10Aiii与结构体80之间。
包括堆叠半导体芯片10A的结构体80的上表面由模制构件94密封。参考标号84表示球焊盘，并且参考标号86表示用作外部连接端子的焊料球。
尽管在上面参考图7描述的第七实施例中说明了结构体80由印刷电路板（PCB）构成，但是结构体80也可由半导体封装体或***体构成。下面，将参考图8和9描述采用半导体封装体和***体的堆叠半导体封装体。
图8是示出根据本发明第八实施例的堆叠半导体封装体的截面图。
根据本发明第八实施例的堆叠半导体封装体的构造中，用作如第七实施例所示的结构体80的印刷电路板以半导体封装体替换。因此，除了结构体80之外，根据本发明第八实施例的堆叠半导体封装体具有与根据第七实施例的堆叠半导体封装体相同的构造。因此，相同的术语和相同的参考标号将用于表示相同的构件部分。
参见图8，在制备包括贯通电极200和具有介电常数减小结构的介电层300的半导体芯片10Ai-10Aiii之后，第一半导体芯片10Ai的贯通电极200和第二半导体芯片10Aii的贯通电极200借助于连接构件20彼此连接，并且第二半导体芯片10Aii的贯通电极200和第三半导体芯片10Aiii的贯通电极200借助于连接构件20彼此连接。这样，多个半导体芯片10Ai-10Aiii，例如三个半导体芯片10Ai-10Aiii，彼此上下堆叠。粘合剂构件30形成在堆叠的半导体芯片10Ai和10Aii以及10Aii和10Aiii之间。连接构件20可包括焊料，并且粘合剂构件30可包括非导电膏。
堆叠的半导体芯片10A安装到结构体80使得位于堆叠半导体芯片10Ai-10Aiii当中最下面的第三半导体芯片10Aiii的贯通电极200与结构体80的连接电极411连接。在本实施例中，结构体80由半导体封装体构成。
半导体封装体包括基板410和第一半导体芯片420，基板410具有在其上表面上的连接电极411和在其下表面上的球焊盘412，第一半导体芯片420安装在基板410的在连接电极411以内的上表面上。第一半导体芯片420采用配线430与基板410电连接，并且由模制构件440密封。参考标号450表示外部连接端子，其安装到基板410的球焊盘412。
第三半导体芯片10Aiii的贯通电极200和结构体80的连接电极411借助于连接构件500彼此连接。在本实施例中，连接构件500形成为焊料球。连接构件500也可形成为引线。
图9是示出根据本发明第九实施例的堆叠半导体封装体的截面图。
根据本发明第九实施例的堆叠半导体封装体的构造中，用作图7所示第七实施例的结构体80的印刷电路板以***体替代。因此，除了结构体80之外，根据本发明第九实施例的堆叠半导体封装体具有与根据第七实施例的堆叠半导体封装体基本相同的构造。因此，相同的术语和相同的参考标号将用于表示相同的构件部分。
参见图9，在制备包括贯通电极200和具有介电常数减小结构的介电层300的半导体芯片10Ai-10Aiii之后，第一半导体芯片10Ai的贯通电极200和第二半导体芯片10Aii的贯通电极200借助于连接构件20彼此连接，并且第二半导体芯片10Aii的贯通电极200和第三半导体芯片10Aiii的贯通电极200也借助于连接构件20彼此连接。这样，多个半导体芯片10Ai-10Aiii，例如三个半导体芯片10Ai-10Aiii，彼此上下堆叠。粘合剂构件30形成在堆叠半导体芯片10A之间。连接构件20可包括焊料，并且粘合剂构件30可包括非导电膏。
堆叠的半导体芯片10Ai-10Aiii安装到结构体80使得位于堆叠半导体芯片10Ai-10Aiii当中最下面的第三半导体芯片10Aiii的贯通电极200与结构体80的连接电极620连接。在本实施例中，结构体80由***体构成。
***体包括***本体610和连接电极620，连接电极620使***本体610的上表面和下表面彼此连接。
第三芯片10Aiii的贯通电极200和结构体80的连接电极620借助于连接构件630彼此连接。
尽管图中没有示出，但是在堆叠的半导体芯片10Ai-10Aiii安装到***体之后，堆叠的半导体芯片10Ai-10Aiii借助于***体连接到另一个半导体结构，例如，半导体封装体或主板。
尽管在参考图6至9描述的实施例中说明了堆叠半导体封装体通过堆叠每一个都如图1所示的多个半导体芯片10A构成，但是应当注意的是，本发明不限于此，而是堆叠半导体封装体可通过堆叠多个任意的图2至5所示的半导体芯片10B、10C、10D和10E来取代图1所示的半导体芯片10A而构成，或者通过堆叠图1至5所示的半导体芯片10A、10B、10C、10D和10E当中的两种或更多种半导体芯片而构成。
图10是示出根据本发明第十实施例的堆叠半导体封装体的截面图。
与上面参考图6至9所述的根据第六至第九实施例的堆叠半导体封装体不同，根据本发明第十实施例的堆叠半导体封装体的构造中，彼此上下堆叠的半导体芯片具有介电常数减小结构不同的介电层300。因此，除了每个半导体芯片10A、10B、10C的介电层300具有不同的介电常数减小结构之外，根据本发明第十实施例的堆叠半导体封装体具有与根据第六至第九实施例的堆叠半导体封装体基本相同的构造。因此，相同的术语和相同的参考标号将用于表示相同的构件部分。
参见图10，在本实施例中，堆叠半导体封装体包括第一至第三半导体芯片10A、10B和10C。此外，堆叠半导体封装体还包括第一和第二介电层40和60、重分配线50以及外部连接端子70。
第一至第三半导体芯片10A、10B和10C的每一个都包括基板100、贯通电极200以及具有介电常数减小结构的介电层300。
第二半导体芯片10B堆叠在第三半导体芯片10C上使得第三半导体芯片10C的贯通电极200与第二半导体芯片10B的贯通电极200连接，并且第一半导体芯片10A堆叠在第二半导体芯片10B上使得第二半导体芯片10B的贯通电极200与第一半导体芯片10A的贯通电极200连接。
第一半导体芯片10A的贯通电极200和第二半导体芯片10B的贯通电极200以及第二半导体芯片10B的贯通电极200和第三半导体芯片10C的贯通电极200借助于连接构件20彼此电连接。粘合剂构件30形成在堆叠的第一半导体芯片10A、第二半导体芯片10B和第三半导体芯片10C之间，以使第一半导体芯片10A、第二半导体芯片10B和第三半导体芯片10C彼此上下贴合。连接构件20可包括焊料，并且粘合剂构件30可包括非导电膏。
在本实施例中，位于最下面的第三半导体芯片10C的具有介电常数减小结构的介电层300具有最高的介电常数。具有介电常数减小结构的介电层300的介电常数朝着最上面的半导体芯片逐渐减小，从而位于最上面的第一半导体芯片10A的具有介电常数减小结构的介电层300具有最低的介电常数。
例如，第三半导体芯片10C的具有介电常数减小结构的介电层300可具有多孔介电层320和无空气间隙介电层330的双层结构，多孔介电层320中具有多个空气间隙A，无空气间隙介电层330中没有空气间隙，第二半导体芯片10B的具有介电常数减小结构的介电层300可具有其中具有多个空气间隙A的多孔介电层320的单层结构，而第一半导体芯片10A的具有介电常数减小结构的介电层300可具有空心型介电层310的单层结构，空心型介电层310具有限定在其中心部分中的空气间隙A。
第一介电层40形成在第三半导体芯片10C的下表面下方使得第三半导体芯片10C的贯通电极200被暴露。此外，与第三半导体芯片10C的贯通电极200电连接的重分配线50形成在第一介电层40下方。第二介电层60形成在包括重分配线50的第一介电层40下方使得重分配线50的一部分被暴露。外部连接端子70安装到重分配线50的通过第二介电层60暴露的部分。
在本实施例中，由于具有介电常数减小结构的介电层300的介电常数从最下面的半导体芯片朝着最上面的半导体芯片逐渐减小，半导体芯片100和贯通电极200之间的寄生电容从最下面的半导体芯片朝着最上面的半导体芯片逐渐减小。结果，上、下半导体芯片之间的运行速度的差异减小，并且改善了功率噪声减小效果。此外，例如图1至5所示的具有介电常数减小结构的介电层300的各种实施例改善了半导体芯片和贯通电极之间的寄生电容的问题。
上述半导体芯片和堆叠半导体封装体可应用于各种封装体模块。
图11是示出包括根据本发明的半导体芯片的电子设备的立体图。
参见图11，根据本发明实施例的半导体芯片可应用于诸如便携式电话的电子设备1000。因为根据本发明实施例的半导体芯片在可靠性方面是优良的，所以有利于改善电子设备1000的性能。电子设备1000不限于图11所示的便携式电话，而是可包括各种电子应用，例如，诸如移动电子应用、膝上计算机、笔记本计算机、便携式多媒体播放机（PMP）、MP3播放机、便携式摄像机、网络写字板、无线电话、导航仪、个人数字助理（PDA），等等。
图12是示出包括根据本发明的半导体芯片的电子***的示例的模块图。
参见图12，电子***1300可包括控制器1310、输入/输出单元1320和存储器1330。控制器1310、输入/输出单元1320和存储器1330可通过母线1350彼此连接。母线1350用作数据通过其移动的通道。例如，控制器1310可至少包括至少一个微处理器、至少一个数字信号处理器、至少一个微控制器和能执行这些部件的相同功能的逻辑装置中的任何一种。控制器1310和存储器1330可包括根据本发明实施例的半导体芯片。输入/输出单元1320可包括选自键区（keypad）、键盘、显示装置等中的至少一种。存储器1330是用于存储数据的装置。存储器1330可存储控制器1310等要执行的指令和/或数据。存储器1330可包括易失性存储装置和/或非易失性存储装置。另外，存储器1330可由闪存构成。例如，应用根据本发明的技术的闪存可安装到诸如移动终端或台式计算机的信息处理***。闪存可由半导体盘装置（SSD）构成。在此情况下，电子***1300可在闪存***中稳定地存储大量的数据。电子***1300还可包括接口1340，其构造为传输数据到通信网络和从通信网络接收数据。接口1340可为有线型或无线型。例如，接口1340可包括天线或者有线或无线收发器。此外，尽管没有示出，但是本领域的技术人员应容易理解电子***1300可附加地提供有应用芯片组、照相机图像处理器（CIS）、输入/输出单元等。
尽管为了说明的目的已经描述了本发明的具体实施例，但是本领域的技术人员应理解，在不脱离所附权利要求中揭示的本发明的范围和精神的情况下，各种变型、添加和替换是可能的。
本申请要求2011年12月22日提交韩国知识产权局的韩国专利申请号第10-2011-140033号的优先权，其全部内容通过引用结合于此。

Claims (20)

1.一种半导体芯片，包括：
基板；
穿过该基板的贯通电极；以及
介电层，形成在该基板和该贯通电极之间，并且具有介电常数减小结构。
2.根据权利要求1所述的半导体芯片，其中具有该介电常数减小结构的该介电层包括空心型介电层，该空心型介电层具有限定在其中心部分中的空气间隙。
3.根据权利要求2所述的半导体芯片，其中该空心型介电层的材料包括选自氧化硅层、氮化硅层、氮氧化硅层、聚酰亚胺、苯并环丁烯和聚对二甲苯中的任何一种。
4.根据权利要求1所述的半导体芯片，其中具有该介电常数减小结构的该介电层包括其中具有多个空气间隙的多孔介电层。
5.根据权利要求4所述的半导体芯片，其中该多孔介电层的材料包括选自氧化硅层、氮化硅层、氮氧化硅层、氢硅倍半氧烷和甲基硅倍半氧烷中的任何一种。
6.根据权利要求1所述的半导体芯片，其中具有该介电常数减小结构的该介电层包括空心型介电层和无空气间隙介电层的双层结构，该空心型介电层具有限定在其中心部分中的空气间隙，该无空气间隙介电层中没有空气间隙。
7.根据权利要求6所述的半导体芯片，其中该空心型介电层和该无空气间隙介电层包括选自氧化硅层、氮化硅层、氮氧化硅层、聚酰亚胺、苯并环丁烯和聚对二甲苯中的任何一种。
8.根据权利要求1所述的半导体芯片，其中具有该介电常数减小结构的该介电层包括多孔介电层和无空气间隙介电层的双层结构，该多孔介电层中具有多个空气间隙，该无空气间隙介电层中没有空气间隙。
9.根据权利要求8所述的半导体芯片，其中该多孔介电层的材料包括选自氧化硅层、氮化硅层、氮氧化硅层、氢硅倍半氧烷和甲基硅倍半氧烷中的任何一种。
10.根据权利要求8所述的半导体芯片，其中该无空气间隙介电层的材料包括选自氧化硅层、氮化硅层、氮氧化硅层、聚酰亚胺、苯并环丁烯和聚对二甲苯中的任何一种。
11.根据权利要求1所述的半导体芯片，其中具有该介电常数减小结构的该介电层包括空心型介电层和多孔介电层的双层结构，该空心型介电层具有限定在其中心部分中的空气间隙，该多孔介电层中具有多个空气间隙。
12.根据权利要求11所述的半导体芯片，其中该空心型介电层的材料包括选自氧化硅层、氮化硅层、氮氧化硅层、聚酰亚胺、苯并环丁烯和聚对二甲苯中的任何一种。
13.根据权利要求11所述的半导体芯片，其中该多孔介电层的材料包括选自氧化硅层、氮化硅层、氮氧化硅层、氢硅倍半氧烷和甲基硅倍半氧烷中的任何一种。
14.一种堆叠半导体封装体，包括：
多个半导体芯片，其每一个都包括基板、穿过该基板的贯通电极以及形成在该基板和该贯通电极之间且具有介电常数减小结构的介电层，并且堆叠为使得该多个半导体芯片的贯通电极彼此连接。
15.根据权利要求14所述的堆叠半导体封装体，还包括：
第一介电层，形成在该多个堆叠的半导体芯片当中的最下面的半导体芯片下方使得该最下面的半导体芯片的该贯通电极被暴露；
重分配线，形成在该第一介电层下访，并且与该最下面的半导体芯片的该暴露的贯通电极电连接；以及
第二介电层，形成在包括该重分配线的该第一介电层下方使得该重分配线的部分被暴露。
16.根据权利要求15所述的堆叠半导体封装体，还包括：
外部连接端子，安装到该重分配线的通过该第二介电层暴露的部分。
17.根据权利要求14所述的堆叠半导体封装体，还包括：
结构体，支撑该半导体芯片并且具有连接电极，该连接电极与该多个堆叠的半导体芯片当中的该最下面的半导体芯片的该贯通电极电连接。
18.根据权利要求17所述的堆叠半导体封装体，其中该结构体包括印刷电路板、***体和半导体封装体中的任何一种。
19.根据权利要求14所述的堆叠半导体封装体，其中，在该半导体芯片当中，该最下面的半导体芯片的具有该介电常数减小结构的介电层具有最高的介电常数，具有该介电常数减小结构的介电层的介电常数朝着最上面的半导体芯片逐渐减小，并且该最上面的半导体芯片的具有该介电常数减小结构的介电层具有最低的介电常数。
20.根据权利要求19所述的堆叠半导体封装体，
其中该半导体芯片包括第一半导体芯片、堆叠在该第一半导体芯片下方的第二半导体芯片以及堆叠在该第二半导体芯片下方的第三半导体芯片，并且
其中该第三半导体芯片的介电层包括多孔介电层和无空气间隙介电层的双层结构，该多孔介电层中具有多个空气间隙，该无空气间隙介电层中没有空气间隙，该第二半导体芯片的介电层包括其中具有多个空气间隙的多孔介电层的单层结构，并且该第一半导体芯片的介电层包括空心型介电层的单层结构，空心型介电层具有限定在其中心部分中的空气间隙。
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US20150091139A1 (en) 2015-04-02
CN103178029B (zh) 2016-12-21
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US20130161826A1 (en) 2013-06-27
US10014278B2 (en) 2018-07-03

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