CN103164565A - Method for automatically forming antenna regular test vectors - Google Patents
Method for automatically forming antenna regular test vectors Download PDFInfo
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- CN103164565A CN103164565A CN2012105124209A CN201210512420A CN103164565A CN 103164565 A CN103164565 A CN 103164565A CN 2012105124209 A CN2012105124209 A CN 2012105124209A CN 201210512420 A CN201210512420 A CN 201210512420A CN 103164565 A CN103164565 A CN 103164565A
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Abstract
The invention provides a method for automatically forming antenna regular test vectors and belongs to the field of process design kit (PDK) verification in integrated circuit auxiliary design software tools. The core idea includes that automatic drawing of the test vectors is achieved through a method that maximum antenna ratios are enabled to be converted to maximum lengths of conduct layers related to an antenna effect. The areas of grids and the widths of the conduct layers are selected through self-adaption, and the lengths of the conduct layers are guaranteed within a reasonable map drawing range. In terms of the antenna effect generated through accumulation of multilayer conduct layers, the antenna effect is quantified to each specific conduct layer through a method for dividing the antenna ratios equally, and then the maximum antenna ratio distributed to each conduct layer is enabled to be converted into the maximum length of each conduct layer to generate the test vectors automatically. According to the method for automatically forming the antenna regular test vectors, just simple process information needs to be provided by users and input, and in allusion to various antenna regulars defined by the users, process connected relation is utilized by tools to generate various test vectors which correspond with the regulars. Therefore, the problems that drawing the map test vectors by hand are low in efficiency, poor in accuracy and not enough in test cases are solved.
Description
Technical field
The present invention is the method for a kind of automatic generation test vector of checking antenna effect design rule.The invention belongs to technological design kit PDK in integrated circuit Autocad instrument (Process Design Kit) checking field.
Background technology
Along with the integrated circuit (IC) design increasingly complex, the top layer wiring metal is more and more, and the size of grid is more and more less, and the possibility that antenna effect occurs becomes increasing.So-called antenna effect refers to that long lead is assembled electric charge too much and discharge breakdown thin gate oxide and cause the phenomenon of circuit malfunction.Eliminating antenna effect is one of problem of important consideration in integrated circuit nanometer technology Design and manufacture.If considering deficiency, antenna effect will directly affect the reliability of integrated circuit (IC) design and the yield rate problem of chip.Usually antenna effect is to check by the antenna rule that Foundry manufacturer provides.These rules are can be connected on grid and not need source electrode or drain electrode to check as the maximum metal area of discharge device whether layout design has effectively evaded antenna effect by regulation, so the correctness of antenna rule file is most important.In order to guarantee the correctness of antenna rule file, traditional way is exactly manual exploitation domain test vector, then verifies by these test vectors whether the design rule that Foundry manufacturer develops is correct.If test result is different with in advance expection, revise the antenna rule file and re-start above-mentioned proof procedure, loop iteration is until the checking of antenna rule file by various test vectors like this.This traditional test vector construction process relates to three difficult points: the one, and the accuracy of test vector structure, one is the completeness of test vector structure, another is the efficiency of test vector structure.In today of nanometer technology fast development, process rule becomes increasingly complex, and the design rule number is more and more, need to more enrich complete test vector set pair design rule and verify.Yet the actual design rule construction cycle is compressed shorter and shorter, and PDK slip-stick artist often attends to one thing and lose sight of another, and can't reach balance on accuracy, completeness and the high efficiency of test vector.Even under many circumstances, at the appointed time interior complete design rule exploitation, the Developmental Engineer checks the correctness of design rule code by the debugging mode of mutual reading code.This method depends on Developmental Engineer's itself experience and ability to a great extent, and very likely ignores the inspection of certain situation.Three large difficult points for traditional test vector structure, the present invention proposes a kind of method of automatic generation antenna regular testing vector, the method only needs the user to provide simple technique information as input, instrument is according to the corresponding test vector of user-defined antenna rule generation, thereby realized the high efficiency that test vector generates, guaranteed simultaneously the rich and accuracy of test vector.
Summary of the invention
The present invention proposes a kind of method of automatic generation antenna regular testing vector.Its basic meaning is: the multiple test vector of verifying this antenna rule according to the antenna rule generation of technique annexation and user's appointment.Its technical method is maximum antenna ratio problem to be converted into the maximum length problem of the conductor layer relevant to the antenna ratio by the method that self-adaptation is chosen polysilicon gate area and conductor layer width, then automatically draws test vector according to conductor size and conductor annexation.Antenna effect is quantized on every layer of concrete conductor by the method for dividing the antenna ratio equally for the cumulative antenna effect that produces of multi-layer conductive, and then the maximum length that the maximum antenna ratio that is assigned to every layer of conductor is converted into every layer of conductor is carried out test vector automatically generate.
The inventive method can generate the test vector of multiple jumper wiring automatically, can automatically generate the test vector that adds back biased diode, and the emitter area size of back biased diode can be controlled.For the test vector of the antenna rule of grid, metal level and hole layer, minute accumulation mode and non-accumulation mode generate automatically.For the conductor surface integration lateral area in the antenna ratio and two kinds of patterns of top surface area, support the mode of top surface area for the hole area in the antenna ratio.All can automatically generate the test vector under multiple voltage environment under multi-layer gate oxygen technique and same technique.The inventive method greatly reduces the time of test vector structure, has guaranteed correctness and the completeness of test vector.Make PDK slip-stick artist's test job concentrate in the checking of antenna rule rather than in the generation of test vector.
Description of drawings
Fig. 1: technique information input schematic diagram
Fig. 2: the schematic diagram of a definition antenna rule
Fig. 3 a: schematic diagram that automatically generates the test vector result
Embodiment:
The probability that antenna effect occurs is weighed by " antenna ratio ".Briefly the antenna ratio generally refers to be connected to metallic conductor area on grid and the ratio of gate oxide area.Usually the antenna ratio is larger with regard to easier generation antenna effect.So the maximum threshold values of antenna rule predetermining antenna ratio, if the antenna ratio surpasses this threshold values shows that there is antenna effect in layout design.In order to verify the correctness of antenna rule, need the situation in the simulation layout design to remove to construct two class testing vector sets.One class is good test vector collection, and namely the antenna ratio surpasses the test case set of the maximum threshold values of antenna rule predetermining; One class is bad test vector collection, i.e. the test case set of antenna ratio in maximum threshold values scope.If the antenna rule does not report an error entirely for good test vector, bad test vector is all reported an error, think that the antenna rule is correct.The main method of eliminating at present antenna effect has jumper wiring and the method that adds back biased diode.
Have difference for the computing formula of whether inserting back biased diode antenna ratio.
● without the antenna ratio computing formula of back biased diode:
EGAR＝EA/Area_gate (1)
Wherein EGAR is the abbreviation of Etch Gate Area Ratio, means the antenna ratio; EA is that metallic conductor area or hole aspect are long-pending, and Area_gate is the gate area of gate oxide.
● add the antenna ratio computing formula of back biased diode:
EGAR＝(EA/Area_gate)-K*AAD-DB (2)
Wherein EGAR is the abbreviation of Etch Gate Area Ratio, means the antenna ratio; EA is that metallic conductor area or hole aspect are long-pending, and Area_gate is the gate area of gate oxide.AAD is the area of back biased diode, and K is amplification coefficient, and DB is a constant Diode_bonus parameter of using when adding back biased diode.
If the inspection layer of antenna rule is metal level, according to above-mentioned formula (1) be connected 2) in EA be the area of inspection layer or connect all effective metal area sums on the grid node, the test vector structure is divided into non-accumulation mode and two kinds of situations of accumulation mode.
1. non-accumulation mode
Non-accumulation mode refers to only consider the antenna effect that the current check layer causes when calculating antenna effect.Namely EA equals the area of inspection layer self in antenna ratio computing formula (1) and (2).According to formula (1), we can derive (2) respectively:
If what A. EA calculated is the lateral area of metallic conductor self:
Metallic conductor length=EGAR*Area_gate/ (2* metallic conductor thickness)-metallic conductor width (3)
* Area_gate/ (2* metallic conductor the thickness)-metallic conductor width (4) of metallic conductor length=(EGAR+K*AAD+DB)
If what B. EA calculated is the top layer area of metallic conductor self:
Metallic conductor length=EGAR*Area_gate/ metallic conductor width (5)
The * Area_gate/ metallic conductor width (6) of metallic conductor length=(EGAR+K*AAD+DB)
In above-mentioned formula (3), antenna ratio, metallic conductor thickness are known constants; In above-mentioned formula (4), antenna ratio, amplification coefficient K, DB and metallic conductor thickness are known constants; In above-mentioned formula (5), the antenna ratio is known constant; Antenna ratio in above-mentioned formula (6), amplification coefficient K, DB are known constants.If the therefore fixing width of gate area and inspection layer conductor, we can instead release the length of inspection layer conductor.Draw the full detail of inspection layer metal when we have just obtained automatic structure test vector like this.Because do not consider the antenna effect of all the other metal levels under non-accumulation mode, therefore it can adopt width and the length identical with the inspection layer conductor to draw.Combined process link information like this, just we can draw under this technique as wire jumper upwards automatically, wire jumper downwards inserts the typical test vector in the various situations such as back biased diode.Because in actual process, the value of antenna ratio is often very large, bad if conductor width and area are selected, tend to cause the metal drawn long and surmount domain full-size scope.During the actual test vector of structure automatically, we adopt the area of the rational grid figure of adaptive process choosing layer and the width of metallic conductor.Under default situations, it is 5um that instrument arranges metal width, and the area of grid gate is 1 square micron, and all metal levels adopt same widths to draw.Before automatically drawing each test vector, instrument can obtain according to the maximum drafting scope that drawn test vector structure and domain allow drawing the maximal value of minimum widith of each metal level of each test vector, if the maximal value of all metal level minimum widiths is less than 5um, all metal levels 5um that Uses Defaults draws, if the maximal value of all metal level minimum widiths is greater than 5um, automatically to adjust the metals plotted width be that the peaked twice of metal level minimum widith is drawn again to instrument.
2. accumulation mode
Accumulation mode refers to consider the antenna effect that multi-layer conductive causes gate oxide when calculating antenna effect.Change for jumper wiring the test vector that the metal line level solves antenna effect, antenna effect may be disconnected at certain layer, therefore the antenna ratio of accumulation mode only considers to cause the effective metal conductor area of antenna effect to the ratio of gate oxide area, and namely the EA in above-mentioned formula (1), (2) is the area sum of effective metal conductor.Suppose to have in the effective metal conductor N section metal to participate in the calculating of antenna ratio (may have same metal layer in N section conductor), we can obtain by the method for dividing the maximum antenna ratio equally the length of every section metallic conductor.Specific formula for calculation is as follows:
If what C. EA calculated is the lateral area of metallic conductor self:
Conductor J length=EGAR*Area_gate/ (2*N* conductor J thickness)-conductor J width, 1＜=J＜=N (7)
* Area_gate/ (2*N* conductor J the thickness)-conductor J width (8) of conductor J length=(EGAR+K*AAD+DB)
If what D. EA calculated is the top layer area of metallic conductor self:
Conductor J length=EGAR*Area_gate/ (N* conductor J width), 1＜=J＜=N (9)
The * Area_gate/ (N* conductor J width) of conductor J length=(EGAR+K*AAD+DB), 1＜=J＜=N (10)
Be similar to non-accumulation mode ground thought, if in above-mentioned (7), (8), (9), (10) the fixing width of gate area and every section conductor, we can instead release the length of every section conductor.Here the width of the area of gate and every section conductor can be got identical value with simplified operation, and all metal width of default setting are 5um, and the area of grid gate is 1 square micron.We just can construct less than the good test vector of maximum antenna ratio and the bad test vector of violation maximum antenna ratio automatically according to the data message of top grid, metal level like this.Same conductor width and area are selected to consider that the conductor length that is calculated by them does not surmount domain full-size scope.We have adopted adaptive algorithm to guarantee that test vector is by rational structure equally.Adopt the test vector that adds back biased diode, the emitter area size of diode can be adjusted, and can draw by the user's request size.
If the inspection layer of antenna rule is the hole layer, disposal route thought and inspection layer are that the processing thought of metal level is similar, and just the hole layer is square, length and width equate, and EA only need consider the top layer area, there is no saying of lateral area, and is that area for connecting hole adds up under accumulation mode.When this test vector structure, we only draw a hole layer in the metal junction, and the porose same size that all adopts.Suppose to have in test vector N hole to participate in the calculating of antenna ratio, under accumulation mode, the size computing formula in hole is:
The length of side=the sqrt in hole (EGAR*Area_gate/N) (11)
The length of side=the sqrt in hole ((EGAR+K*AAD+DB) * Area_gate/N) (12)
Be the hole length of side computing formula under non-accumulation mode when above-mentioned formula (11), (12) middle N=1.
Therefore be the test vector structure of hole layer for inspection layer, we can automatically construct jumper wiring pattern under accumulation mode and non-accumulation mode test vector, add the test vector of antenna device or the test vector of the above two combinations.
A kind of method of automatic generation antenna regular testing vector is supported multi-layer gate oxygen technique in addition.The grid layer that the user uses in the time of can choosing as required concrete structure test vector, instrument is drawn corresponding test vector according to this information.Simultaneously for the situation of same technique multiple voltage, the user equally can the nominative testing vector place voltage environment.Instrument is constructed multiple test vector to satisfy antenna rule checking demand according to the customer requirements Automatic Combined.
To sum up set forth, the below provides the step that a test vector generates:
The first step: input technique information (for example: top conductors link information, conductor thickness information etc.), referring to accompanying drawing 1.
Second step: the antenna rule of inspection layer is wanted in definition, referring to accompanying drawing 2.
The 3rd step: call computer software programs of the present invention, automatically generate antenna regular testing vector, referring to accompanying drawing 3.
The technique information of above-mentioned steps one definition is global information, and the user only need to define once.In step 2, antenna that many of user's definables will check rule, the software program of invocation step three then, the good test vector of corresponding all the antenna rules of disposable generation and bad test vector.
For the antenna effect rule file under a typical Smic40nm technique, the antenna rule always has 21.Classic method manual drawing test vector will be spent 1 month, and above-mentioned automatic generation test vector method only needs less than all domain test vectors that just obtained all antenna rules in 1 minute, only spends less than 10 minutes and write the test vector create-rule.The inventive method has improved the development efficiency of test vector greatly, has reduced human cost, guarantees that design rule verification is fully reliable.
Claims (1)
1. method that automatically generates antenna regular testing vector, its basic meaning is: the multiple test vector of verifying this antenna rule according to the antenna rule generation of technique annexation and user's appointment.Its principal character is: can automatically generate the test vector of multiple jumper wiring, can automatically generate the test vector that adds backward dioded, can support the automatic generation of the test vector of accumulation mode and non-accumulation mode.Can support lateral area and two kinds of patterns of top surface area for the conductor area in the antenna ratio; Support top surface area for the hole area in the antenna ratio.All can realize automatic generation to the antenna regular testing vector under multiple voltage environment under multi-layer gate oxygen technique and same technique.
Concrete steps:
The first step: the user inputs technique information (for example: top conductors link information, conductor thickness information etc.).
Second step: the antenna rule of inspection layer is wanted in user's definition.
The 3rd step: call computer software programs of the present invention, automatically generate antenna regular testing vector.
Wherein the 3rd step realized that the core technology thought of test vector robotization was:
1) test vector for non-accumulation mode lower conductor layer antenna rule generates automatically, the method that instrument is chosen polysilicon gate area and conductor layer width by self-adaptation is converted into maximum antenna ratio problem the maximum length problem of the conductor layer relevant to the antenna ratio, then automatically draws test vector according to conductor size and conductor annexation.
2) test vector for accumulation mode lower conductor layer antenna rule generates automatically, instrument is quantized to antenna effect on every layer of concrete conductor by the method for dividing the antenna ratio equally, and then the maximum length that the maximum antenna ratio that is assigned to every layer of conductor is converted into every layer of conductor is carried out test vector automatically generates.
3) test vector for the conductor layer antenna rule that adds diode generates automatically, and instrument is considered antenna effect factor and maximum antenna ratio that diode causes together by the fixing method of diode area.Test vector for non-accumulation mode generates automatically, and instrument will both act on the automatic drafting that maximum length problem that sum is converted into the conductor layer relevant to antenna effect realizes conductor layer.Test vector for accumulation mode generates automatically, and instrument will both act on sum to be divided equally and be assigned on every layer of concrete conductor, and then the maximum length that the concrete antenna effect value that is assigned to every layer of conductor is converted into every layer of conductor is carried out test vector automatically generates.
4) test vector for hole layer antenna rule under non-accumulation mode generates automatically, instrument is chosen the polysilicon gate area by self-adaptation method is converted into maximum antenna ratio problem the maximal side problem in the hole relevant to the antenna ratio, then automatically draws test vector according to hole dimension and conductor annexation.
5) test vector for hole layer antenna rule under accumulation mode generates automatically, instrument is quantized to antenna effect on every layer of hole by the method for dividing the antenna ratio equally, and then the maximal side that is assigned to maximum antenna ratio on every layer of hole and is converted into every layer of hole layer is carried out test vector automatically generates.
6) test vector for the hole layer antenna rule that adds diode generates automatically, and instrument is considered antenna effect factor and maximum antenna ratio that diode causes together by the fixing method of diode area.Test vector for non-accumulation mode generates automatically, and instrument will both act on the automatic drafting that maximal side problem that sum is converted into the hole layer relevant to antenna effect realizes test vector.Test vector for accumulation mode generates automatically, and instrument will both act on sum to be divided equally and be assigned on every layer of hole, and then the maximal side that is assigned to concrete antenna effect value on every layer of hole and is converted into every layer of hole layer is carried out test vector automatically generates.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108897933A (en) * | 2018-06-15 | 2018-11-27 | 北方电子研究院安徽有限公司 | A kind of method of quick elimination antenna effect |
| CN109298686A (en) * | 2017-07-25 | 2019-02-01 | 通用汽车环球科技运作有限责任公司 | System and method for using business intelligence for rule-based design and manufacture technology |
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| US20010010093A1 (en) * | 2000-01-25 | 2001-07-26 | Nec Corporation | Layout design method |
| CN1848121A (en) * | 2005-04-05 | 2006-10-18 | 台湾积体电路制造股份有限公司 | Antenna ratio deciding method |
| CN101339578A (en) * | 2008-08-14 | 2009-01-07 | 四川登巅微电子有限公司 | Method for creating file containing aerial effect information |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109298686A (en) * | 2017-07-25 | 2019-02-01 | 通用汽车环球科技运作有限责任公司 | System and method for using business intelligence for rule-based design and manufacture technology |
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Application publication date: 20130619 |