CN101339578A - Method for creating file containing aerial effect information - Google Patents
Method for creating file containing aerial effect information Download PDFInfo
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- CN101339578A CN101339578A CNA2008100458090A CN200810045809A CN101339578A CN 101339578 A CN101339578 A CN 101339578A CN A2008100458090 A CNA2008100458090 A CN A2008100458090A CN 200810045809 A CN200810045809 A CN 200810045809A CN 101339578 A CN101339578 A CN 101339578A
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Abstract
The invention discloses a method for generating files containing the antenna effect information, which is characterized in that: at first, a GDSII file is generated from a layout; then the GDSII file is operated by a layout verification tool to generate files containing the information of connecting lines; at last, the information of the connecting lines in the files which contain the information of the connecting lines is written into a CLF file. By using the layout verification tool and script language, the method provided by the invention can directly extract the CLF file with a simple process of realization, thus greatly saving time of editing engineers of integrated circuit layouts and saving cost on the design of the integrated circuit layouts; the method can also generate needed CLF files rapidly with respect to varied locating and wiring tools, thus providing great convenience for entering varied locating and wiring tools needed by the same IP; for integrated circuit layouts of varied projects, an operation file and a script program file complied last time can be adopted, thus reducing time of editing engineers of integrated circuit layouts to the minimal during the process of generation of the CLF files.
Description
Technical field
The present invention relates to the field of integrated circuit back-end design, particularly a kind of generation comprises the method for antenna effect message file.
Background technology
In the IC Chip Production manufacture process, floating empty metal wire or polysilicon conductor can be collected electric charge as antenna in technological process (as plasma etching).Big and when being directly connected to polysilicon gate when metal wire or polysilicon conductor total length, along with the accumulation of the electric charge of its collection, voltage just might puncture thin gate oxide also along with rising, and this phenomenon is called antenna effect.Generally, we weigh the probability that antenna effect can take place a chips with " antenna ratio " (" antenna ratio ").The definition of " antenna ratio " is: the area of the conductor (generally being metal or polysilicon line) of formation so-called " antenna " and the ratio of the gate oxide area that is linked to each other.
Antenna effect is especially obvious in the following technology of 0.18um, can influence the chip yield, causes integrity problem.General circuit layout design process can be considered the influence of antenna effect to chip, especially in chip, use IP kernel (intellectual property core Intellectual Property Core, refer to realize the integrated circuit (IC) design of certain function, it is one section hardware description language program with particular electrical circuit function, this program and integrated circuit technology are irrelevant, can be transplanted to and go the production integrated circuit (IC) chip in the different semiconductor technologies.IP kernel has two kinds, and the VHDL program irrelevant with technology is called soft nuclear; Integrated circuit diagram with particular electrical circuit function is called stone.Stone does not generally allow change, and it is big to utilize stone to carry out the integrated circuit (IC) design difficulty, but easy successful flow.) time, because IP as a black box, do not know the connection situation of the port (input/output port of IP) of IP in IP inside, so when using IP, need a file that comprises all port link informations of IP, such as CLF (Cell library Format, the file of definition submodule information in integrated circuit (IC) design) file, should comprise all metal wires that are connected on the port in this file, information (the metal wire of polysilicon line and diffusion zone, the area of polysilicon line and diffusion zone, the ratio of these line areas and gate oxide area etc.).Instrument for different automatic placement and routings, the form of CLF file is different, such as instrument Astro of automatic placement and routing (automatic placement and routing's instrument of Synopsys company) and Soc Encounter (automatic placement and routing's instrument of Candence company) relatively more commonly used now, the form that different separately CLF files is all arranged, the CLF file between these instruments can not be used mutually.
The method that generates the CLF file at present mainly is the human-edited, promptly each port is gone up the metal wire, polysilicon line and the diffusion zone that connect and manually add in the CLF file of set form, other method is exactly to comprise the method that transforms the CLF file in automatic placement and routing's instrument.
Bigger design such as big Simulation with I P, needs concrete each port of calculating to go up the area of the conductor that connects in the time of the manual CLF of generation file, they are consuming time many and make mistakes easily; There is problem consuming time equally in method for the generation CLF that provides by automatic placement and routing's instrument, because these instruments all can not be directly from layout extraction CLF.
Summary of the invention
The present invention can be by layout verification tool, directly apace from layout extraction CLF file for the method that provides a kind of generation to comprise the antenna effect message file is provided.
Technical scheme of the present invention is as follows:
A kind of generation comprises the method for antenna effect message file, it is characterized in that: at first from domain, generate the GDSII file, then the GDSII file is generated the file that comprises link information by layout verification tool operation, the link information that will comprise at last in the file of link information writes in the CLF file.
Described domain is the graphical representation form of circuit in the integrated circuit (IC) design, is the bridge that connects integrated circuit (IC) design and integrated circuit manufacturing.
(geometry data standard ii) is the Standard File Format of X-Y scheme to described GDSII, the file of GDSII form is the graphic file of integrated circuit diagram, the Standard File Format of X-Y scheme is the file of binary mode, and most of layout verification tool is all supported the file of this form.In layout editing instrument (as Virtuoso, Laker and L-edit etc.),, can directly produce the GDSII file of the integrated circuit diagram that edits by the function that the layout editing instrument carries.
In order from GDSII, to extract the needed file that comprises link information, need utilize layout verification tool such as Calibre, Hercules, Dracula, Diva etc., and the operation of these instruments must have an operating file, and the operating file of each instrument all has fixing separately grammer, this file generally is to write by text edit software, and is to write operating file according to institute's tool using, so that can move selected layout verification tool by this operating file.
Use the operating file operation layout verification tool of above-mentioned layout verification tool then, the result can generate the file that comprises link information.
The information that comprises the metal wire, polysilicon lines and the diffusion zone that are connected to port in the described file that comprises link information; Described link information comprises the area or the girth of metal wire, polysilicon line, diffusion zone, and the ratio of these lines and gate oxide area or girth.
Described link information writes the CLF file by script.The present invention uses and realizes this process based on the script of LINUX/UNIX operating system, and the script of operable LINUX/UNIX operating system has PERL, AWK, TCL, Sed etc.
These scripts are program languages, therefore need write a program file (being generally the file of textual form) based on script, the effect of this file is to operate the file that comprises link information, thereby generate the CLF file, its detailed process is to extract to comprise the link information that comprises in the file of link information, and these link information are write in the CLF file with set form.Because different scripts has different grammers and form, it all is different therefore using different scripts, used program file.
In addition for different automatic placement and routings instrument, the form of the CLF file that it can read in also different (form of the CLF file that can read in such as Astro and Soc Encounter is just different), therefore when using with a kind of script, generate the CLF file that different automatic placement and routings instrument can read in, described program file can be different.
Beneficial effect of the present invention is as follows:
The present invention directly extracts the CLF file by layout verification tool and script from domain GDSII file, and its implementation procedure is simple, can save integrated circuit diagram editor slip-stick artist's time greatly, thereby saves the cost of integrated circuit diagram design; And for different placement-and-routing's instruments, can generate the CLF file that needs fast, very convenient when same IP need call in different placement-and-routings instrument; For the integrated circuit diagram of disparity items, can use the operating file and the shell script file that write for the first time, in the process that generates the CLF file, the time that integrated circuit diagram editor slip-stick artist is spent can reduce to minimum.
Description of drawings
Fig. 1 is a schematic flow sheet of the present invention
Embodiment
Embodiment 1
As shown in Figure 1, a kind of generation comprises the method for antenna effect message file, at first from the domain that edits, generate the GDSII file, then the GDSII file is generated the file that comprises link information by layout verification tool operation, the link information that will comprise at last in the file of link information writes in the CLF file.
Described domain is the graphical representation form of circuit in the integrated circuit (IC) design, is the bridge that connects integrated circuit (IC) design and integrated circuit manufacturing.
The file of described GDSII form is the graphic file of integrated circuit diagram, is the file of binary mode, and most of layout verification tool is all supported the file of this form.In layout editing instrument (as Virtuoso, Laker and L-edit etc.),, can directly produce the GDSII file of the integrated circuit diagram that edits by the function that the layout editing instrument carries.
In order from GDSII, to extract the needed file that comprises link information, need utilize layout verification tool such as Calibre, Hercules, Dracula, Diva etc., and the operation of these instruments must have an operating file, and the operating file of each instrument all has fixing separately grammer, this file generally is to write by text edit software, and is to write operating file according to institute's tool using, so that can move selected layout verification tool by this operating file.
Use the operating file operation layout verification tool of above-mentioned layout verification tool then, the result can generate the file that comprises link information.
The information that comprises the metal wire, polysilicon lines and the diffusion zone that are connected to port in the described file that comprises link information; Described link information comprises the area or the girth of metal wire, polysilicon line, diffusion zone, and the ratio of these lines and gate oxide area or girth.
Described link information writes the CLF file by script.The present invention uses and realizes this process based on the script of LINUX/UNIX operating system, and the script of operable LINUX/UNIX operating system has PERL, AWK, TCL, Sed etc.
These scripts are program languages, therefore need write a program file (being generally the file of textual form) based on script, the effect of this file is to operate the file that comprises link information, thereby generate the CLF file, its detailed process is to extract to comprise the link information that comprises in the file of link information, and these link information are write in the CLF file with set form.Because different scripts has different grammers and form, it all is different therefore using different scripts, used program file.
In addition for different automatic placement and routings instrument, the form of the CLF file that it can read in also different (form of the CLF file that can read in such as Astro and Soc Encounter is just different), therefore when using with a kind of script, generate the CLF file that different automatic placement and routings instrument can read in, described program file can be different.
Embodiment 2
In Laker (the layout editing instrument of Silicon canvas company) layout editing environment, from the domain of having finished, generate the GDSII file.
Write the file that from the GDSII file, extracts metal wire, polysilicon lines and diffusion zone information, use Calibre (layout verification tool of Mentor company) in this example, write the needed operating file of extraction with the grammer of Calibre, move Hercules then and generate the file that comprises metal wire, polysilicon lines and diffusion zone information.
Be to use AWK (a kind of script) under the LINUX system in this example, write the script that generates set form CLF file in the file that can from the 2nd step, obtain, just can obtain needed CLF file behind the Run Script, the CLF file that generates in this example is the CLF file that is used among the Soc Encounter (automatic placement and routing's instrument of Candence company).
Embodiment 3
In Virtuoso (the layout editing instrument of Cadence company) layout editing environment, from the domain of having finished, generate the GDSII file.
Write the file that from the GDSII file, extracts metal wire, polysilicon lines and diffusion zone information, use Hercules (layout verification tool of Synopsys company) in this example, write the needed operating file of extraction with the grammer of Hercules, move Hercules then and generate the file that comprises metal wire, polysilicon lines and diffusion zone information.
Be to use PERL (a kind of script) under the LINUX system in this example, write the script that generates set form CLF file in the file that can from the 2nd step, obtain, just can obtain needed CLF file behind the Run Script, the CLF file that generates in this example is the CLF file that is used among the Astro (automatic placement and routing's instrument of Synopsys company).
Claims (9)
1, a kind of generation comprises the method for antenna effect message file, it is characterized in that: at first from domain, generate the GDSII file, then the GDSII file is generated the file that comprises link information by layout verification tool operation, the link information that will comprise at last in the file of link information writes in the CLF file.
2, described a kind of generation comprises the method for antenna effect message file according to claim 1, it is characterized in that: described domain is the graphical representation form of circuit in the integrated circuit (IC) design, the file of described GDSII form is the graphic file of integrated circuit diagram, is the file of binary mode.
3, described a kind of generation comprises the method for antenna effect message file according to claim 1, it is characterized in that: described layout verification tool is to extract link information and generate the file that comprises link information from the GDSII file by an operating file; Described operating file has fixing grammer, is to write according to the use layout verification tool by text edit software.
4, described a kind of generation comprises the method for antenna effect message file according to claim 3, and it is characterized in that: described layout verification tool moves by operating file, generates the file that comprises link information.
5, comprise the method for antenna effect message file according to claim 1 or 3 described a kind of generations, it is characterized in that: the information that comprises the metal wire, polysilicon lines and the diffusion zone that are connected to port in the described file that comprises link information; Described link information comprises the area or the girth of metal wire, polysilicon line, diffusion zone, and the ratio of line and gate oxide area or girth.
6, described a kind of generation comprises the method for antenna effect message file according to claim 1, and it is characterized in that: described link information writes the CLF file by script.
7, described a kind of generation comprises the method for antenna effect message file according to claim 6, it is characterized in that: described script is a program language, extract link information by writing a program file based on script, and link information write in the CLF file, described program file is a textual form.
8, comprise the method for antenna effect message file according to claim 6 or 7 described a kind of generations, it is characterized in that: described script not simultaneously, program file is also different.
9, comprise the method for antenna effect message file according to claim 6 or 7 described a kind of generations, it is characterized in that: described script is for when a kind of, and automatic placement and routing's instrument as required, program file are also different.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100458090A CN101339578A (en) | 2008-08-14 | 2008-08-14 | Method for creating file containing aerial effect information |
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2008100458090A CN101339578A (en) | 2008-08-14 | 2008-08-14 | Method for creating file containing aerial effect information |
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| CN101339578A true CN101339578A (en) | 2009-01-07 |
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| CNA2008100458090A Pending CN101339578A (en) | 2008-08-14 | 2008-08-14 | Method for creating file containing aerial effect information |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826127A (en) * | 2010-04-07 | 2010-09-08 | 芯硕半导体（中国）有限公司 | Method for converting GDSII file into maskless photoetching machine exposure data |
| CN102955123A (en) * | 2011-08-19 | 2013-03-06 | 上海华虹Nec电子有限公司 | Examination method for different-party IP (internet protocol) containing client party chip antenna effect |
| CN103164565A (en) * | 2012-12-04 | 2013-06-19 | 天津蓝海微科技有限公司 | Method for automatically forming antenna regular test vectors |
| CN112329364A (en) * | 2020-11-06 | 2021-02-05 | 海光信息技术股份有限公司 | Information extraction method medium, information extraction device, circuit verification method medium, and circuit verification device |
| CN112329379A (en) * | 2019-07-31 | 2021-02-05 | 天津大学 | Integrated circuit reliability evaluation method aiming at antenna effect |
| CN113792517A (en) * | 2021-09-09 | 2021-12-14 | 广芯微电子（广州）股份有限公司 | Digital layout design method and device |
-
2008
- 2008-08-14 CN CNA2008100458090A patent/CN101339578A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826127A (en) * | 2010-04-07 | 2010-09-08 | 芯硕半导体（中国）有限公司 | Method for converting GDSII file into maskless photoetching machine exposure data |
| CN102955123A (en) * | 2011-08-19 | 2013-03-06 | 上海华虹Nec电子有限公司 | Examination method for different-party IP (internet protocol) containing client party chip antenna effect |
| CN102955123B (en) * | 2011-08-19 | 2014-10-08 | 上海华虹宏力半导体制造有限公司 | Examination method for different-party IP (internet protocol) containing client party chip antenna effect |
| CN103164565A (en) * | 2012-12-04 | 2013-06-19 | 天津蓝海微科技有限公司 | Method for automatically forming antenna regular test vectors |
| CN112329379A (en) * | 2019-07-31 | 2021-02-05 | 天津大学 | Integrated circuit reliability evaluation method aiming at antenna effect |
| CN112329364A (en) * | 2020-11-06 | 2021-02-05 | 海光信息技术股份有限公司 | Information extraction method medium, information extraction device, circuit verification method medium, and circuit verification device |
| CN113792517A (en) * | 2021-09-09 | 2021-12-14 | 广芯微电子（广州）股份有限公司 | Digital layout design method and device |
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Application publication date: 20090107 |