CN104242943A - Six-bit asynchronous successive approximation analog-digital converter based on resistor type digital-analog converter - Google Patents
Six-bit asynchronous successive approximation analog-digital converter based on resistor type digital-analog converter Download PDFInfo
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Abstract
The invention discloses a six-bit asynchronous successive approximation analog-digital converter based on a resistor type digital-analog converter. The six-bit asynchronous successive approximation analog-digital converter comprises a sampling and holding circuit, an analog-digital converter body, a switch selecting network, a comparator module, an output data coding module and an asynchronous digital control logic circuit, wherein the sampling and holding circuit is used for sampling signals inputted from the outside and outputting a sampling value of the signals inputted from the outside; the digital-analog converter body is used for generating reference voltage; the comparator module comprises a first-stage comparator sub-module and a second-stage comparator sub-module; the first-stage comparator sub-module is used for generating first-stage comparator outputting data according to the sampling value and corresponding reference voltage; the second-stage comparator sub-module is used for generating second-stage comparator outputting data according to control signals, the corresponding reference voltage and the sampling value; the outputting data coding module is used for coding the first-stage comparator outputting data and the second-stage comparator outputting data so as to obtain first-stage outputting data and second-stage outputting data; and the asynchronous digital control logic circuit is used for generating the control signals according to the first-stage comparator outputting data. By the analog-digital converter in an embodiment of the invention, bits of outputting data of every stage are increased, so that conversion time is shortened, and conversion speed is increased.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of six asynchronous gradually-appoximant analog-digital converters based on resistor-type digital to analog converter.
Background technology
The analog to digital converter of high-speed low-power-consumption is widely used in the field such as radio front end receiver of radio sensing network, and considers the required precision of this field to analog to digital converter, and six analog to digital converters can meet performance requirement.Therefore and be unfavorable for low power dissipation design in the analog to digital converter of different structure, full parellel structural module transducer is realizing that high speed design has advantage, but its area and power consumption exponentially increase with precision.And the analog to digital converter that gradually-appoximant analog-digital converter in contrast to other structures has the advantage of low-power consumption, and it forms primarily of digital module, be applicable to technogenic migration, so along with the proposition of entering technique progress in several years and asynchronous gradually-appoximant analog-digital converter design philosophy, making gradually-appoximant analog-digital converter while reaching low-power consumption, realize design at a high speed becomes possibility.
In the related, with reference to shown in Fig. 1, gradually-appoximant analog-digital converter mainly comprises: sampling hold circuit 10, capacitor type digital to analog converter 20, comparator 30 and digital control logic 40.Wherein, sampling hold circuit 10 can select different structure according to precision and rate request; Capacitor type digital to analog converter 20 is often divided into capacitor type and resistor-type two kinds; Comparator 30 is often divided into static comparison device and dynamic comparer two kinds; Digital control logic 40 is often divided into synchronous and asynchronous two kinds.In order to realize the design of high-speed AD converter, comparator 30 more options dynamic comparer, digital control logic 40 more options asynchronous digital control logic.But, because capacitor type digital to analog converter needs the process of charge redistribution, consume change-over time, reduce conversion speed, and gradually-appoximant analog-digital converter change-over time in correlation technique and conversion efficiency can not meet the demand of user well, have much room for improvement.
Summary of the invention
The present invention is intended to solve one of technical problem in above-mentioned correlation technique at least to a certain extent.
For this reason, the object of the invention is to propose one can reduce change-over time, improves six asynchronous gradually-appoximant analog-digital converters based on resistor-type digital to analog converter of conversion speed.
For achieving the above object, the embodiment of the present invention proposes a kind of six asynchronous gradually-appoximant analog-digital converters based on resistor-type digital to analog converter, comprise: sampling hold circuit, described sampling hold circuit is used for sampling to external input signal, and exports the sampled value of described external input signal; Digital to analog converter, described resistor-type digital to analog converter is for generation of reference voltage; Network selected by switch; Comparator module, described comparator module comprises first order comparator submodule and second level comparator submodule, described first order comparator submodule is used for generating first order comparator according to described sampled value and corresponding reference voltage and exports data, and described second level comparator submodule is used for generating second level comparator according to control signal, corresponding reference voltage and described sampled value and exports data; Export data decoding module, described output data decoding module is connected with described comparator module, carries out decoding for exporting data to described first order comparator output data and second level comparator, exports data and second level output data to obtain the first order; And asynchronous digital control logic circuit, described asynchronous digital control logic circuit is used for exporting control signal described in data genaration according to described first order comparator.
According to six asynchronous gradually-appoximant analog-digital converters based on resistor-type digital to analog converter that the embodiment of the present invention proposes, by sampling to external input signal, and export the sampled value of external input signal, thus generate first order output data according to sampled value and corresponding reference voltage, and export the control signal of data genaration, corresponding reference voltage and sampled value according to first order comparator and generate second level output data, by increasing every grade of outputs data bits number, thus reduce change-over time, improve conversion speed.
In addition, six asynchronous gradually-appoximant analog-digital converters based on resistor-type digital to analog converter according to the above embodiment of the present invention can also have following additional technical characteristic:
Further, in one embodiment of the invention, described output data decoding module comprises the first output module and the second output module, described first output module is arranged between the output of described asynchronous digital control logic circuit and described first order comparator submodule, and described second output module is connected with the output of described second level comparator submodule.
Further, in one embodiment of the invention, described first order comparator submodule and second level comparator submodule all can comprise 7 comparators.
Further, in one embodiment of the invention, described comparator can be four end dynamic comparers.
Further, in one embodiment of the invention, described digital to analog converter can be resistor-type digital to analog converter.
Further, in one embodiment of the invention, described first order comparator submodule is triggered by first order clock signal, and described second level comparator submodule is triggered by second level clock signal.
Further, in one embodiment of the invention, described first order clock signal has precedence over described second level clock signal.
The aspect that the present invention adds and advantage will part provide in the following description, and part will become obvious from the following description, or be recognized by practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or additional aspect of the present invention and advantage will become obvious and easy understand from accompanying drawing below combining to the description of embodiment, wherein:
Fig. 1 is the structural representation of gradually-appoximant analog-digital converter in correlation technique;
Fig. 2 is according to an embodiment of the invention based on the structural representation of six asynchronous gradually-appoximant analog-digital converters of resistor-type digital to analog converter;
Fig. 3 is the principle schematic of four end dynamic comparers according to an embodiment of the invention; And
Fig. 4 contrasts schematic diagram based on the sequential relationship of six asynchronous gradually-appoximant analog-digital converters of resistor-type digital to analog converter and the gradually-appoximant analog-digital converter of other structures according to an embodiment of the invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Be exemplary below by the embodiment be described with reference to the drawings, be intended to for explaining the present invention, and can not limitation of the present invention be interpreted as.
In addition, term " first ", " second " only for describing object, and can not be interpreted as instruction or hint relative importance or imply the quantity indicating indicated technical characteristic.Thus, be limited with " first ", the feature of " second " can express or impliedly comprise one or more these features.In describing the invention, the implication of " multiple " is two or more, unless otherwise expressly limited specifically.
In the present invention, unless otherwise clearly defined and limited, the term such as term " installation ", " being connected ", " connection ", " fixing " should be interpreted broadly, and such as, can be fixedly connected with, also can be removably connect, or connect integratedly; Can be mechanical connection, also can be electrical connection; Can be directly be connected, also indirectly can be connected by intermediary, can be the connection of two element internals.For the ordinary skill in the art, above-mentioned term concrete meaning in the present invention can be understood as the case may be.
In the present invention, unless otherwise clearly defined and limited, fisrt feature second feature it " on " or D score can comprise the first and second features and directly contact, also can comprise the first and second features and not be directly contact but by the other characterisation contact between them.And, fisrt feature second feature " on ", " top " and " above " comprise fisrt feature directly over second feature and oblique upper, or only represent that fisrt feature level height is higher than second feature.Fisrt feature second feature " under ", " below " and " below " comprise fisrt feature directly over second feature and oblique upper, or only represent that fisrt feature level height is less than second feature.
Below before describing six the asynchronous gradually-appoximant analog-digital converters based on resistor-type digital to analog converter proposed according to inventive embodiments, the gradually-appoximant analog-digital converter technology in once correlation technique is simply described first.
In the related, with reference to shown in Fig. 1, conventional successive is approached analog to digital converter and is mainly comprised: sampling hold circuit 10, capacitor type digital to analog converter 20, comparator 30 and digital control logic 40.Specific works process is as follows: sampling hold circuit 10 pairs of input signals are sampled, capacitor type digital to analog converter 20 produces reference voltage by charge redistribution, comparator 30 pairs of sampled result and charge redistribution result compare, comparative result feeds back to digital control logic circuit 40, and carry out the circulation of next bit, binary search algorithm is followed, the output data that final generation is all in whole transfer process.For sampling hold circuit 10 and capacitor type digital to analog converter 20, different circuit structures can be selected according to the precision of gradually-appoximant analog-digital converter and rate request.Static comparison device and dynamic comparer are mainly divided into for comparator 30, wherein static comparison device passes through preamplifier, pass to rear class after being amplified by input signal to compare, not only precision is high but also lack of proper care little, but shortcoming is the use due to preamplifier, power consumption is comparatively large, and speed is slower.And dynamic comparer mainly realizes the rapid judgement of voltage by positive feed-back latch, in circuit, there is no static path, so there is no quiescent dissipation, be conducive to the Design and implementation of high speed, low-power consumption.For synchronous digital control logic 40, the change-over time of each is equal, and demand fulfillment comparator compares time the slowest situation, causes the waste and the redundancy that there is change-over time.
It can thus be appreciated that the gradually-appoximant analog-digital converter in correlation technique can't meet the instructions for use of user well on change-over time and conversion speed, haves much room for improvement.
The present invention just based on the problems referred to above, and proposes a kind of six asynchronous gradually-appoximant analog-digital converters based on resistor-type digital to analog converter.
Six the asynchronous gradually-appoximant analog-digital converters based on resistor-type digital to analog converter proposed according to the embodiment of the present invention are described with reference to the accompanying drawings.With reference to shown in Fig. 2, this analog to digital converter comprises: sampling hold circuit 100, digital to analog converter 200, switch are selected network 300, comparator module 400, asynchronous digital control logic circuit 500 and exported data decoding module 600.
Wherein, sampling hold circuit 100 for sampling to external input signal, and exports the sampled value of external input signal.Digital to analog converter 200 is for generation of reference voltage.Comparator module 400 comprises first order comparator submodule 401 and second level comparator submodule 402, first order comparator submodule 401 exports data for generating first order comparator according to sampled value and corresponding reference voltage, and second level comparator submodule 402 exports data for generating second level comparator according to control signal, corresponding reference voltage and sampled value.Asynchronous digital control logic circuit 500 is for exporting data genaration control signal according to first order comparator.Output data decoding module 600 is connected with comparator module 400, exports data decoding module 600 and carries out decoding for exporting data to first order comparator output data and second level comparator, exports data and second level output data to obtain the first order.The analog to digital converter of the embodiment of the present invention by increasing every grade of data bits exported, thus improves conversion speed.
Further, in one embodiment of the invention, with reference to shown in Fig. 2, first order comparator submodule 401 is triggered by first order clock signal, and second level comparator submodule 402 is triggered by second level clock signal.Wherein, in one embodiment of the invention, first order clock signal has precedence over second level clock signal.
Further, in one embodiment of the invention, with reference to shown in Fig. 2, export data decoding module 600 and comprise the first output module 601 and the second output module 602.Particularly, first output module 601 is arranged between the output of asynchronous digital control logic circuit 500 and first order comparator submodule 401, second output module 602 is connected with the output of second level comparator submodule 402, and the first output module 601 of output module 600 and the second output module 602 are respectively used to export the first order and export data and second level output data.
Wherein, in one embodiment of the invention, with reference to shown in Fig. 2, first order comparator submodule 401 and second level comparator submodule 402 all can comprise 7 comparators.It should be noted that, the comparator number that the embodiment of the present invention proposes is not limited thereto the situation of numerical value, and the concrete number of comparator can adjust according to practical situations.
Preferably, in one embodiment of the invention, comparator can be four end dynamic comparers.Wherein, in an embodiment of the present invention, the embodiment of the present invention exports the use of three bit data and four end dynamic comparers by every grade, realizes the design of high speed, low-power consumption.
Preferably, in one embodiment of the invention, digital to analog converter 200 can be resistor-type digital to analog converter.In an embodiment of the present invention, the embodiment of the present invention, by using resistor-type digital to analog converter, saves the time of capacitor type digital to analog converter charge redistribution, and then reduces overall change-over time, improves conversion speed.
Particularly, in one embodiment of the invention, with reference to shown in Fig. 2, the analog to digital converter of the embodiment of the present invention is realized by two-stage, and one-level comprises seven comparators, and output data such as the first order producing three exports data and second level output data.Wherein, V
sigexternal input signal, V
iNthe sampled value of input signal, V
cMit is the common mode electrical level receiving sampling capacitance.V
rEFPand V
rEFNthe reference voltage at resistor-type digital to analog converter two ends, V
rEFiit is the reference voltage of the supply comparator that resistor-type digital to analog converter produces.O
1iand O
2ithe output signal of comparator, CLK1
stand CLK2
ndit is the clock signal of two-stage.First, sampling hold circuit 100 couples of external input signal V
sigsample, obtain sampled value V
iN, V
iNbe connected to the input of the two-stage of six asynchronous gradually-appoximant analog-digital converters based on resistor-type digital to analog converter, totally ten four comparators.After sampling terminates, the clock signal clk 1 of first order comparator submodule 401
steffectively, the first order seven comparators start to compare; According to binary search algorithm, seven reference voltages produced by resistor-type digital to analog converter of the first order are respectively (VREFP-VREFN) of-3/4 ,-1/2 ,-1/4,0,1/4,1/2,3/4 times.Secondly, after the first order compares end, can by exporting the output signal O of data decoding module 600 pairs of first order seven comparators
1inamely first order comparator output data carry out decoding, obtain exporting D5, D4, D3 and first order output data based on three bit data of six asynchronous gradually-appoximant analog-digital converter first order of resistor-type digital to analog converter.Meanwhile, according to the comparator output signal O of the first order
1ithe control signal Ai of the second level and the clock signal clk 2 of the second level can be obtained
nd, control signal Ai determines the reference voltage of next stage seven comparator input terminals.Select network 300 by switch, determine seven comparator input terminals reference voltage which resistor-type digital to analog converter produces being connected to the second level.After end is compared in the second level, can by exporting the output signal O of seven comparators in the data decoding module 600 pairs of second level
2inamely second level comparator output data carry out decoding, obtain exporting D2, D1, D0 and second level output data based on three bit data of six asynchronous gradually-appoximant analog-digital converter second level of resistor-type digital to analog converter.In order to ensure second level clock signal clk 2 in design
ndtime effective, the reference voltage of the second level selects network 300 to set up completely by switch, clock signal clk 2
ndand certain time delay to be kept between control signal Ai.
Further, in one embodiment of the invention, with reference to shown in Fig. 3, Fig. 3 is the principle schematic of four end dynamic electric voltage comparators according to an embodiment of the invention, and CLK is clock signal,
be comparator input signal, OUTP and OUTN is comparator output signal.In embodiment in the present invention, comparator is unique analog module and main power consumption source.Four end dynamic electric voltage comparators shown in Fig. 4 containing preamplifier, do not have static path, only consume dynamic power consumption, be conducive to the realization of low power dissipation design.When CLK is low level, transistor M7, M8, M9, M10 conducting, nodes X P and XN is high level, transistor M11 and M12 conducting, and it is low level that comparator exports OUTP and OUTN, and comparator is in reset mode, and the spurious charge in circuit is unloaded puts.When CLK is high level, transistor M1, M2 conducting, comparator input terminal
voltage swing determine nodes X P and XN unload electric discharge lotus speed, the crystal M11/M12 unloading the fireballing node of discharge stream corresponding first ends, and the comparator output signal OUTP/OUTN of its correspondence first becomes high level.And nodes X P unloads the speed of discharge stream by comparator input terminal voltage
with
sum determines, nodes X N unloads the speed of discharge stream by comparator input terminal voltage
with
sum determines, as described in following formula (1).
V
OUT～V
XP-V
XN＝(V
IN1+V
REF2)-(V
IN2+V
REF1)＝(V
IN1-V
IN2)-(V
REF1-V
REF2) (1)
Described in formula (1), the difference (V of what four end dynamic electric voltage comparators in Fig. 3 finally compared is two input sample signals
iN1-V
iN2) and the difference (V of two reference voltages
rEF1-V
rEF2), then realize the design of Differential input circuit, be conducive to eliminating even-order harmonic.Due to adopt in the embodiment of the present invention based in the asynchronous gradually-appoximant analog-digital converter of resistor-type digital to analog converter, digital to analog converter no longer adopts capacitive structure, also the process of charge redistribution is just no longer included, so adopt four end comparators in design, refer to document [Ying-Zu Lin, S.-J.Chang, Y.-T.Liu, et.al. " An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count. " IEEE Tran.Circuits Syst.I, 57 (2010) 1829.].
Further, with reference to shown in Fig. 4, Fig. 4 be the embodiment of the present invention based on six asynchronous gradually-appoximant analog-digital converters of resistor-type digital to analog converter and the sequential relationship comparison diagram of other structure gradually-appoximant analog-digital converters.In low speed gradually-appoximant analog-digital converter in the related, digital control logic circuit 500 often adopts the synchronous digital control logic in Fig. 4 (a), the change-over time of its each bit is equal, once complete conversion needs (N+1) individual clock cycle, and N is the precision of gradually-appoximant analog-digital converter herein.Such as, the synchronous gradually-appoximant analog-digital converter of six 500MHz sample rates, needs the external timing signal of 3.5GHz, and the clock signal producing this speed not only difficulty is large, and power consumption is also very large.In addition, for synchronous digital control logic, the change-over time of each is equal, and the situation that the demand fulfillment comparator decision time is the slowest, thus there is waste and the redundancy of change-over time.Therefore, synchronous gradually-appoximant analog-digital converter is not also suitable for the design of high speed circuit, and formula (2) describes the relation of change-over time in this structure.
T
TOTAL＝T
S/H+T
DAC+N·T
COMP+T
LOGIC (2)
In formula (2), N is the precision of analog to digital converter, T
tOTALonce the time of complete conversion, T
s/Hthe time that sampling keeps, T
dACthe time of capacitor type digital to analog converter charge redistribution, T
cOMPthe comparison time of comparator, T
lOGICit is the time of digital control logic.
Fig. 4 (b) is typically based on the asynchronous gradually-appoximant analog-digital converter sequential chart of capacitor type digital to analog converter, under asynchronous digital control logic, each is triggered by the comparative result of upper, no longer as ensureing in synchronous digital control logic that the change-over time of each is equal, eliminate the waste of change-over time, the comparison time of N times of comparator in formula (2) is converted to the middle highest significant position (MSB) of formula (3) to least significant bit (LSB) sum.
Fig. 4 (c) is six asynchronous gradually-appoximant analog-digital converter sequential charts based on resistor-type digital to analog converter of the employing of the embodiment of the present invention, by adopting resistor-type digital to analog converter, eliminate the time of capacitor type digital to analog converter charge redistribution, and for six precision analog to digital converters, under this structure, circuit is divided into two-stage, level one data exports three, and the overall transformation time is as described in formula (4).
T
TOTAL＝T
S/H+T
COMP，ST1+T
COMP，ST2+T
LOGIC (4)
In formula (4), T
cOMP, ST1be first order change-over time, approximate T in Fig. 4 (b)
cOMP, MSB-2time, because gradually-appoximant analog-digital converter follows binary search algorithm, according to binary search algorithm, the input voltage sampled value of comparator input terminal and reference voltage more and more close, and the comparison time of comparator is inversely proportional to input voltage difference, so input terminal voltage difference is less, the comparison time of comparator is longer.(see document [Sun Tong. the research & design [master thesis] of low-power consumption gradually-appoximant analog-digital converter. Beijing: Tsing-Hua University, 2007.]).So in an embodiment of the present invention, the first three bits position MSB that the first order exports, in MSB-1, MSB-2, to compare the time the longest for MSB-2, and then T
cOMP, ST1approximate this comparison time T
cOMP, MSB-2.In like manner, for T change-over time of the second level in the embodiment of the present invention
cOMP, ST2, approximate T in Fig. 4 (b)
cOMP, LSBtime.Can be found out by above-mentioned contrast, the once complete conversion of six gradually-appoximant analog-digital converters of the embodiment of the present invention only needs two-stage, and the conversion speed of circuit is improved.
Six asynchronous gradually-appoximant analog-digital converters based on resistor-type digital to analog converter of the embodiment of the present invention, for the design of six precision, every grade exports data three, and be divided into two-stage, the conversion efficiency of circuit is greatly optimized.It should be noted that, embodiments of the invention are by based on based on six asynchronous gradually-appoximant analog-digital converters of resistor-type digital to analog converter, the superiority of analysis and designation structure, but those skilled in the art should be understood that, the embodiment of the present invention is not limited to six design accuracies, for the analog to digital converter of different accuracy, according to precision reasonable distribution every grade of outputs data bits number, the optimum of speed and performance can be realized.
According to six asynchronous gradually-appoximant analog-digital converters based on resistor-type digital to analog converter that the embodiment of the present invention proposes, by sampling to external input signal, and export the sampled value of external input signal, thus generate first order output data according to sampled value and corresponding reference voltage, and according to being exported the control signal of data genaration by first order comparator, corresponding reference voltage and sampled value generate the second level and export data, by increasing every grade of outputs data bits number, thus reduce change-over time, improve conversion speed, and use resistor-type digital to analog converter, save the time of capacitor type digital to analog converter charge redistribution, and then further reduce overall change-over time, improve conversion speed.In addition, the embodiment of the present invention exports the use of three bit data and four end dynamic comparers by every grade, achieves the design of high speed, low-power consumption, meets the requirement of user better.
Should be appreciated that each several part of the present invention can realize with hardware, software, firmware or their combination.In the above-described embodiment, multiple step or method can with to store in memory and the software performed by suitable instruction execution system or firmware realize.Such as, if realized with hardware, the same in another embodiment, can realize by any one in following technology well known in the art or their combination: the discrete logic with the logic gates for realizing logic function to data-signal, there is the application-specific integrated circuit (ASIC) of suitable combinational logic gate circuit, programmable gate array (PGA), field programmable gate array (FPGA) etc.
Those skilled in the art are appreciated that realizing all or part of step that above-described embodiment method carries is that the hardware that can carry out instruction relevant by program completes, described program can be stored in a kind of computer-readable recording medium, this program perform time, step comprising embodiment of the method one or a combination set of.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing module, also can be that the independent physics of unit exists, also can be integrated in a module by two or more unit.Above-mentioned integrated module both can adopt the form of hardware to realize, and the form of software function module also can be adopted to realize.If described integrated module using the form of software function module realize and as independently production marketing or use time, also can be stored in a computer read/write memory medium.
The above-mentioned storage medium mentioned can be read-only memory, disk or CD etc.
In the description of this specification, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present invention or example.In this manual, identical embodiment or example are not necessarily referred to the schematic representation of above-mentioned term.And the specific features of description, structure, material or feature can combine in an appropriate manner in any one or more embodiment or example.
Although illustrate and describe embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, those of ordinary skill in the art can change above-described embodiment within the scope of the invention when not departing from principle of the present invention and aim, revising, replacing and modification.
Claims (7)
1., based on six asynchronous gradually-appoximant analog-digital converters of resistor-type digital to analog converter, it is characterized in that, comprising:
Sampling hold circuit, described sampling hold circuit is used for sampling to external input signal, and exports the sampled value of described external input signal;
Digital to analog converter, described digital to analog converter is for generation of reference voltage;
Network selected by switch;
Comparator module, described comparator module comprises first order comparator submodule and second level comparator submodule, described first order comparator submodule is used for generating first order comparator according to described sampled value and corresponding reference voltage and exports data, and described second level comparator submodule is used for generating second level comparator according to control signal, corresponding reference voltage and described sampled value and exports data;
Export data decoding module, described output data decoding module is connected with described comparator module, carries out decoding for exporting data to described first order comparator output data and second level comparator, exports data and second level output data to obtain the first order; And
Asynchronous digital control logic circuit, described asynchronous digital control logic circuit is used for exporting control signal described in data genaration according to described first order comparator.
2. six asynchronous gradually-appoximant analog-digital converters based on resistor-type digital to analog converter according to claim 1, it is characterized in that, described output data decoding module comprises the first output module and the second output module, described first output module is arranged between the output of described asynchronous digital control logic circuit and described first order comparator submodule, and described second output module is connected with the output of described second level comparator submodule.
3. six asynchronous gradually-appoximant analog-digital converters based on resistor-type digital to analog converter according to claim 1, is characterized in that, described first order comparator submodule and second level comparator submodule include 7 comparators.
4. six asynchronous gradually-appoximant analog-digital converters based on resistor-type digital to analog converter according to claim 3, is characterized in that, described comparator is four end dynamic comparers.
5. six asynchronous gradually-appoximant analog-digital converters based on resistor-type digital to analog converter according to claim 1, it is characterized in that, described digital to analog converter is resistor-type digital to analog converter.
6. six asynchronous gradually-appoximant analog-digital converters based on resistor-type digital to analog converter according to claim 1, it is characterized in that, described first order comparator submodule is triggered by first order clock signal, and described second level comparator submodule is triggered by second level clock signal.
7. six asynchronous gradually-appoximant analog-digital converters based on resistor-type digital to analog converter according to claim 6, it is characterized in that, described first order clock signal has precedence over described second level clock signal.
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| CN116192145A (en) * | 2022-12-13 | 2023-05-30 | 辰芯半导体（深圳）有限公司 | Double-limit ADC capable of continuously detecting and power management chip |
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| CN109391269A (en) * | 2017-08-14 | 2019-02-26 | 联发科技股份有限公司 | Successive approximation register type analog-digital converter and its control method |
| CN109391269B (en) * | 2017-08-14 | 2023-02-28 | 联发科技股份有限公司 | Successive approximation register type analog-digital converter and control method thereof |
| CN116192145A (en) * | 2022-12-13 | 2023-05-30 | 辰芯半导体（深圳）有限公司 | Double-limit ADC capable of continuously detecting and power management chip |
| CN116192145B (en) * | 2022-12-13 | 2024-05-28 | 辰芯半导体（深圳）有限公司 | Double-limit ADC capable of continuously detecting and power management chip |
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