CN103123916A - 半导体器件、电子器件以及半导体器件制造方法 - Google Patents

半导体器件、电子器件以及半导体器件制造方法 Download PDF

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CN103123916A
CN103123916A CN2012103761414A CN201210376141A CN103123916A CN 103123916 A CN103123916 A CN 103123916A CN 2012103761414 A CN2012103761414 A CN 2012103761414A CN 201210376141 A CN201210376141 A CN 201210376141A CN 103123916 A CN103123916 A CN 103123916A
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weld pad
zone line
solder projection
semiconductor device
forms
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CN103123916B (zh
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清水浩三
作山诚树
赤松俊也
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Fujitsu Ltd
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Fujitsu Ltd
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Abstract

本发明涉及半导体器件、电子器件以及半导体器件制造方法。所述半导体器件包括：连接构件，该连接构件包括形成在连接构件的主表面上的第一焊垫；半导体芯片，该半导体芯片包括其上形成第二焊垫的电路形成表面，该芯片安装在连接构件上使得电路形成表面面向主表面；以及钎料凸块，该钎料凸块连接第一焊垫和第二焊垫并且由包含Bi和Sn的金属制成，其中该块包括形成为靠近第二焊垫的第一界面层、形成为靠近第一焊垫的第二界面层、形成为靠近界面层中的任一个的第一中间区域，以及形成为靠近界面层中的另一个并且形成为靠近第一中间区域的第二中间区域；在第一中间区域中，Bi浓度高于Sn浓度；而在第二中间区域中，Sn浓度高于Bi浓度。

Description

半导体器件、电子器件以及半导体器件制造方法
技术领域
本文中讨论的实施方案涉及半导体器件、电子器件以及用于制造该半导体器件的方法。
背景技术
随着半导体元件的集成密度的增加和电子部件的封装密度的增加，半导体元件和使用该半导体元件的电子器件的输入/输出端子的数量逐渐增加。例如，在将被倒装安装的半导体元件中，减小了连接端子之间的间距而且也减小了连接端子的面积。
为了实现高速操作，严峻的需求强加于高速操作被期望的当前半导体元件上。例如，在当前高速半导体元件例如大规模集成电路(LSI)中，使用所谓的低K材料例如多孔硅作为层间绝缘膜以减小布线图案之间的寄生电容。然而，低K材料的问题在于：材料通常具有对应于低介电常数的低密度，因此材料在机械上易损坏并且由于接合期间的热变形而易于受损。例如，多孔硅具有4GPa至8GPa的弹性模数，并且其机械强度低于传统层间绝缘材料例如氧化硅膜的机械强度。
在这种情况下，当通过半导体芯片的倒装安装来制造半导体器件时，通过在低温下接合连接端子来期望包含低K材料的高速半导体元件减小衬底在接合期间的热变形。然而，用于接合连接端子的通用无引线钎料在217℃或更高的温度下用于接合，而其不适于在这样的低温下接合。在这种情况下，在包含低K材料的高速半导体元件的安装过程中，使用具有139℃的熔点的共晶Sn(锡)-Bi(铋)钎料或为了改善机械特性如延展性将少量元素如Ag、Cu和Sb添加到Sn-Bi的钎料作为能够在多数情况下减小热应力的钎料材料。
如上所述，共晶Sn-Bi钎料具有139℃的熔点，并且可以在比例如为传统无引线钎料的Sn-Ag-Cu钎料(熔点为217℃)低约80℃的温度下被安装。
然而，在实际的电子器件中存在如下的需求：为了确保电子器件的可靠性，使电子器件在考虑实际环境的约150℃的环境温度下经历温度循环测试或高温暴露测试。然而，在执行这种测试时，测试的环境温度(150℃)超过Sn-Bi钎料的熔点(139℃)，这可以引起接合部分等再熔化的问题。
在具有其中层叠大量电路板和半导体芯片的构造的半导体器件或电子器件中，可能出现如下的问题：在半导体器件或电子器件中，之前通过回流钎料凸块而被接合的部分在将在以后执行的钎料凸块回流过程中熔化。
上述相关技术的例子在Kenichi YASAKA，Yasuhisa OHTAKE等人的“Microstructural Changes in Micro-joins between Sn-58Bi Solders andCopper by Electro-migration”，ICEP 2010 Proceedings FA2-1，第475-478页和OHTAKE等人的“Electro-migration in Microjoints between Sn-BiSolders and Cu”，16th Symposium on Microjoining and AssemblyTechnology in Electronics，2月2-3日，2010，Yokohama，第157-160页中公开。
发明内容
因此，本实施方案的一个方面的目的是提供具有比通过回流刚形成的钎料凸块的熔化温度更高的熔化温度的钎料凸块。
根据实施方案的一个方面，半导体器件包括：第一连接构件，该第一连接构件包括形成在该第一连接构件的第一主表面上的第一连接焊垫；第一/快速半导体芯片(第一半导体芯片或快速半导体芯片)，该第一/快速半导体芯片包括其上形成半导体集成电路的电路形成表面以及形成在该电路形成表面上的第二连接焊垫，该第一/快速半导体芯片以电路形成表面面向第一主表面的方式安装在第一连接构件上；以及钎料凸块，该钎料凸块将第一连接焊垫连接到第二连接焊垫并且由包含Bi和Sn的金属制成，其中该钎料凸块包括形成为靠近第二连接焊垫的第一界面层、形成为靠近第一连接焊垫的第二界面层、形成为靠近第一界面层或第二界面层中的任一个的第一中间区域、以及形成为靠近第一界面层和第二界面层中的另一个并且形成为靠近第一中间区域的第二中间区域；第一中间区域中的Bi的浓度高于第一中间区域中的Sn的浓度；以及第二中间区域中的Sn的浓度高于第二中间区域中的Bi的浓度。
附图说明
图1A是示出根据第一实施方案的半导体器件的构造的俯视图；
图1B是沿着图1A的IB-IB线的横截面视图；
图1C是示出形成在图1A的构件中的布线图案的一个实例的俯视图；
图2A是示出用于第一实施方案的钎料凸块的结构的横截面视图；
图2B是示出根据第一实施方案的一个修改方案的钎料凸块的结构的横截面视图；
图3A是示出图2A的钎料凸块的形成工艺的视图(No.1)；
图3B是示出图2A的钎料凸块的形成工艺的视图(No.2)；
图3C是示出图2B的钎料凸块的形成工艺的视图；
图4是Sn-Bi二元体系的相图；
图5A是示出钎料凸块的初始状态的SEM图像；
图5B是示出关于样品1的钎料凸块的最终状态的SEM图像；
图5C是示出关于样品2的钎料凸块的最终状态的SEM图像；
图6是示出钎料凸块的另一个修改方案的横截面视图；
图7A是说明根据第二实施方案的半导体器件的制造工艺的第一部分的视图(No.1)；
图7B是说明根据第二实施方案的半导体器件的制造工艺的第一部分的视图(No.2)；
图7C是说明根据第二实施方案的半导体器件的制造工艺的第一部分的视图(No.3)；
图7D是说明根据第二实施方案的半导体器件的制造工艺的第一部分的视图(No.4)；
图8A是说明根据第二实施方案的半导体器件的制造工艺的第二部分的另一个视图(No.1)；
图8B是说明根据第二实施方案的半导体器件的制造工艺的第二部分的另一个视图(No.2)；
图8C是说明根据第二实施方案的半导体器件的制造工艺的第二部分的另一个视图(No.3)；
图8D是说明根据第二实施方案的半导体器件的制造工艺的第二部分的另一个视图(No.4)；
图8E是说明根据第二实施方案的半导体器件的制造工艺的第二部分的另一个视图(No.5)；
图8F是说明根据第二实施方案的半导体器件的制造工艺的第二部分的另一个视图(No.6)；
图9A是说明根据第二实施方案的半导体器件的制造工艺的第三部分的又一个视图(No.1)；
图9B是说明根据第二实施方案的半导体器件的制造工艺的第三部分的又一个视图(No.2)；
图9C是说明根据第二实施方案的半导体器件的制造工艺的第三部分的又一个视图(No.3)；
图9D是说明根据第二实施方案的半导体器件的制造工艺的第三部分的又一个视图(No.4)；
图10是示出根据第三实施方案的半导体器件的构造的横截面视图；
图11是示出根据第四实施方案的半导体器件的构造的横截面视图；以及
图12是示出根据第五实施方案的电子器件的立体图。
具体实施方式
(第一实施方案)
图1A是示出根据第一实施方案的半导体器件20的构造的俯视图。图1B示出沿着图1A中的IB-IB线的横截面视图。
参考图1A和图1B，半导体器件20具有电路板11(第一连接构件)和半导体芯片21(第一/快速半导体芯片)，并且半导体芯片21被倒装安装在电路板11的安装表面11A(第一主表面)上。
在更详细地描述时，半导体芯片21具有其上形成大规模集成电路(LSI)的电路形成表面21A。在电路形成表面21A上，包含铜(Cu)的多个电极焊垫21a(第二连接焊垫21a)例如以矩阵形状形成。与之相比，在电路板11上，对应于电极焊垫21a并且同样地包含铜的电极焊垫11a(第一连接焊垫11a)以矩阵形状例如形成在面向半导体芯片21的电路形成表面21A的安装表面11A上。
半导体芯片21以电路形成表面21A面向电路板11的安装表面11A的方式被安装在电路板11上。电极焊垫21a通过Sn-Bi钎料凸块31A电连接且机械连接至对应的电极焊垫11a。
在电路板11的安装表面11A上，各自包含铜的多个布线图案11b例如如图1C的俯视图所示来形成。每个布线图案11b从电极焊垫11a延伸到对应于电极焊垫11a设置在安装表面11A上的电极焊垫11c。在电路板11中，用粗虚线示意性地示出的通孔塞11C对应于电极焊垫11a来形成。通孔塞11C从安装表面11A穿过电路板11延伸到面对的后表面11B(第二主表面)。图1C是电路板11的安装表面11A除去半导体芯片21的俯视图。在图1C中，用对应于除去状态的细虚线来示出半导体芯片21。在后表面11B上，具有尺寸大于电极焊垫11a的尺寸的电极焊垫11d对应于通孔塞11C例如以大于电极焊垫11a的间距的间距以基本上的矩阵形状来形成。在每个电极焊垫11d上，形成有大于电极焊垫11a的钎料凸块11D。电极焊垫11d也可以用铜形成，而钎料凸块11D也可以由与钎料凸块31A相同的Sn-Bi钎料形成。
在具有这种构造的半导体器件20中，在电路板11上倒装安装的半导体芯片21的电极焊垫21a通过钎料凸块31A、在电路板11的安装表面11A上的电极焊垫11a、在安装表面11A上的布线图案11b和电极焊垫11c、通孔电极(through electrode)11C以及对应的电极焊垫11d来电连接至钎料凸块11D。电路板11可以在安装表面11A上、在电路板11中或者另外地在后表面11B上设置有其他的有源元件或无源元件。
图2A是详细地示出钎料凸块31A的构造的横截面视图；
参考图2A，在本实施方案中，在钎料凸块31A中的层叠状态下，包含铜-锡(Cu-Sn)合金的第一界面层31a形成为接触包含铜的电极焊垫21a，包含铜-锡合金的第二界面层31b形成为接触同样包含铜的电极焊垫11a，并且包含浓度为85重量％或更大的Bi(铋)作为主要成分的第一中间区域31c形成为接触第一界面层31a接触。此外，在第一中间区域31c和第二界面层31b之间形成第二中间区域31d。包含含有高浓度Sn的铜-锡合金的第二中间区域31d通过集中到钎料凸块的第二界面层31b的附近的Sn与在第二界面层31b中的铜反应来形成。
例如，当钎料凸块31A的直径为约100μm时，第一中间区域31c和第二中间区域31d的厚度分别达到例如65μm和35μm。
图2B示出图2A的实施方案的修改方案。在图2B的修改方案中，第一中间区域31c形成为接触第二界面层31b，而第二中间区域31d形成为接触第一界面层31a。
通过如下文所述使用共晶Sn-Bi钎料作为钎料凸块31A来例如在139℃的回流温度下将半导体芯片21接合到电路板11上、然后将直流电施加到钎料凸块31A以诱导电迁移并且以具有熔点例如超过仍高于原始Sn-Bi钎料的熔点的215℃的特征，来形成如图2A和图2B所示的第一中间区域31c和第二中间区域31d。
如下文所述，通过使用共晶Sn-Bi钎料作为钎料凸块31A来例如在139℃的回流温度下将半导体芯片21接合到电路板11上、随后将直流电施加到钎料凸块31A以诱导电迁移，来形成如图2A和图2B所示的第一中间区域31c和第二中间区域31d，从而，钎料凸块31A具有熔点例如超过215℃的特征，所述215℃仍高于原始Sn-Bi钎料的熔点。
因此，注意，虽然在低回流温度下形成图2A和图2B的钎料凸块31A，但是，即使在环境温度几乎增加至回流温度以上，钎料凸块31A也不再熔化，从而稳定地保持半导体芯片21与电路板11之间的电连接和机械连接。
在下文中，参考图3A和图3B对图2A的结构的形成工艺进行描述。
参考图3A，在本实施方案中，通过在氮气氛中在139℃的温度下回流具有基本上共晶组成的Sn-Bi钎料凸块31Aa来将半导体芯片21接合到电路板11上。通过伴有回流的热处理，在钎料凸块31Aa中，第一界面层31a在与电极焊垫21a的接合部分由铜-锡合金形成，并且第二界面层31b在与电极焊垫11a的接合部分同样由铜-锡合金形成。在下文中，图3A的状态被称为“初始状态”。
接下来，如图3B所示，在本实施方案中，使用电极焊垫21a作为阳极并且使用电极焊垫31b作为阴极来将直流电I施加到钎料凸块31Aa。已知：当直流电I被施加到Sn-Bi钎料时，通过电迁移，Bi集中到阳极而Sn集中到阴极(Microstructural Changes in Micro-joins between Sn-58BiSolders and Copper by Electro-migration ICEP 2010 Proceedings FA2-1，第475-478页和Otake等人的16th Symposium on“Microjoining andAssembly Technology in Electronics”，2月2-3日，2010，Yokohama)。
然后，在本实施方案中，利用电迁移现象在起初为均匀的钎料凸块31Aa中引发偏析以形成富含Bi的第一中间区域31c和富含Sn的第二中间区域31d。
图4是Sn-Bi二元体系的相图。
参考图4，当Sn-Bi钎料具有基本上共晶的组成时，熔点为约139℃。因此，可以通过在这样的低温下接合而不在用于半导体芯片21中的低K材料或类似材料中产生过度热应力的情况下来形成图3A的结构。
此外，通过执行图3B的通电工艺，在第一中间区域31c中，Bi的浓度变得高于与共晶组成基本上对应的初始组成的Bi的浓度，因而第一中间区域31c的熔化温度变得高于初始组成的熔化温度。类似地，在第二中间区域31d中，Sn的浓度也变得高于初始构造的Sn的浓度，从而第二中间区域31d的熔化温度也变得高于初始构造的熔化温度。更具体地，获得了优选特征，使得在接合期间在如上所述发生偏析的钎料凸块31A中熔化温度变得比钎料凸块31Aa的熔化温度更高。在下文中，图3B的状态被称为“最终状态”。
图5A是与图3A的初始状态对应的沿着就在回流之后并在施加直流电I之前的钎料凸块31Aa的VA-VA线的截面的SEM(扫描电子显微镜)图像。
参考图5A，发现：在共晶合金中形成特征组织，其中富含Bi的亮域和富含Sn的暗域几乎均匀地混合在钎料凸块31Aa中。
与之相比，图5B示出沿着在通电之后即在最终状态下的钎料凸块31A的图3B的VB-VB线的横截面结构。
参考图5B，具有Cu6Sn5组成的合金(金属间化合物)层沿着电极焊垫21a的表面形成为第一界面层31a。此外，具有Cu3Sn组成的合金(金属间化合物)层沿着电极焊垫11a的表面形成为第二界面层31b。
此外，主要包含Bi而基本上不包含Sn的第一中间区域31c以层的形状形成为靠近第一界面层31a，并且主要包含Cu6Sn5合金(金属间化合物)而基本上不包含Bi的区域作为整体以层的形状形成在第一中间区域31c与第二界面层31b之间，从而形成第二中间区域31d。在以1.0×108Am-2至2.0×108Am-2的电流密度将直流电施加在图5A的结构中而不从电极焊垫21a向电极焊垫11a加热的情况下，获得图5B的组织，这对应于后面描述的实施例1。
图5C示出在与后面描述的实施例2对应的另一个样品的最终状态下的沿着在图3B的通电之后的钎料凸块31A的VC-VC线的横截面结构。
参考图5C，具有Cu6Sn5组成的合金(金属间化合物)层以与图5B的情况中的方式相同的方式沿着电极焊垫21a的表面形成为第一界面层31a，并且具有Cu3Sn组成的合金(金属间化合物)层沿着电极焊垫11a的表面形成为第二界面层31b。
此外，同样在图5C的组织中，主要包含Bi而基本上不包含Sn的第一中间区域31c以层的形状形成为靠近界面层31a。此外，在第一中间区域31c与第二界面层31b之间，主要包含Cu6Sn5合金(金属间化合物)而基本上不包含Sn的区域以层的形状形成，从而形成第二中间区域31d。在以1.0×108Am-2至2.0×108Am-2的电流密度将直流电施加在图5A的结构中同时从电极焊垫21a向电极焊垫11a将待由Sn-Bi钎料31Aa连接的电极焊垫21a和电极焊垫11a的接合部分加热到100℃或更高的情况下，获得图5C的组织。
图5B和图5C中描述的结果示出：Cu通过扩散从施加直流电时作为阴极的电极焊垫11a移动到钎料凸块31Aa中，并且通过扩散进行移动的Cu通过与存在于钎料凸块31Aa中的Sn反应来形成钎料凸块31A中的界面层31b和中间区域31d。图5B和图5C中描述的结果示出：Cu通过扩散从施加直流电时作为阳极的电极焊垫21a移动到钎料凸块31Aa中，并且通过扩散进行移动的Cu通过与存在于钎料凸块31Aa中的Sn反应来形成钎料凸块31A中的界面层31a。
在下文中，对特定实施例进行描述。
(实施例1)
电极焊垫21a通过电解镀覆Cu膜以10μm的膜厚度形成在半导体芯片21的电路形成表面21A上。电极焊垫11a也通过电解镀覆Cu膜以10μm的膜厚度形成在电路板11的安装表面11A(第一主表面)上。然后，对应于图3A的工艺使用包含比例为40重量％至70重量％的Bi组分并且具有基本上共晶组成的Sn-Bi钎料作为钎料凸块31Aa，通过在氮气氛中在139℃的温度下回流钎料凸块31A来将半导体芯片21安装在电路板11上。
此外，使用电极焊垫21a作为阳极并且使用电极焊垫11a作为阴极来在此状态下将直流电I从阳极21a侧向阴极11a侧施加到钎料凸块31A并且持续5小时，换言之，从阴极11a侧向阳极21a侧施加电子流e-。在本实验中，在通电期间不有意从外部加热钎料凸块31Aa。
通过这样的实验获得具有以上在图5B中示出的其中发生Bi和Sn的偏析的层组织的钎料凸块31A。
半导体芯片21被倒装安装在电路板11上这样获得的半导体器件20被确认电连接，然后在-25℃到+125℃之间的温度下经历500个循环的温度循环测试。于是，确认了钎料凸块31A将连接部分的电阻的增加抑制到10％或更低。此外，使所述半导体器件20在温度为121℃并且湿度为85％的环境中静置1000小时，然后研究连接部分的电阻。于是，确认了电阻的增加为10％或更低。
(实施例2)
电极焊垫21a通过电解镀覆Cu膜以10μm的膜厚度形成在半导体芯片21的电路形成表面21A上。电极焊垫11a也通过电解镀覆Cu膜以10μm的膜厚度形成在电路板11的安装表面11A上。向电极焊垫21a和11a的表面施加熔剂，然后，对应于图3A的工艺使用包含比例为40重量％至70重量％的Bi组分并且具有基本上共晶组成的Sn-Bi钎料作为钎料凸块31Aa，通过在氮气氛中在139℃的温度下回流钎料凸块31A来将半导体芯片21安装在电路板11上。
此外，使用电极焊垫21a作为阳极并且使用电极焊垫11a作为阴极来在此状态下将直流电I从阳极21a侧向阴极11a侧施加到钎料凸块31A并且持续5小时，换言之，从阴极11a侧向阳极21a侧施加电子流e-。在本实验中，通过在通电期间从外部加热将钎料凸块31Aa的温度升高到100℃或更高且139℃或更低的温度。
通过这样的实验获得：具有以上在图5C中示出的其中发生Bi和Sn的偏析的层组织的钎料凸块31A。
半导体芯片21被倒装安装在电路板11上这样获得的半导体器件20被确认电连接，然后在-25℃到+125℃之间的温度下经历500个循环的温度循环测试。于是，确认了钎料凸块31A将连接部分的电阻的增加抑制到10％或更低。此外，使所述半导体器件20在温度为121℃并且湿度为85％的环境中静置1000小时，然后研究连接部分的电阻。于是，确认了电阻的增加为10％或更低。
(实施例3)
因而，在本实施方案中，可以使用铜(Cu)作为电极焊垫21a和11a。然而，除此之外，也可以使用与Sn一起形成金属间化合物的其他的金属元素，例如镍(Ni)。
电极焊垫21a通过电解镀覆镍(Ni)膜以10μm的膜厚度形成在半导体芯片21的电路形成表面21A上。电极焊垫11a也通过电解镀覆镍膜以10μm的膜厚度形成在电路板11的安装表面11A上。向电极焊垫21a和11a的表面施加熔剂，然后，对应于图3A的工艺使用包含比例为40重量％至70重量％的Bi组分并且具有基本上共晶组成的Sn-Bi钎料作为钎料凸块31Aa，通过在氮气氛中在139℃的温度下回流钎料凸块31A来将半导体芯片21安装在电路板11上。
此外，使用电极焊垫21a作为阳极并且使用电极焊垫11a作为阴极来在此状态下将直流电I从阳极21a侧向阴极11a侧施加到钎料凸块31A并且持续5小时，换言之，从阴极11a侧向阳极21a侧施加电子流e-。
半导体芯片21被倒装安装在电路板11上这样获得的半导体器件20被确认电连接，然后在-25℃到+125℃之间的温度下经历500个循环的温度循环测试。于是，确认了钎料凸块31A将连接部分的电阻的增加抑制到10％或更低。此外，使所述半导体器件20在温度为121℃并且湿度为85％的环境中静置1000小时，然后研究连接部分的电阻。于是，确认了电阻的增加为10％或更低。
(实施例4)
如上所述，在本实施方案中，尽管不仅可以使用铜而且可以使用镍作为电极焊垫21a和11a，但是也可以使用与Sn一起形成金属间化合物的其他的金属元素，例如锑(Sb)、钯(Pd)、银(Ag)、金(Au)、铂(Pt)、钴(Co)或类似元素。
电极焊垫21a通过电解镀覆钯(Pd)膜以3至4μm的膜厚度形成在半导体芯片21的电路形成表面21A上。
电极焊垫11a也通过电解镀覆钯膜以3至4μm的膜厚度形成在电路板11的安装表面11A上。向电极焊垫21a和11a的表面施加熔剂，然后，对应于图3A的工艺使用包含比例为40重量％至70重量％的Bi组分并且具有基本上共晶组成的Sn-Bi钎料作为钎料凸块31Aa，通过在氮气氛中在139℃的温度下回流钎料凸块31A来将半导体芯片21安装在电路板11上。
在本实施方案中，通过减小通电期间的电流密度或者通过减少通电时间也可以将具有Sn浓度高于初始组成的Sn浓度的Sn-Bi合金层形成为如图6所示的第二中间区域31d。
此外，使用电极焊垫21a作为阳极并且使用电极焊垫11a作为阴极来在此状态下将直流电I从阳极21a侧向阴极11a侧施加到钎料凸块31A，换言之，从阴极11a侧向阳极21a侧施加电子流e-持续3小时。
半导体芯片21被倒装安装在电路板11上这样获得的半导体器件20被确认电连接，然后在-25℃到+125℃之间的温度下经历500个循环的温度循环测试。于是，确认了钎料凸块31A将连接部分的电阻的增加抑制到10％或更低。此外，使所述半导体器件20在温度为121℃并且湿度为85％的环境中静置1000小时，然后研究连接部分的电阻。于是，确认了电阻的增加为10％或更低。
在本实施方案中，施加直流电的方向不限于如图3B所示的从电极焊垫21a向电极焊垫11a的方向，而也可以被设置成如图3C所示出的从电极焊垫11a向电极焊垫21a的方向。在此情况下，电极焊垫11a用作阳极而电极焊垫21a用作阴极，并且在钎料凸块31A中，形成如下的结构：如以上参考图2B所述的，第一中间区域31c形成为靠近第二界面层31b，并且第二中间区域31d形成为靠近第一界面层31a。
(第二实施方案)
在下文中，参考图7A至图7D、图8A至图8D、图9A、图9B、图10A、图10B、图11A至图11D对用于制造根据第二实施方案的半导体器件20的方法进行描述。
参考图7A，通过溅射方法在半导体芯片21的电路形成表面21A上以例如50nm至200nm的膜厚度形成薄铜膜或镍膜21s作为用于电解镀覆的籽层。此外，如图7B所示，在籽层21s上形成具有与待形成的电极焊垫21a对应的开口部分R1A的光刻胶膜R1。
然后，通过将图7B的结构浸没在铜或镍的电解镀覆浴中并且使用籽层21s作为电极来执行电解镀覆，如图7C所示，在籽层21s上对应于开口部R1A以例如1μm至5μm的膜厚度形成包含铜或镍的电极焊垫21a。
然后，如图7D所示，通过移除光刻胶膜R1，获得了如下的结构：电极焊垫21a形成在覆盖半导体芯片21的电路形成表面21A的籽层21s上。
相比之下，如图8A所示，通过例如溅射方法在电路板11的安装表面11A上以50nm至200nm的膜厚度形成薄铜膜或镍膜11s作为用于电解镀覆的籽层。然后，如图8B所示，在籽层11s上形成具有与待形成的电极焊垫11a对应的开口部分R2A的光刻胶膜R2。
通过将图8B的结构浸没在铜或镍的电解镀覆浴中并且使用籽层11s作为电极来执行电解镀覆，如图8C所示，在籽层11s上对应于开口部R2A以1μm至5μm的膜厚度形成包含铜或镍的电极焊垫11a。
然后，如图8D所示，通过移除光刻胶膜R2，获得了如下的结构：电极焊垫11a形成在覆盖电路板11的安装表面11A的籽层11s上。
然后，在本实施方案中，如图8E所示，在图8D的结构上形成光刻胶膜R3，然后将光刻胶膜R3曝光并且显影以形成如图8F所示的光刻胶图案R3A，使得光刻胶图案R3A保护与形成在之前参考图1C描述的电路板11的安装表面11A上的布线图11b对应的部分。
然后，如图9A所示，通过熔剂层将包含Sn-Bi合金并且具有接近于共晶组成的初始组成的钎料凸块31Aa例如支撑在图7D的结构的电极焊垫21a上。然后，将其中使钎料凸块31Aa如上所述支撑在电极焊垫21a上的半导体芯片21以如下方式安置在电路板11上：电路形成表面21A面向电路板11的安装表面11A，并且钎料凸块31Aa紧靠在处于安装表面11A上的电极焊垫11a上。
然后，在此状态下在139℃的温度下对初始组成的钎料凸块31Aa进行回流，从而半导体芯片21通过钎料凸块31Aa被安装在电路板11上。
接下来，如图9B所示，在籽层21s和籽层11s之间连接直流电源35，然后将直流电I从作为阳极的电极焊垫21a向作为阴极的电极焊垫11a施加到钎料凸块31Aa上，换言之，从作为阴极的电极焊垫11a向作为阳极的电极焊垫21a施加电子流e-。
因此，如之前参考图3A和图3B所描述的，在初始组成的钎料凸块31Aa中，Bi集中至电极焊垫21a即靠近阳极的一侧，从而形成第一中间区域31c，并且Sn集中至电极焊垫11a即靠近阴极的一侧，从而形成第二中间区域31d，使得初始组成的钎料凸块31Aa变成钎料凸块31A。
当在图9B的工艺中反转直流电I的方向时，获得了之前参考图2B描述的结构，在该结构中，第二中间区域31d形成为靠近第一界面层31a并且第一中间区域31c形成为靠近第二界面层31b。
接下来，如图9C所示，将图9B的结构浸没在例如包含硫酸氢钾作为主要成分的蚀刻剂37中例如1分钟。因而，通过蚀刻将籽层21s和籽层11s的未被光刻胶图案R3A保护的部分移除。执行该蚀刻仅用于移除薄籽层21s和11s，而厚电极焊垫21a和11a基本上不受影响。
在从蚀刻剂37中拉出之后，通过例如剥离液或类似物或在氧等离子体中的灰化或类似方法来移除光刻胶图案R3A以完成如下构造的半导体器件20：半导体芯片21通过钎料凸块31电连接并且机械连接到电路板11上，并且预定的布线图案11b形成在电路板11的安装表面11A上。
在本实施方案中，图7A至图7D的工艺中的任何一个工艺和图8A至图8F的工艺中的任何一个工艺可以被首先执行，但是可以被同时执行。
虽然在本实施方案中所述布线图案也形成在电路板11的后表面11B上，但是省略了说明。
根据上述的实施方案，通过对包含Sn-Bi合金的钎料凸块进行回流来接合半导体芯片和电路板或者接合第一连接构件和第二连接构件、然后向钎料凸块施加直流电，在钎料凸块中可以以彼此隔离的方式形成Bi浓度高的区域和Sn浓度高的区域。因此，可以使钎料凸块的熔化温度高于初始熔化温度。
(第三实施方案)
图10是示出根据第三实施方案的半导体器件40的轮廓的横截面视图。
参考图10，半导体器件40具有封装衬底41，该封装衬底41具有分别形成前表面和后表面的主表面41A和41B。***件42通过Sn-Bi钎料凸块41a被安装在封装衬底41的主表面41A上，并且***件42对应于上面的实施方案中的电路板11。另外，多个半导体芯片21通过各自包含钎料凸块31A的钎料凸块阵列431A被安装在***件42上，其中多个电路图案42Ckt以多层互连结构形成在***件42中。此外，在封装衬底41的主表面41B上，形成有用于安装在***板或类似结构上的不同的钎料凸块41b。
此外，尽管未示出，但是在封装衬底41的主表面41A和41B上形成有以多层互连结构的电路。
当组装这样的半导体器件40时，为了减小对半导体芯片21的热应力，在钎料凸块阵列431A中使用具有普通共晶组成的Sn-Bi钎料来将半导体芯片21安装在***件42上。此后，当***件42安装在封装衬底41上时，或者此外，以后当封装衬底41安装在电子器件的***板或类似结构上时，出现如下的问题：构成钎料凸块阵列431A的钎料凸块在用于回流钎料凸块41a和41b的热处理下再熔化。
为了解决此问题，在本实施方案中，当半导体芯片21安装在***件42上时，将直流电施加到钎料凸块31A以将钎料凸块31A隔离成如在上述的实施方案中所描述的富含Bi的区域即第一中间区域31c和富含Sn的区域即第二中间区域31d。因此，整个钎料凸块31A的熔化温度从安装过程中的初始温度例如139℃升高到215℃或更高。因此，即使当以后回流钎料凸块41a或41b时，钎料凸块31A也不再熔化。
类似地，在本实施方案中，***件42也经由钎料凸块41a被安装在封装衬底41上，然后施加直流电从而将钎料凸块41a隔离成其中富含Bi的区域和富含Sn的区域。因此，钎料凸块41a的熔化温度变得高于回流期间的温度，使得当安装封装衬底41时不发生钎料凸块41a的再熔化或类似的问题。并且当半导体器件40经历热循环测试和高温暴露测试时，连接不会变差。
因而，根据本实施方案，在多个部件堆叠且同时通过钎料凸块安装的构造中，可以在安装之后升高钎料凸块的熔化温度，使得可以高产量地制造高可靠性的电子器件。
(第四实施方案)
图11是示出根据第四实施方案的半导体器件60的构造的横截面视图。
参考图11，半导体器件60具有电路板61，该电路板61具有主表面61A和61B，其中半导体芯片62通过树脂层62C以面朝上的状态接合到电路板61的主表面61A上，即，其上形成半导体集成电路的电路形成表面是上侧，换言之，面向与电路板61相反的侧。
此外，半导体芯片21通过上述钎料凸块阵列431A以面朝下的状态安装在半导体芯片62上，并且半导体芯片62通过接合线62A和62B电连接到形成在电路板61的主表面61A上的电路图案。
在主表面61A上，半导体芯片62和21使用密封树脂63与接合线62A和62B密封在一起，并且多个通孔61t形成在电路板61中。在主表面61A上的电路图案通过通孔61t电连接到形成在主表面61B上的电路图案。
在主表面61B上，形成有多个钎料凸块61b。电路板61通过钎料凸块61b安装在例如服务器的各种电子设备的例如***板上。
同样在本实施方案中，在如上所述的139℃的低温下回流构成钎料凸块阵列431A的钎料凸块31A之后对该钎料凸块31A通电，因此，熔化温度升高到例如215℃或更高。
因此，即使当通过回流钎料凸块61b将半导体器件60安装在另一个衬底上时以及即使当这样形成的电子器件经历各种热循环测试和高温暴露测试时，构成钎料凸块阵列431A的钎料凸块31A也不再熔化。
因而，根据本实施方案，可以高产量地制造高可靠性的半导体器件。
(第五实施方案)
根据上述不同的实施方案的半导体器件可以被不同地应用，例如，从应用于针对所谓的高端使用的例如如图12所示具有***板71的服务器70的电子设备，到应用于针对大众使用的例如便携式电话和数码相机的电子设备的电路布线板。
参考图12，图10的半导体器件40或图11的半导体器件60例如通过钎料凸块41b或61b连同存储器模块71B或类似结构一起以支撑有散热构件71A的状态倒装安装在***板71上。
上面对优选实施方案进行了描述，但是实施方案不限于特定实施方案，而是可以在权利要求的范围内进行各种修改和变化。
附录
附录1.一种半导体器件，包括：
第一连接构件，所述第一连接构件包括形成在所述第一连接构件的第一主表面上的第一连接焊垫；
第一/快速半导体芯片，所述第一/快速半导体芯片包括其上形成半导体集成电路的电路形成表面以及形成在所述电路形成表面上的第二连接焊垫，所述第一/快速半导体芯片以所述电路形成表面面向所述第一主表面的方式安装在所述第一连接构件上；以及
钎料凸块，所述钎料凸块将所述第一连接焊垫连接到所述第二连接焊垫并且由包含Bi和Sn的金属制成，
其中所述钎料凸块包括形成为靠近所述第二连接焊垫的第一界面层、形成为靠近所述第一连接焊垫的第二界面层、形成为靠近所述第一界面层或所述第二界面层中的任一个的第一中间区域、以及形成为靠近所述第一界面层和所述第二界面层中的另一个并且形成为靠近所述第一中间区域的第二中间区域；
所述第一中间区域中的Bi的浓度高于所述第一中间区域中的Sn的浓度；以及
所述第二中间区域中的Sn的浓度高于所述第二中间区域中的Bi的浓度。
附录2.根据附录1所述的半导体器件，其中所述第一中间区域基本上不包含Sn，而所述第二中间区域基本上不包含Bi。
附录3.根据附录1所述的半导体器件，其中所述第一中间区域基本上不包含Sn，而所述第二中间区域由Sn和Bi的合金制成。
附录4.根据附录1至3中任一项所述的半导体器件，其中所述第二中间区域包含Sn与以下金属元素的金属间化合物或固溶体：所述金属元素构成所述第二连接焊垫或所述第一连接焊垫中的与所述第一界面层或所述第二界面层中靠近所述第二中间区域的所述另一个靠近的任一个所述焊垫。
附录5.根据附录1至4中任一项所述的半导体器件，其中所述金属元素选自铜、镍、锑、钯、银、金、铂和钴。
附录6.根据附录1至5中任一项所述的半导体器件，其中所述第一中间区域中的Bi的浓度超过85重量％。
附录7.根据附录1至6中任一项所述的半导体器件，其中所述第一连接构件是不同于所述第一/快速半导体芯片的第二半导体芯片。
附录8.根据附录1至6中任一项所述的半导体器件，其中所述第一连接构件是如下***件，所述***件包括面向所述第一主表面的第二主表面并且包括形成在所述第二主表面上并电连接至所述第一连接焊垫的第三连接焊垫。
附录9.根据附录8所述的半导体器件，还包括：
布线板，
其中所述半导体器件使用形成在所述第三连接焊垫上的第二钎料凸块来安装在所述布线板的主表面上。
附录10.一种电子器件，包括：
***板；以及
倒装安装在所述***板上的半导体器件，所述半导体器件包括：
第一连接构件，所述第一连接构件包括形成在所述第一连接构件的第一主表面上的第一连接焊垫；
第一/快速半导体芯片，所述第一/快速半导体芯片包括其上形成半导体集成电路的电路形成表面以及形成在所述电路形成表面上的第二连接焊垫，所述第一/快速半导体芯片以所述电路形成表面面向所述第一主表面的方式安装在所述第一连接构件上；以及
钎料凸块，所述钎料凸块将所述第一连接焊垫连接到所述第二连接焊垫并且由包含Bi和Sn的金属制成，
其中所述钎料凸块包括形成为靠近所述第二连接焊垫的第一界面层、形成为靠近所述第一连接焊垫的第二界面层、形成为靠近所述第一界面层或所述第二界面层中的任一个的第一中间区域、以及形成为靠近所述第一界面层和所述第二界面层中的另一个并且形成为靠近所述第一中间区域的第二中间区域；
所述第一中间区域中的Bi的浓度高于所述第一中间区域中的Sn的浓度；以及
所述第二中间区域中的Sn的浓度高于所述第二中间区域中的Bi的浓度。
附录11.一种半导体器件制造方法，包括：
在第一连接构件的第一主表面上形成第一连接焊垫；
在第一/快速半导体芯片的其上形成半导体集成电路的电路形成表面上形成第二连接焊垫；
将所述第一/快速半导体芯片以如下方式置于所述第一连接构件上：所述电路形成表面面向所述第一主表面并且所述第一连接焊垫通过包含Sn-Bi合金的钎料凸块接触所述第二连接焊垫；
使钎料凸块回流以用于接合所述第一连接焊垫和所述第二连接焊垫；以及
在所述第一连接焊垫与所述第二连接焊垫之间的所述接合之后，使用所述第一连接焊垫或所述第二连接焊垫中的任一个作为阳极并且使用所述第一连接焊垫和所述第二连接焊垫中的另一个作为阴极来施加直流电，以将所述钎料凸块中的Bi集中到所述阳极的附近并且将所述钎料凸块中的Sn集中到所述阴极的附近。
附录12.根据附录11所述的半导体器件制造方法，其中在加热所述钎料凸块时实施所述直流电的施加。
附录13.根据附录11至12中任一项所述的半导体器件制造方法，其中在100℃或更高的温度下实施所述直流电的施加，并且所述钎料凸块在所述温度下不熔化。
附录14.根据附录11至13中任一项所述的半导体器件制造方法，其中在1.0×108Am-2至2.0×108Am-2范围内的电流密度下实施所述直流电的施加。
附录15.根据附录11至14中任一项所述的半导体器件制造方法，其中通过以如下方式设定电流密度和施加时间来实施所述直流电的施加：在所述阳极的附近形成基本上不包含Sn的第一中间区域并且在所述阴极的附近形成基本上不包含Bi的第二中间区域。
附录16.根据附录11至14中任一项所述的半导体器件制造方法，其中通过以如下方式设定电流密度和施加时间来实施所述直流电的施加：在所述阳极的附近形成基本上不包含Sn的第一中间区域并且在所述阴极的附近形成包含Sn和Bi的第二中间区域。
附录17.根据附录11至16中任一项所述的半导体器件制造方法，其中
形成所述第一连接焊垫包括形成第一金属膜，所述第一金属膜形成在所述第一主表面上并且连接至所述第一连接焊垫以用作通向所述第一连接焊垫的第一导电路径；
形成所述第二连接焊垫包括形成第二金属膜，所述第二金属膜形成在所述电路形成表面上并且连接至所述第二连接焊垫以用作通向所述第二连接焊垫的第二导电路径；以及
通过所述第一导电路径和所述第二导电路径实施所述直流电的施加。
附录18.根据附录17所述的半导体器件制造方法，还包括：
在所述施加直流电之后，通过湿法蚀刻移除所述第一金属膜和所述第二金属膜。
附录19.根据附录11至18中任一项所述的半导体器件制造方法，其中在所述施加直流电的过程中，所述第一连接焊垫和所述第二连接焊垫的材料通过扩散移动到所述钎料凸块中，以与锡形成金属间化合物相或固溶体。
附录20.根据附录19所述的半导体器件制造方法，其中所述材料选自铜、镍、锑、钯、银、金、铂和钴。

Claims (20)

1.一种半导体器件，包括：
第一连接构件，所述第一连接构件包括形成在所述第一连接构件的第一主表面上的第一连接焊垫；
第一/快速半导体芯片，所述第一/快速半导体芯片包括其上形成半导体集成电路的电路形成表面以及形成在所述电路形成表面上的第二连接焊垫，所述第一/快速半导体芯片以所述电路形成表面面向所述第一主表面的方式安装在所述第一连接构件上；以及
钎料凸块，所述钎料凸块将所述第一连接焊垫连接到所述第二连接焊垫并且由包含Bi和Sn的金属制成，
其中所述钎料凸块包括形成为靠近所述第二连接焊垫的第一界面层、形成为靠近所述第一连接焊垫的第二界面层、形成为靠近所述第一界面层或所述第二界面层中的任一个的第一中间区域、以及形成为靠近所述第一界面层和所述第二界面层中的另一个并且形成为靠近所述第一中间区域的第二中间区域；
所述第一中间区域中的Bi的浓度高于所述第一中间区域中的Sn的浓度；以及
所述第二中间区域中的Sn的浓度高于所述第二中间区域中的Bi的浓度。
2.根据权利要求1所述的半导体器件，其中所述第一中间区域基本上不包含Sn，所述第二中间区域基本上不包含Bi。
3.根据权利要求1所述的半导体器件，其中所述第一中间区域基本上不包含Sn，所述第二中间区域由Sn和Bi的合金制成。
4.根据权利要求1所述的半导体器件，其中所述第二中间区域包含Sn与以下金属元素的金属间化合物或固溶体：所述金属元素构成所述第二连接焊垫或所述第一连接焊垫中的与所述第一界面层或所述第二界面层中靠近所述第二中间区域的所述另一个靠近的任一个所述焊垫。
5.根据权利要求4所述的半导体器件，其中所述金属元素选自铜、镍、锑、钯、银、金、铂和钴。
6.根据权利要求1所述的半导体器件，其中所述第一中间区域中的Bi的浓度超过85重量％。
7.根据权利要求1所述的半导体器件，其中所述第一连接构件是不同于所述第一/快速半导体芯片的第二半导体芯片。
8.根据权利要求1所述的半导体器件，其中所述第一连接构件是包括面向所述第一主表面的第二主表面并且包括形成在所述第二主表面上且电连接至所述第一连接焊垫的第三连接焊垫的***件。
9.根据权利要求8所述的半导体器件，还包括：
布线板，
其中所述半导体器件使用形成在所述第三连接焊垫上的第二钎料凸块来安装在所述布线板的主表面上。
10.一种电子器件，包括：
***板；以及
倒装地安装在所述***板上的半导体器件，所述半导体器件包括：
第一连接构件，所述第一连接构件包括形成在所述第一连接构件的第一主表面上的第一连接焊垫；
第一/快速半导体芯片，所述第一/快速半导体芯片包括其上形成半导体集成电路的电路形成表面以及形成在所述电路形成表面上的第二连接焊垫，所述第一/快速半导体芯片以所述电路形成表面面向所述第一主表面的方式安装在所述第一连接构件上；以及
钎料凸块，所述钎料凸块将所述第一连接焊垫连接到所述第二连接焊垫并且由包含Bi和Sn的金属制成，
其中所述钎料凸块包括形成为靠近所述第二连接焊垫的第一界面层、形成为靠近所述第一连接焊垫的第二界面层、形成为靠近所述第一界面层或所述第二界面层中的任一个的第一中间区域、以及形成为靠近所述第一界面层和所述第二界面层中的另一个并且形成为靠近所述第一中间区域的第二中间区域；
所述第一中间区域中的Bi的浓度高于所述第一中间区域中的Sn的浓度；以及
所述第二中间区域中的Sn的浓度高于所述第二中间区域中的Bi的浓度。
11.一种半导体器件制造方法，包括：
在第一连接构件的第一主表面上形成第一连接焊垫；
在第一/快速半导体芯片的其上形成半导体集成电路的电路形成表面上形成第二连接焊垫；
将所述第一/快速半导体芯片以如下方式置于所述第一连接构件上：所述电路形成表面面向所述第一主表面并且所述第一连接焊垫通过包含Sn-Bi合金的钎料凸块接触所述第二连接焊垫；
使钎料凸块回流以用于接合所述第一连接焊垫和所述第二连接焊垫；以及
在所述第一连接焊垫与所述第二连接焊垫之间的所述接合之后，使用所述第一连接焊垫或所述第二连接焊垫中的任一个作为阳极并且使用所述第一连接焊垫和所述第二连接焊垫中的另一个作为阴极来施加直流电，以将所述钎料凸块中的Bi集中到所述阳极的附近并且将所述钎料凸块中的Sn集中到所述阴极的附近。
12.根据权利要求11所述的半导体器件制造方法，其中在加热所述钎料凸块时实施所述直流电的施加。
13.根据权利要求12所述的半导体器件制造方法，其中在100℃或更高的温度下实施所述直流电的施加，并且所述钎料凸块在所述温度下不熔化。
14.根据权利要求11所述的半导体器件制造方法，其中在1.0×108Am-2至2.0×108Am-2范围内的电流密度下实施所述直流电的施加。
15.根据权利要求11所述的半导体器件制造方法，其中通过以如下方式设定电流密度和施加时间来实施所述直流电的施加：在所述阳极的附近形成基本上不包含Sn的第一中间区域并且在所述阴极的附近形成基本上不包含Bi的第二中间区域。
16.根据权利要求11所述的半导体器件制造方法，其中通过以如下方式设定电流密度和施加时间来实施所述直流电的施加：在所述阳极的附近形成基本上不包含Sn的第一中间区域并且在所述阴极的附近形成包含Sn和Bi的第二中间区域。
17.根据权利要求11所述的半导体器件制造方法，其中
形成所述第一连接焊垫包括形成第一金属膜，所述第一金属膜形成在所述第一主表面上并且连接至所述第一连接焊垫以用作通向所述第一连接焊垫的第一导电路径；
形成所述第二连接焊垫包括形成第二金属膜，所述第二金属膜形成在所述电路形成表面上并且连接至所述第二连接焊垫以用作通向所述第二连接焊垫的第二导电路径；以及
通过所述第一导电路径和所述第二导电路径实施所述直流电的施加。
18.根据权利要求17所述的半导体器件制造方法，还包括：
在施加所述直流电之后，通过湿法蚀刻移除所述第一金属膜和所述第二金属膜。
19.根据权利要求11所述的半导体器件制造方法，其中在施加所述直流电的过程中，所述第一连接焊垫和所述第二连接焊垫的材料通过扩散移动到所述钎料凸块中，以与锡形成金属间化合物相或固溶体。
20.根据权利要求19所述的半导体器件制造方法，其中所述材料选自铜、镍、锑、钯、银、金、铂和钴。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104602450A (zh) * 2014-12-31 2015-05-06 京东方科技集团股份有限公司 电路板及其制造方法和显示装置
CN111630646A (zh) * 2018-12-28 2020-09-04 Ｊｘ金属株式会社 焊料接合部

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6037300B2 (ja) * 2012-03-15 2016-12-07 パナソニックＩｐマネジメント株式会社 回路部材接合構造体
KR102105634B1 (ko) * 2013-10-02 2020-04-28 에스케이하이닉스 주식회사 신뢰성 있는 본딩 구조를 갖는 금속 배선 구조, 집적 회로, 집적 회로 패키지 및 이들의 제조 방법
JP2015072996A (ja) 2013-10-02 2015-04-16 新光電気工業株式会社 半導体装置
KR101731700B1 (ko) * 2015-03-18 2017-04-28 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
JP6217836B1 (ja) * 2016-12-07 2017-10-25 千住金属工業株式会社 核材料および半導体パッケージおよびバンプ電極の形成方法
US10586782B2 (en) 2017-07-01 2020-03-10 International Business Machines Corporation Lead-free solder joining of electronic structures
JP2019145546A (ja) * 2018-02-16 2019-08-29 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法
US10903186B2 (en) * 2018-10-19 2021-01-26 Toyota Motor Engineering & Manufacturing North America, Inc. Power electronic assemblies with solder layer and exterior coating, and methods of forming the same
CN112151401B (zh) * 2020-10-12 2023-08-18 电子科技大学 一种基于半导体温控的晶粒取向控制方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1330398A (zh) * 2000-06-16 2002-01-09 国际商业机器公司 管芯级封装及其制造方法
US20070284741A1 (en) * 2005-06-30 2007-12-13 Intel Corporation Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same
US20080105984A1 (en) * 2006-11-03 2008-05-08 Samsung Electronics Co., Ltd. Semiconductor chip stack package with reinforcing member for preventing package warpage connected to substrate
CN101233613A (zh) * 2005-08-11 2008-07-30 德州仪器公司 具有改进的机械可靠性和热可靠性的半导体装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4011214B2 (ja) * 1998-11-13 2007-11-21 富士通株式会社 半導体装置及び半田による接合方法
US7168608B2 (en) * 2002-12-24 2007-01-30 Avago Technologies General Ip (Singapore) Pte. Ltd. System and method for hermetic seal formation
JP4961165B2 (ja) * 2006-06-02 2012-06-27 日立協和エンジニアリング株式会社 電子部品搭載用基板、電子部品および電子装置
KR20090039411A (ko) * 2007-10-18 2009-04-22 삼성전자주식회사 솔더 볼과 칩 패드가 접합된 구조를 갖는 반도체 패키지,모듈, 시스템 및 그 제조방법
JP5035134B2 (ja) * 2008-06-20 2012-09-26 富士通株式会社 電子部品実装装置及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1330398A (zh) * 2000-06-16 2002-01-09 国际商业机器公司 管芯级封装及其制造方法
US20070284741A1 (en) * 2005-06-30 2007-12-13 Intel Corporation Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same
CN101233613A (zh) * 2005-08-11 2008-07-30 德州仪器公司 具有改进的机械可靠性和热可靠性的半导体装置
US20080105984A1 (en) * 2006-11-03 2008-05-08 Samsung Electronics Co., Ltd. Semiconductor chip stack package with reinforcing member for preventing package warpage connected to substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104602450A (zh) * 2014-12-31 2015-05-06 京东方科技集团股份有限公司 电路板及其制造方法和显示装置
WO2016107143A1 (zh) * 2014-12-31 2016-07-07 京东方科技集团股份有限公司 电路板及其制造方法，和显示装置
US10178771B2 (en) 2014-12-31 2019-01-08 Boe Technology Group Co., Ltd. Circuit board, manufacturing method thereof and display apparatus
CN111630646A (zh) * 2018-12-28 2020-09-04 Ｊｘ金属株式会社 焊料接合部

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