CN103084950A - 晶片加工方法 - Google Patents
晶片加工方法 Download PDFInfo
- Publication number
- CN103084950A CN103084950A CN2012104334820A CN201210433482A CN103084950A CN 103084950 A CN103084950 A CN 103084950A CN 2012104334820 A CN2012104334820 A CN 2012104334820A CN 201210433482 A CN201210433482 A CN 201210433482A CN 103084950 A CN103084950 A CN 103084950A
- Authority
- CN
- China
- Prior art keywords
- wafer
- stacked
- chamfered section
- processing method
- grinding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000003672 processing method Methods 0.000 title claims abstract description 19
- 238000005520 cutting process Methods 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000012423 maintenance Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 description 120
- 239000004065 semiconductor Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000007767 bonding agent Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
- B24B7/20—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground
- B24B7/22—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
- B24B7/228—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain for grinding thin, brittle parts, e.g. semiconductors, wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Mechanical Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
Abstract
本发明提供一种晶片加工方法,在不使晶片破损的前提下比以往时间短且廉价地将晶片薄化至预定厚度。其为将在外周具有倒角部的晶片薄化至预定厚度的晶片加工方法,其特征在于具备:层叠晶片形成步骤,将晶片的表面贴附于支承基板上以形成层叠晶片;倒角部除去步骤,将切削刀具定位于所述晶片的表面侧的外周侧面,并从在所述层叠晶片形成步骤形成的层叠晶片的外周侧向中心切入,将从所述晶片的表面至所述预定厚度的倒角部除去,所述切削刀具具有与所述层叠晶片的层叠方向平行的旋转轴线;以及薄化步骤,在所述倒角部除去步骤实施后,对所述层叠晶片的所述晶片的背面侧进行磨削以将晶片薄化至预定厚度。
Description
技术领域
本发明涉及将形成于晶片的外周部的倒角部除去以使晶片薄化至预定厚度的晶片加工方法。
背景技术
半导体晶片在表面形成大量的IC(Integrated Circuit,集成电路)、LSI(Large ScaleIntegration,大规模集成电路)等器件,且一个一个的器件由分割预定线(间隔道)划分开,在将所述半导体晶片通过磨削装置对背面进行磨削而加工至预定的厚度后,通过切削装置(切割装置)对分割预定线进行切削来分割出一个一个的器件,分割成的器件被广泛应用于手机、个人电脑等各种电子产品中。
对晶片背面进行磨削的磨削装置具备:卡盘工作台,其用于保持晶片;及磨削单元,其以能够旋转的方式装配有磨削轮,所述磨削轮具有磨削磨具,所述磨削磨具用于对保持在卡盘工作台上的晶片进行磨削,该磨削装置能够将晶片高精度地磨削至预定的厚度。
在晶片的磨削时,为了保护在表面形成的器件而在晶片的表面贴附表面保护带,之后利用磨削装置对晶片的背面进行磨削。不过,若通过磨削将晶片的厚度薄化至例如数十μm左右时,由于表面保护带的刚性无法对晶片平稳地保持,会整体地发生挠曲而成为不稳定状态,因而存在对磨削及后续的晶片处理产生阻碍的问题。
为了使通过磨削而薄化了的晶片的处理变得容易,在日本特开2000-158334号公报记载了下述方法:在将晶片的表面侧贴附在具有刚性的支承基板后,对晶片的背面进行磨削。
一般来说,在半导体晶片的外周形成有从表面到背面的圆弧状的倒角部,在对晶片背面进行磨削而使晶片薄化后,在倒角部残存有由圆弧面与磨削面形成的尖刃(檐状),既危险又会在外周部分产生缺损,从而存在器件的品质下降、晶片破损的问题。
为解决此问题,日本特开2000-173961号公报公开了下述半导体装置的制造方法:使形成于半导体晶片的外周的倒角部在与平坦部的交界部分的表面形成切口后,进行晶片的背面磨削直到晶片的板厚变得比切口深度薄。
专利文献1:日本特开2000-158334号公报
专利文献2:日本特开2000-173961号公报
然而,如专利文献2公开的半导体装置的制造方法,在将晶片贴附在支承基板或表面保护带之前从晶片的表面侧对晶片的倒角部与平坦部的交界进行切削的话,存在切削屑落在晶片的表面并附着在器件的表面而造成品质下降的问题。
特别是对于形成有多个CCD、CMOS等固体图像传感器的晶片,会造成固体图像传感器的成像性能下降的致命问题。为除去附着在表面的切削屑必须要进行过度的清洗。
在将晶片贴附在支承基板后除去倒角部的情况下,由于需要除去从晶片的背面侧到表面的倒角部,因而加工耗费时间。并且,需要比倒角部的宽度厚的切削刀具,不仅切削刀具本身的费用升高,而且伴随着连续加工,切削刀具容易发生不均匀磨损,因而需要频繁更换切削刀具。
另一方面,在使用比倒角部的宽度薄的切削刀具的情况下,需要在晶片外周部进行多次圆形切削加工,存在生产性不佳的问题。
发明内容
本发明正是鉴于以上各点而完成的,其目的在于提供一种晶片加工方法,在不使晶片破损的前提下比以往时间短且廉价地将晶片薄化至预定厚度。
根据本发明,提供一种晶片加工方法,所述晶片加工方法是将在外周具有倒角部的晶片薄化至预定厚度的晶片加工方法,其特征在于,所述晶片加工方法具备下述步骤:层叠晶片形成步骤,在该层叠晶片形成步骤中,将晶片的表面贴附于支承基板上而形成层叠晶片;倒角部除去步骤,在该倒角部除去步骤中,将切削刀具定位于在所述晶片的表面侧的外周侧面,从在所述层叠晶片形成步骤形成的层叠晶片的外周侧向中心切入,将从所述晶片的表面至预定厚度的倒角部除去,所述切削刀具具有与所述层叠晶片的层叠方向平行的旋转轴线;以及薄化步骤,在该薄化步骤中,在所述倒角部除去步骤实施后,对所述层叠晶片的所述晶片的背面侧进行磨削,将晶片薄化至预定厚度。
优选的是,还具备保持步骤,在该保持步骤中,在所述倒角部除去步骤实施前,以切削装置的卡盘工作台对所述层叠晶片的靠所述支承基板的那一侧进行保持,在所述倒角部除去步骤中,使具有与所述卡盘工作台的旋转轴线平行的旋转轴线的切削刀具定位于所述晶片的表面侧的外周侧面,从所述层叠晶片的外周侧向中心切入,使所述卡盘工作台至少旋转1周,从而将从所述晶片的表面至预定厚度的倒角部除去。
本发明的晶片加工方法包含倒角部除去步骤,在该倒角部除去步骤中,使切削刀具定位于由卡盘工作台保持的晶片的表面侧侧方,从层叠晶片的外周侧向中心切入,将从晶片的表面至预定厚度的倒角部除去,所以能够在晶片不破损的前提下比以往时间短且廉价地对晶片的背面进行磨削而将晶片薄化至预定厚度。
附图说明
图1是示出层叠晶片形成步骤的立体图。
图2是示出在第一实施方式中的倒角部除去步骤中使具有预定厚度以上的厚度的切削刀具定位于晶片的表面侧的侧方的状态下的侧视图。
图3是示出切削刀具从晶片的外周侧向中心切入状态的状态的倒角部除去步骤的侧视图。
图4是示出使用未达到预定厚度的切削刀具的本发明第二实施方式的倒角部除去步骤的侧视图。
图5是示出本发明第三实施方式的倒角部除去步骤的侧视图。
图6是示出倒角部除去步骤后的层叠晶片的侧视图。
图7是示出适合实施本发明的晶片加工方法的磨削装置的立体图。
图8是示出薄化步骤的侧视图。
标号说明
2:切削装置;
4:卡盘工作台;
6:切削单元;
10:主轴;
11:半导体晶片;
14:切削刀具;
22:磨削装置;
23:支承基板;
25:层叠晶片;
30:磨削单元;
44:磨削轮;
48:磨削磨具;
58:卡盘工作台。
具体实施方式
下面,对本发明的实施方式参照附图进行详细说明。参照图1,示出的是层叠晶片形成步骤的立体图。半导体晶片11例如由厚度为700μm的硅晶片构成,在表面11a呈格子状地形成有多条分割预定线(间隔道)13,并且,在由多条分割预定线13划分的各区域形成IC、LSI等器件15。
如此构成的半导体晶片11在表面的平坦部具有形成有器件15的器件区域17和围绕器件区域17的外周剩余区域19。而且,在半导体晶片11的外周形成有作为用于标示硅晶片的结晶方位的标记的缺口21。
根据本发明的晶片加工方法,作为第1步骤实施层叠晶片形成步骤,在该层叠晶片形成步骤中,如图1所示在晶片11的表面11a贴附作为保护部件的支承基板23以形成如图2所示的层叠晶片25。
支承基板23可以采用例如硅晶片、玻璃基板等。由于在薄化步骤实施后要将支承基板23从晶片11剥离,因此,作为粘接剂优选使用例如经过热水浸泡粘力降低的热水湿润型粘接剂。
在所述层叠晶片形成步骤中,不限于使用粘接剂进行贴附,也可以是,将晶片直接接合于支承基板上而形成SOI(Silicon On Insulator,硅绝缘体)晶片。
在层叠晶片25形成后,如图2所示,实施保持步骤,在该保持步骤中,以切削装置2的卡盘工作台4对层叠晶片25的支承基板23侧进行吸附保持。在晶片11的外周形成从表面11a到背面11b的圆弧状的倒角部12。
标号6是切削装置2的切削单元,切削刀具14被固定在主轴10的末端部,所述主轴10以能够旋转的方式收纳于主轴箱8中。以使主轴10的轴心(旋转轴线)10a与层叠晶片25的层叠方向平行的方式配置切削单元6,在本实施方式中,切削单元6与卡盘工作台4的旋转轴线4a平行。
在实施由切削装置2的卡盘工作台4对层叠晶片25的支承基板23侧吸附保持的保持步骤后,将切削刀具14定位于晶片11的表面11a侧的侧方,并且将切削刀具14定位于预定的高度位置以从晶片11的表面11a除去预定的厚度t1。此时,卡盘工作台4可以如图2所示处于旋转状态,也可以处于停止状态。
然后,实施倒角部除去步骤。具体来说,如图3所示,在使切削刀具14高速(如30000rpm)旋转的同时,使卡盘工作台4与切削单元6在水平方向相对移动预定距离,从而使切削刀具14从晶片11的外周侧向中心切入。
接着,通过使卡盘工作台4至少旋转1周,将从晶片11的表面11a至预定厚度t1的倒角部12除去。图6示出了在实施倒角部除去步骤后在晶片11的外周形成了圆形切削槽29的状态下的侧视图。
在图2和图3所示的实施方式中,切削刀具14具有预定的厚度t1。因而在使切削刀具14从晶片11的外周向中心切入且卡盘工作台4至少旋转1周时,在晶片11的外周部形成从表面11a至预定厚度t1的圆形切削槽29。
参照图4,示出了本发明第二实施方式中的倒角部除去步骤的侧视图。在本实施方式的倒角部除去步骤中,使用未达到预定厚度t1的切削刀具14A。
在该情况下,实施一次倒角部除去步骤,在晶片11的外周形成未达到预定厚度t1的圆形切削槽27之后,再实施多次同样的倒角部除去步骤,如图6所示,形成达到预定厚度t1的圆形切削槽29。
参照图5,示出了表示倒角部除去步骤的第三实施方式的切削装置2A的主要部分侧视图。在本实施方式的倒角部除去步骤中,以具有水平的旋转轴线4a的卡盘工作台4A对层叠晶片25的支承基板23侧进行吸附保持。从而以层叠方向处于水平方向的方式保持层叠晶片25。
切削单元6A是在具有水平方向的旋转轴线10a的主轴10的末端装有切削刀具14的一般的切削单元。在本实施方式的倒角部除去步骤中,将切削刀具14定位于晶片11的表面11a侧的外周的预定位置,使切削刀具14与卡盘工作台4A在铅直方向相对移动预定距离,从而使切削刀具14从晶片11的外周侧向中心切入,在切入状态下使卡盘工作台4A至少旋转1周,从而将从晶片11的表面11a至预定厚度t1的倒角部12除去。
由于切削刀具14具有预定的厚度t1,因此通过在切削刀具14切入晶片11的外周侧的状态下使卡盘工作台4A至少旋转1周,从而如图6所示,形成相对于晶片11的表面11a具有预定宽度t1的圆形切削槽29。
在倒角部除去步骤实施后,实施薄化步骤,在该薄化步骤中,使用如图7所示的磨削装置22,对层叠晶片25的晶片11的背面侧进行磨削,将晶片11薄化至预定厚度。在图7所示的磨削装置22的基座24的后方竖立设置有柱26。在柱26固定有一对在上下方向延伸的导轨28。
磨削单元30包括:主轴38,其以能够旋转的方式装在主轴箱32中;马达40,其用于驱动主轴38旋转;轮架42,其固定在主轴38的末端;以及磨削轮44,其以能够装卸的方式安装在轮架42。
磨削装置22具备由滚珠丝杠50和脉冲马达52构成的磨削单元进给机构54,所述磨削单元进给机构54用于使磨削单元30沿一对导轨28在上下方向移动。通过脉冲马达52驱动滚珠丝杆50旋转而使移动基台36沿上下方向移动。
在基座24的上表面形成有凹部24a,在所述凹部24a配设有卡盘工作台机构56。卡盘工作台机构56具有卡盘工作台58,并且通过未图示的移动机构在晶片装卸位置A和与磨削单元30相对的磨削位置B之间沿Y轴方向移动。标号60、62是波纹部。在基座24的前方侧配设有供磨削装置22的操作人员输入磨削条件等的操作面板64。
在对晶片11的背面11b侧进行磨削而使晶片11薄化至预定厚度的薄化步骤中,如图8所示,由磨削装置22的卡盘工作台58对层叠晶片25的支承基板23侧进行吸附保持,使晶片11的背面11b露出。
在图8中,在固定于磨削单元30的主轴38的末端的轮架42由未图示的多个螺钉以能够装卸的方式装有磨削轮44。磨削轮44通过在轮基座46的自由端部(下端部)呈环状地配设多个磨削磨具48而构成。
在薄化步骤中,一边使卡盘工作台58沿箭头a所示的方向以例如300rpm旋转,一边使磨削轮44沿箭头b所示的方向以例如6000rpm旋转,并且,驱动磨削单元进给机构54以使磨削轮44的磨削磨具48与晶片11的背面11b接触。然后,磨削轮44以预定的磨削进给速度向下方磨削进给预定量。
在通过接触式或非接触式的厚度测定器测定晶片11的厚度的同时将晶片11磨削至预期厚度t1。在将晶片11磨削至预期厚度t1后,通过磨削将倒角部12完全除去。因此不会随着晶片薄化而形成尖刃,从而能够防止晶片破损。
Claims (2)
1.一种晶片加工方法,所述晶片加工方法为将在外周具有倒角部的晶片薄化至预定厚度的晶片加工方法,其特征在于,
所述晶片加工方法具备:
层叠晶片形成步骤,在该层叠晶片形成步骤中,将晶片的表面贴附于支承基板上以形成层叠晶片;
倒角部除去步骤,在该倒角部除去步骤中,将切削刀具定位于所述晶片的表面侧的外周侧面,并从在所述层叠晶片形成步骤形成的层叠晶片的外周侧向中心切入,将从所述晶片的表面至所述预定厚度的倒角部除去,所述切削刀具具有与所述层叠晶片的层叠方向平行的旋转轴线;以及
薄化步骤,在该薄化步骤中,在所述倒角部除去步骤实施后,对所述层叠晶片的所述晶片的背面侧进行磨削以将晶片薄化至预定厚度。
2.根据权利要求1所述的晶片加工方法,其中,
所述晶片加工方法还具备保持步骤,在该保持步骤中,在所述倒角部除去步骤实施前,以切削装置的卡盘工作台对所述层叠晶片的靠所述支承基板的那一侧进行保持,
在所述倒角部除去步骤中,将具有与所述卡盘工作台的旋转轴线平行的旋转轴线的切削刀具定位于所述晶片的表面侧的外周侧面,并从所述层叠晶片的外周侧向中心切入,使所述卡盘工作台至少旋转1周,从而将从所述晶片的表面至所述预定厚度的倒角部除去。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011244321A JP5946260B2 (ja) | 2011-11-08 | 2011-11-08 | ウエーハの加工方法 |
JP2011-244321 | 2011-11-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103084950A true CN103084950A (zh) | 2013-05-08 |
CN103084950B CN103084950B (zh) | 2016-08-17 |
Family
ID=48129145
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201210433482.0A Active CN103084950B (zh) | 2011-11-08 | 2012-11-02 | 晶片加工方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9437439B2 (zh) |
JP (1) | JP5946260B2 (zh) |
CN (1) | CN103084950B (zh) |
DE (1) | DE102012220161B4 (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104733300A (zh) * | 2013-12-23 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | 一种键合晶片的减薄方法 |
KR20150131964A (ko) * | 2014-05-16 | 2015-11-25 | 가부시기가이샤 디스코 | 웨이퍼 가공 방법 및 중간 부재 |
CN110712306A (zh) * | 2015-04-15 | 2020-01-21 | 株式会社迪思科 | 晶片的生成方法 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6100002B2 (ja) * | 2013-02-01 | 2017-03-22 | 株式会社荏原製作所 | 基板裏面の研磨方法および基板処理装置 |
CN103280423A (zh) * | 2013-05-29 | 2013-09-04 | 华进半导体封装先导技术研发中心有限公司 | 一种机械式拆键合工艺及*** |
CN103367221A (zh) * | 2013-07-23 | 2013-10-23 | 华进半导体封装先导技术研发中心有限公司 | 一种晶圆拆键合工艺及*** |
JP6223873B2 (ja) * | 2014-03-14 | 2017-11-01 | 株式会社荏原製作所 | 研磨装置及び研磨方法 |
JP6313251B2 (ja) | 2015-03-12 | 2018-04-18 | 東芝メモリ株式会社 | 半導体装置の製造方法 |
JP7130323B2 (ja) * | 2018-05-14 | 2022-09-05 | 株式会社ディスコ | ウェーハの加工方法 |
US11538711B2 (en) | 2018-07-23 | 2022-12-27 | Micron Technology, Inc. | Methods for edge trimming of semiconductor wafers and related apparatus |
JP7258489B2 (ja) * | 2018-08-21 | 2023-04-17 | 株式会社岡本工作機械製作所 | 半導体装置の製造方法及び製造装置 |
JP7216613B2 (ja) * | 2019-05-16 | 2023-02-01 | 株式会社ディスコ | 加工装置 |
JP2022139255A (ja) * | 2021-03-11 | 2022-09-26 | 株式会社岡本工作機械製作所 | 半導体装置の製造方法及び製造装置 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN87107167A (zh) * | 1986-10-22 | 1988-05-04 | Bbc勃朗·勃威力有限公司 | 在半导体功率元件的半导体薄片边缘上开环形槽的方法 |
JPH03183130A (ja) * | 1989-12-12 | 1991-08-09 | Sony Corp | 半導体基板の製造方法 |
CN100555599C (zh) * | 2003-10-14 | 2009-10-28 | 特拉希特技术公司 | 制备和组装基材的方法 |
US20100156241A1 (en) * | 2008-12-24 | 2010-06-24 | Ngk Insulators, Ltd. | Method for manufacturing composite substrate and composite substrate |
CN101853864A (zh) * | 2009-03-31 | 2010-10-06 | 台湾积体电路制造股份有限公司 | 晶片键合方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3742593A (en) * | 1970-12-11 | 1973-07-03 | Gen Electric | Semiconductor device with positively beveled junctions and process for its manufacture |
US4261781A (en) * | 1979-01-31 | 1981-04-14 | International Business Machines Corporation | Process for forming compound semiconductor bodies |
US6113721A (en) * | 1995-01-03 | 2000-09-05 | Motorola, Inc. | Method of bonding a semiconductor wafer |
JP3352896B2 (ja) | 1997-01-17 | 2002-12-03 | 信越半導体株式会社 | 貼り合わせ基板の作製方法 |
JPH10337645A (ja) * | 1997-04-08 | 1998-12-22 | Olympus Optical Co Ltd | 研削方法およびその研削方法により加工されたガラスレンズ |
JP2000158334A (ja) | 1998-11-30 | 2000-06-13 | Disco Abrasive Syst Ltd | 作業用トレー及び研削方法 |
JP3515917B2 (ja) | 1998-12-01 | 2004-04-05 | シャープ株式会社 | 半導体装置の製造方法 |
FR2823373B1 (fr) * | 2001-04-10 | 2005-02-04 | Soitec Silicon On Insulator | Dispositif de coupe de couche d'un substrat, et procede associe |
DE10255058A1 (de) * | 2002-11-25 | 2004-06-17 | Loh Optikmaschinen Ag | Verfahren und Vorrichtung zur Randbearbeitung einer optischen Linse aus Kunststoff sowie Kombinationswerkzeug dafür |
US7129172B2 (en) * | 2004-03-29 | 2006-10-31 | Intel Corporation | Bonded wafer processing method |
FR2880184B1 (fr) * | 2004-12-28 | 2007-03-30 | Commissariat Energie Atomique | Procede de detourage d'une structure obtenue par assemblage de deux plaques |
JP4918229B2 (ja) * | 2005-05-31 | 2012-04-18 | 信越半導体株式会社 | 貼り合わせウエーハの製造方法 |
FR2935536B1 (fr) * | 2008-09-02 | 2010-09-24 | Soitec Silicon On Insulator | Procede de detourage progressif |
US8551881B2 (en) * | 2011-04-25 | 2013-10-08 | Nanya Technology Corporation | Method of bevel trimming three dimensional semiconductor device |
-
2011
- 2011-11-08 JP JP2011244321A patent/JP5946260B2/ja active Active
-
2012
- 2012-11-01 US US13/666,365 patent/US9437439B2/en active Active
- 2012-11-02 CN CN201210433482.0A patent/CN103084950B/zh active Active
- 2012-11-06 DE DE102012220161.0A patent/DE102012220161B4/de active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN87107167A (zh) * | 1986-10-22 | 1988-05-04 | Bbc勃朗·勃威力有限公司 | 在半导体功率元件的半导体薄片边缘上开环形槽的方法 |
JPH03183130A (ja) * | 1989-12-12 | 1991-08-09 | Sony Corp | 半導体基板の製造方法 |
CN100555599C (zh) * | 2003-10-14 | 2009-10-28 | 特拉希特技术公司 | 制备和组装基材的方法 |
US20100156241A1 (en) * | 2008-12-24 | 2010-06-24 | Ngk Insulators, Ltd. | Method for manufacturing composite substrate and composite substrate |
CN101853864A (zh) * | 2009-03-31 | 2010-10-06 | 台湾积体电路制造股份有限公司 | 晶片键合方法 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104733300A (zh) * | 2013-12-23 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | 一种键合晶片的减薄方法 |
CN104733300B (zh) * | 2013-12-23 | 2018-09-25 | 中芯国际集成电路制造(上海)有限公司 | 一种键合晶片的减薄方法 |
KR20150131964A (ko) * | 2014-05-16 | 2015-11-25 | 가부시기가이샤 디스코 | 웨이퍼 가공 방법 및 중간 부재 |
KR102455708B1 (ko) | 2014-05-16 | 2022-10-17 | 가부시기가이샤 디스코 | 웨이퍼 가공 방법 및 중간 부재 |
CN110712306A (zh) * | 2015-04-15 | 2020-01-21 | 株式会社迪思科 | 晶片的生成方法 |
CN110712306B (zh) * | 2015-04-15 | 2021-12-07 | 株式会社迪思科 | 晶片的生成方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2013102026A (ja) | 2013-05-23 |
DE102012220161A1 (de) | 2013-05-08 |
US9437439B2 (en) | 2016-09-06 |
JP5946260B2 (ja) | 2016-07-06 |
DE102012220161B4 (de) | 2024-03-07 |
CN103084950B (zh) | 2016-08-17 |
US20130115861A1 (en) | 2013-05-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103084950A (zh) | 晶片加工方法 | |
KR102163441B1 (ko) | 웨이퍼의 가공 방법 | |
CN101941248B (zh) | 切削装置 | |
JP5500942B2 (ja) | ウエーハの加工方法 | |
US9768049B2 (en) | Support plate and method for forming support plate | |
KR102154719B1 (ko) | 판형물의 가공 방법 | |
KR102028765B1 (ko) | 원형 판형상물의 분할 방법 | |
CN101131921A (zh) | 晶片的加工方法 | |
CN101402178A (zh) | 晶片的磨削加工装置 | |
KR20150007944A (ko) | 웨이퍼의 가공 방법 | |
JP2009246098A (ja) | ウエーハの研削方法 | |
JP5657302B2 (ja) | 切削方法 | |
CN101807542A (zh) | 晶片的加工方法 | |
KR20010030338A (ko) | 절삭방법 | |
KR20140133451A (ko) | 웨이퍼 절삭 방법 | |
CN102456600A (zh) | 晶片搬送机构 | |
CN101811273A (zh) | 工件加工方法和工件加工装置 | |
CN102103986A (zh) | 晶片的加工方法 | |
CN109904119B (zh) | 一种芯片的制备方法 | |
JP5881504B2 (ja) | ウエーハの加工方法 | |
JP2013012595A (ja) | ウエーハの加工方法 | |
JP2005109155A (ja) | 半導体ウェーハの加工方法 | |
JP2012146889A (ja) | ウエーハの研削方法 | |
CN109285771A (zh) | 晶片的加工方法 | |
CN109216270A (zh) | 晶片的加工方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |