CN103077933A - 三维的芯片到晶圆级集成 - Google Patents

三维的芯片到晶圆级集成 Download PDF

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Publication number
CN103077933A
CN103077933A CN2012104174253A CN201210417425A CN103077933A CN 103077933 A CN103077933 A CN 103077933A CN 2012104174253 A CN2012104174253 A CN 2012104174253A CN 201210417425 A CN201210417425 A CN 201210417425A CN 103077933 A CN103077933 A CN 103077933A
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Prior art keywords
crystal grain
semiconductor base
conductive pole
wafer
secondary mold
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CN2012104174253A
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CN103077933B (zh
Inventor
A·S·科尔卡
K·坦比杜赖
V·汉德卡尔
H·D·阮
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Maxim Integrated Products Inc
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Maxim Integrated Products Inc
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Abstract

公开了一种三维的芯片到晶圆级集成，集成电路器件包括半导体基底和附接到该半导体基底的晶粒。导电柱被连接到半导体基底或晶粒中的至少一个。二次塑模被模制到半导体基底上位于晶粒上方，并且导电柱延伸通过二次塑模。

Description

三维的芯片到晶圆级集成
背景技术
三维集成电路（3D IC）能够用两个或更多层的集成到单个IC芯片中的电子元件构成。电子元件可堆叠以形成单个电路。在有些情况下，垂直穿透性硅通孔（TSV）连接被用以连接到3D IC的电子元件。但是，当两个或更多个晶粒（die）堆叠在彼此之上时，TSV连接的使用可能要求重新设计被堆叠在另一晶粒之下的每个晶粒，以利用TSV连接到下晶粒。在其它的情况中，穿透性模塑焊剂连接，诸如穿透性模塑通孔（TMV）连接，使用焊球来提供在印刷电路板（PCB）和模制复合物的顶侧之间的互连。然而，该类型的构造限制了如由焊球的尺寸和间距要求所确定的在到PCB的连接之间的最小可能的间距。
发明内容
公开了一种集成电路器件，其包括半导体基底和附接到该半导体基底的晶粒。二次塑模（overmold）被模制到半导体基底上在晶粒上方。导电柱被连接到半导体基底或晶粒中的至少一个并且延伸通过二次塑模。在实施方式中，半导体基底可包括第二晶粒。导电柱可形成在晶粒和/或第二晶粒上。二次塑模可用以将第一晶粒模制到第二晶粒上，从而导电柱延伸通过二次塑模。在其它实施方式中，半导体基底可包括载体。二次塑模可用以将晶粒模制到载体上，从而导电柱延伸通过二次塑模。
该发明内容被提供用以通过简化的形式介绍构思的选择，该构思的选择在下面的详细说明中将进一步描述。该发明内容并不意图识别所要求保护的主题的关键特征或基本特征，也并不意图用作辅助确定所要求保护的主题的范围。
附图说明
参照附图描述具体实施方式。在具体实施方式和附图中的不同实例中使用的相同的标号可指代相似或相同的对象。
图1A是图示了根据本公开的示例实施方式的集成电路器件的示意性局部横截面侧面图，该集成电路器件包括被嵌入到二次塑模（多模）中的晶粒，该二次塑模模制到半导体晶圆上在该晶粒上方，其中该晶粒以面向下的取向布置。
图1B是图示了根据本公开的示例实施方式的集成电路器件的示意性局部横截面侧面图，该集成电路器件包括被嵌入到二次塑模中的晶粒，该二次塑模模制到半导体晶圆上在该晶粒上方，其中该晶粒以面向上的取向布置。
图1C是图示了根据本公开的示例实施方式的集成电路器件的示意性局部横截面侧面图，该集成电路器件包括被嵌入到二次塑模中的晶粒，该二次塑模模制到牺牲晶圆上在该晶粒上方，其中该晶粒以面向上的取向布置。
图2是图示了根据本公开的示例实施方式的集成电路器件的示意性局部横截面侧面图，该集成电路器件包括被嵌入到二次塑模中的第一晶粒，该二次塑模模制到半导体晶圆上在第一晶粒上方，其中第一晶粒以面向下的取向布置，并且该集成电路器件进一步包括嵌入到被模制在半导体晶圆上的二次塑模中的第二晶粒，其中该第二晶粒以面向上的取向布置。
图3是图示了根据本公开的示例实施方式的集成电路器件的示意性横截面侧面图，该集成电路器件包括被嵌入到二次塑模中的第一晶粒，该二次塑模被模制在半导体晶圆上在第一晶粒上方，其中第一晶粒以面向下的取向布置，并且该集成电路器件进一步包括嵌入在被模制在半导体晶圆上的二次塑模中的第二晶粒，其中该第二晶粒以面向上的取向布置。
图4是图示了根据本公开的示例实施方式的集成电路器件的示意性横截面侧面图，该集成电路器件包括被嵌入到二次塑模中的第一晶粒，该二次塑模被模制在半导体晶圆上在第一晶粒上方，其中第一晶粒以面向上的取向布置，并且该集成电路器件进一步包括嵌入在被模制到半导体晶圆上的二次塑模中的第二晶粒，其中该第二晶粒以面向上的取向布置。
图5是图示了根据本公开的示例实施方式的集成电路器件的示意性横截面侧面图，该集成电路器件包括被嵌入到二次塑模中的第一晶粒，该二次塑模模制在半导体晶圆上在第一晶粒上方，其中第一晶粒以面向下的取向布置，并且该集成电路器件进一步包括第二晶粒，该第二晶粒嵌入到二次塑模中并且被以面向上的取向模制在第一晶粒的晶粒附接垫上。
图6是图示了根据本公开的示例实施方式的集成电路器件的示意性局部横截面侧面图，该集成电路器件包括被嵌入到二次塑模中的晶粒，该二次塑模被模制到半导体晶圆上在该晶粒上方，其中该晶粒以面向下的取向布置，并且其中该集成电路器件包括外部散热器。
图7是图示了形成3D半导体芯片封装的方法的流程图，该3D半导体芯片封装包括与导电柱相连的一个或更多个晶粒，其中所述芯片封装通过利用二次塑模将晶粒模制到半导体基底而形成。
具体实施方式
概述
3D IC能够利用两个或更多层的集成到单个IC芯片中的电子元件构成。电子元件可以堆叠以形成单个电路。在有些情况下，垂直TSV用来连接到3D IC的电子元件。然而，当两个或更多个晶粒堆叠在彼此之上时，这可能需要重新设计堆叠在另一晶粒之下的每个晶粒，以通过TSV连接到下晶粒。在其它情况中，穿透性模塑焊剂连接，诸如TMV，使用焊球以在PCB和模制复合物的顶侧之间互连。然而，该类型的构造限制了如由焊球的尺寸和间距要求所确定的到PCB的连接之间的最小可能间距。
其它的类型的3D IC能够利用在其上布置有两个或更多个晶粒的模制环氧树脂晶圆来构成。然而，因为半导体晶粒，诸如硅片，具有与晶圆的环氧树脂材料不同的热膨胀系数（CTE），则用以将晶粒二次模塑到晶圆的模制复合物的厚度可能需要是显著的以防止最终形成的IC芯片的变形（warp）。另外，当重构模制的晶圆时，该类型构造的最终封装封脚（packagefootprint）/形状因子将通常大于最大的晶粒。
因此，三维（3D）半导体芯片封装被描述为使用由导电材料形成的柱以连接到嵌入在二次塑模中的晶粒。在实施方式中，导电柱允许到晶粒的连接布置不同于晶粒的布置（例如，成扇形展开），而不要求对晶粒再设计/再布局，并且还可以允许到晶粒的连接之间的微细节距。另外，晶粒能够附接到工作硅晶圆，使得最终形成的芯片封装的封脚/形状因子与从晶圆切割时的底层晶粒的相同。半导体芯片封装能够通过利用二次塑模将硅片固定到硅基底来形成，所述硅基底诸如是硅晶圆。通过由同类型的基底材料形成晶粒和基底，在制造时可以降低半导体芯片封装的变形。延伸通过二次塑模的导电柱能够连接到晶粒和/或基底。到晶粒和/或基底的连接也可用TSV连接和/或TMV连接来提供。
在有些情况下，基底可包括连接到一个或多个晶粒的电路。在其它的情况下，基底可以是牺牲（伪）载体，诸如硅载体晶圆（例如，用于实现扇出（fan-out，输出端）类型构造）。在一些构造中，晶粒可以以面向下的取向附接到基底。在其它的构造中，晶粒可以以面向下的取向附接到基底。导电柱可提供到晶粒和/或基底的电连接（例如，用于将电信号传送到晶粒或基底或从晶粒或基底传送电信号）。导电柱此外可用于半导体芯片封装的热管理。例如，导电柱可以热连接到散热器、散热垫等，用于从晶粒和/或晶圆传送热。3D芯片封装能被用于可能需要三维异构晶粒一体化的器件，诸如电源***级芯片（SoC）器件、手持装置、移动式电话装置和/或便携式电子装置。
包括与导电柱相连的一个或更多个晶粒的3D半导体芯片封装可在晶圆级封装（WLP）处理中通过将一个或更多个晶粒安置在半导体基底上、在该一个或更多个晶粒和/或半导体基底上形成导电柱并且利用二次塑模将该一个或更多个晶粒模制在半导体基底上而形成。二次塑模的表面可以被平面化（例如，依赖于模制处理）。半导体基底可包括牺牲载体，将牺牲载体可以经由背面研磨（back grinding）等而变薄以减小芯片封装的厚度。例如，在实施方式中，第一晶粒可以放置在第二晶粒上。导电柱可以形成在第一晶粒和/或第二晶粒上。二次塑模可用以将第一晶粒模制在第二晶粒上，使得导电柱延伸通过二次塑模。在其它的实施方式中，晶粒可以放置在载体上。导电柱可以形成在晶粒上。二次塑模可用以将晶粒模制在载体上，使得导电柱延伸通过二次塑模。
如这里使用的，术语“半导体基底”是指诸如但不局限于以下材料构造成的基底：硅，二氧化硅，氧化铝，蓝宝石，锗，砷化镓（GaAs），硅和锗的合金，和/或磷化铟（InP）。另外，处于本公开的目的，半导体基底能够形成为半导体或电绝缘体，并且包括半导体和绝缘材料两个的层。例如，在实施方式中，半导体基底能够利用诸如二氧化硅的绝缘体形成，绝缘体层上形成有诸如硅的半导体材料层。电子元件，诸如晶体管和二极管，能够制造在半导体中。在其它的实施方式中，半导体基底能够形成为绝缘体、电介质等。
示例实施方式
图1至6图示根据本公开的示例实施方式的包括与导电柱相连的一个或更多个晶粒的3D半导体芯片封装。如所示的，半导体芯片封装能够利用芯片到晶圆（C2W）堆叠通过将小的硅片（silicon die）利用二次塑模模制到大的硅基底上而形成。现在参考图1A至6，描述包括芯片封装100的半导体器件。芯片封装100包括模利用二次塑模，诸如模制复合物106，模制在半导体基底（诸如晶圆104）上的一个或更多个晶粒102。晶粒102的示例包括但不必然局限于：半导体晶粒（例如，硅片）、微机电***（MEMS）晶粒和无源晶粒（例如，无源玻璃晶粒）。到晶粒102和/或晶圆104的连接利用由导电材料（例如，铜、金等）形成的柱108提供，柱108延伸穿过模制复合物106。例如，柱108能够电和/或热连接到设有晶粒102和/或晶圆104的集成电路。在一些实施方式中，柱108能够连接到晶粒102以提供3D封装的有效热管理。到晶粒102和/或晶圆104的连接也可利用TSV连接和/或TMV连接提供。
在实施方式中，一个或多个晶粒102和晶圆104可以由同种基底材料形成以减少变形。例如，晶粒102和晶圆104可以利用硅基底形成。在实施方式中，每个晶粒102能够是大约一百微米（100μm厚），而模制复合物106能够是大约三百微米（300μm）厚，晶圆104能够是大约七百微米（700μm）厚。应该注意，这些厚度仅被提供为示例，并不意图限制本公开。由此，芯片封装100可包括具有其它不同厚度的晶粒102、晶圆104和/或模制复合物106。在有些情况（例如，如图1A和1B中所示）下，晶圆104可包括可与一个或多个晶粒102相连的电路，诸如晶体管等。例如，晶圆104可以被分割为单独的半导体晶粒。在其它的情况（例如，如图1C中所示）中，晶圆104可以是牺牲（伪）载体，诸如硅载体晶圆，其中载体晶圆中的部分或全部能够在晶粒102被已经模制到晶圆104之后被去除。
在一些实施方式中，（例如，如图1A中所示），晶粒102能够附接到晶圆104使得顶部晶粒处于面向下定向（即，到顶部晶粒的连接面向“下”，即朝向晶圆104）。在其它的实施方式中，（例如，如图1B和1C中所示），晶粒102能够附接到晶圆104使得顶部晶粒处于面向上定向（即，到顶部晶粒的连接面向“上”，即背离晶圆104）。在面向上的该类型的实施方式中，晶粒102能够利用晶粒附接垫110（例如，如图1B中所示）连接到晶圆104。另外，在面向上的实施方式中，到晶粒102的连接能够布置或重新布置成扇出（例如，以提供在连接之间的更大间距，如图1C中所示）。这可以随着晶粒通过增强的小型化变得更小而特别有用。例如，具有三毫米乘三毫米（3mm×3mm）的覆盖区封脚但要求在连接之间的十分之五毫米（0.5mm）节距的晶粒可能在晶粒上存在多个连接焊盘时需要扇出以实现期望的节距。
利用该芯片封装100能够包括多于一个的晶粒102。例如，两个晶粒102能够以并排构造来提供（例如，如图1A至4中所示）。另外，在一些构造中，以面向上定向布置的晶粒102能够以并排构造与以面向下定向布置的晶粒（例如，如图2和3中所示）一起被包括在同一芯片封装100中。在有些情况下，一个或更多个晶粒102可以连接到包括在晶圆104上的电路，而一个或更多个其它的晶粒102可将晶圆104用作伪晶圆（例如，如图3和4中所示）。另外，两个或更多个晶粒102能够堆叠在彼此之上，并且连接到晶圆104（例如，如图5所示）。
在一种构造中，晶粒102和晶圆104能够是异构的。例如，晶粒102能够是数字或无源元件，并且晶圆104能够包括模拟元件等，诸如模拟***级芯片（SoC）等。然而，该构造仅作为示例提供，并不意图限制本公开。由此，其它的构造能够使用异构和同构的构造中的数字和/或模拟元件的其它布置。例如，晶粒102能够是模拟元件，并且晶圆104能够包括数字元件。在有些情况下，柱108可用于芯片封装100的热管理。例如，柱108能够热连接到散热器（例如，外部散热器112，如图6中所示）、热垫等，用于从晶粒102和/或晶圆104传送热。例如，参考图6，焊球118被连接到柱108，柱108被连接到晶圆104，晶圆104被连接到散热器112。以此，提供了从晶粒102到晶圆104的用于散热的连续通路。
示例制造过程
以下讨论描述了用于制造如下3D半导体芯片封装的示例技术：该3D半导体芯片封装包括一个或更多个与导电柱相连的晶粒，其中芯片封装在晶圆级封装（WLP）处理中通过利用二次塑模将晶粒模制在半导体基底上而形成。图7描述了用于制造半导体器件的处理700的示例实施方式，所述半导体器件诸如是图1A至6图示的以及上述的示例芯片封装100。在图示的处理700中，导电柱形成在晶粒和/或半导体基底上（块710）。例如，参考图1A至6，柱108，诸如包括铜或另一导电材料的小节距柱，被形成在晶粒102和/或晶圆104上。在一些实施方式中，柱108能够利用干膜照相处理形成并且可以为约五十微米（50μm）宽和约一百五十微米厚（150μm），具有三比一（3:1）的纵横比。在其它的实施方式中，柱108的高度能够是约两百微米（200μm）（例如，利用厚干膜照相处理来形成柱108）。干膜照相处理可包括将诸如铜的导电材料的种子层形成在晶粒102和/或晶圆104上。然后，干膜可以层叠在所述种子层上。接着，负性光致抗蚀剂处理可用以将柱108的形状曝光到干膜中并将孔创建到种子层。然后，通过将导电材料沉积在干膜中的孔中，柱108可从下到上被电镀。干膜照相处理仅作为示例提供，并不意图限制本公开。由此，柱108可利用其它的制造技术、导电材料等形成。在实施方式中，在晶粒102和/或晶圆104在相连的晶圆上时，柱108可以形成在晶粒102和/或晶圆104上。例如，柱108可以形成在包括晶粒102的晶圆上，该晶圆然后可以被减薄且切块（分割）。
一个或更多个晶粒然后被放置在半导体基底上，诸如晶圆上（块710）。例如，继续参考图1A至6，拾取和放置工具可用以将晶粒102放置在晶圆104上。在一些实施方式中，晶粒102能够利用环氧胶附接到晶圆。在一些实施方式中，晶粒102能够以面向下的取向被放置在晶圆104上。在该类型的构造中，晶粒102能够利用焊球114等连接到晶圆104。在其它的实施方式中，晶粒102能够以面向上取向放置在晶圆104上。在该类型的构造中，晶粒102能够利用晶粒附接垫110等连接到晶圆104。应该注意到，在该类型的构造中，焊球、铜柱等可以形成在晶圆104上并且用以在晶圆104上将晶粒102对准。在有些情况下，晶粒102能够在将晶粒102模制到晶圆104上之前（例如，利用背面研磨工具）被减薄。
二次塑模然后被模制到半导体基底上在晶粒上方（块730）。例如，继续参考图1A至6，晶粒102能够通过将模制复合物106模制到晶圆104上在晶粒102上方而被嵌入在模制复合物106中。模制复合物106可包括液体或粉末材料，诸如环氧树脂材料、基于树脂的材料和/或热塑性弹性体材料。例如，在具体情况中，环氧树脂构架能够与球形环氧树脂填充金属一起使用。模制复合物106可以基于包括但不限于如下特征的特性来选择：热膨胀系数（CTE）、挠曲模量和/或颗粒大小。例如，模制复合物106可以被选择以提供用于柱108之间的渗透的所需的填充能力。另外，模制复合物106可以构造成在晶粒102和晶圆104之间渗透（例如，以与二次塑模材料相比具有高的填料含量和小的颗粒大小的底层填料的方式）。例如，当晶粒102和晶圆104之间的间距在约四十微米和六十微米（40μm--60μm）之间时，毛细管作用可用以将模制复合物106吸到在晶粒102和晶圆104之间的空间中。
在一些实施方式中，转移模塑处理能够被用于模制复合物106。在实施方式中，液态模制复合物106可用以形成二次塑模。在其它的实施方式中，压模处理能够被用于模制复合物106。例如，粒状的模制复合物106被放入压模空腔，压力被施加到模制复合物106，然后维持热和压力直到模制材料已经固化。应该注意到，模制复合物106的厚度可选择成防止或最小化压力对柱108的影响。例如，当使用压模处理时，模制复合物106的厚度能够选择成大于柱108的高度。然而，在其它的实施方式中，模制复合物106的厚度可以等于或小于柱108的高度。在一些实施方式中，平面化可用以使二次塑模的表面平坦（块732）。例如，当模制复合物106利用转移模塑处理被模制时，平面磨削可用于使模制复合物106变平并暴露柱108。
一个或更多个再分布层（RDL）然后可形成在二次塑模上（块740）。例如，继续参考图1A至6，再分布层116能够施加在模制复合物106上。应该注意，除再分布层116之外，其它材料也可以沉积在模制复合物106上。例如，氧化铅和/或低温聚酰亚胺可用以提供凸起下金属喷镀（UBM）。另外地，应当注意，许多RDL可以形成在模制复合物106上。另外，在一些构造中，芯片封装100不一定包括RDL（例如，当晶粒以面向下的取向被放置在半导体基底上时）。然后，一个或更多个焊剂凸起可以形成在再分布层上(块750)。例如，继续参考图1A至图6，外部焊剂凸起118被施加到再分布层116。在有些情况下，半导体基底可以被减薄以减小芯片封装的总厚度（块760）。例如，晶圆104能够利用背面研磨等被减薄。接着，半导体基底可以被切割以提供单独的集成电路器件（块770）。例如，继续参考图1A至图6，晶圆104能够被切割以提供单个的芯片封装100。在一些实施方式中，散热器能够连接到芯片封装100的硅表面。例如，继续参考图6，散热器112能够连接到晶圆104的底面（晶粒102的相反侧）。
结论
虽然已经针对结构特征和/或处理操作在语言上描述了本主题，但是应该理解，在所附权利要求书中限定的主题并不局限于上述的具体特征或作用。相反地，上述的具体特征和作用被公开为实施权利要求的示例形式。

Claims (20)

1.一种半导体器件，包括：
半导体基底；
晶粒，所述晶粒附接到所述半导体基底；
二次塑模，所述二次塑模被模制到所述半导体基底上位于所述晶粒上方；和
导电柱，所述导电柱连接到所述半导体基底或所述晶粒中的至少一个，所述导电柱延伸通过所述二次塑模。
2.根据权利要求1所述的半导体器件，其特征在于，所述半导体基底和所述晶粒具有至少大致相同的热膨胀系数。
3.根据权利要求1所述的半导体器件，其特征在于，所述半导体基底包括载体，及到所述晶粒扇出的连接。
4.根据权利要求1所述的半导体器件，其特征在于，所述半导体基底包括第二晶粒。
5.根据权利要求4所述的半导体器件，其特征在于，所述晶粒包括模拟元件或数字元件中的一个，并且所述第二晶粒包括模拟元件或数字元件中的另一个。
6.根据权利要求1所述的半导体器件，其特征在于，进一步包括：
再分布层，所述再分布层形成在所述二次塑模上；和
多个焊剂凸起，所述多个焊剂凸起形成在所述再分布层上，所述多个焊剂凸起中的至少一个经由所述再分布层连接到所述导电柱。
7.根据权利要求1所述的半导体器件，其特征在于，所述晶粒以面向上的取向附接到所述半导体基底。
8.根据权利要求1所述的半导体器件，其特征在于，所述晶粒以面向下的取向附接到所述半导体基底。
9.根据权利要求1所述的半导体器件，其特征在于，所述导电柱提供到所述半导体基底或所述晶粒中的所述至少一个的电连接。
10.根据权利要求1所述的半导体器件，其特征在于，所述导电柱构造成从所述半导体基底或所述晶粒中的至少一个传送热。
11.根据权利要求1所述的半导体器件，其特征在于，进一步包括散热器，所述散热器与所述半导体基底的与所述晶粒相反的一侧结合。
12.一种制造晶圆级封装的方法，包括：
将晶粒放置在半导体基底上；
将导电柱形成在所述半导体基底或所述晶粒中的至少一个上，所述导电柱连接到所述半导体基底或所述晶粒中的所述至少一个；以及
将二次塑模模制在所述半导体基底上位于所述晶粒上方，所述导电柱延伸通过所述二次塑模。
13.根据权利要求12所述的方法，其特征在于，进一步包括：
将再分布层形成在所述二次塑模上；并且
将多个焊剂凸起形成在所述再分布层上，所述多个焊剂凸起中的至少一个经由所述再分布层连接到所述导电柱。
14.根据权利要求12所述的方法，其特征在于，所述半导体基底和所述晶粒具有至少大致相同的热膨胀系数。
15.根据权利要求12所述的方法，其特征在于，将所述晶粒放置在半导体基底上包括将所述晶粒以面向上的取向放置在所述半导体基底上。
16.根据权利要求12所述的方法，其特征在于，将所述晶粒放置在半导体基底上包括将所述晶粒以面向下的取向放置在所述半导体基底上。
17.根据权利要求12所述的方法，其特征在于，所述导电柱提供到所述半导体基底或所述晶粒中的所述至少一个的电连接。
18.根据权利要求12所述的方法，其特征在于，所述导电柱构造成从所述半导体基底或所述晶粒中的至少一个传送热。
19.一种半导体器件，包括：
第一晶粒；
第二晶粒，所述第二晶粒附接到所述第一晶粒；
二次塑模，所述二次塑模被模制到所述第一晶粒上位于所述第二晶粒上方；和
导电柱，所述导电柱连接到所述第一晶粒或所述第二晶粒中的至少一个，所述导电柱延伸通过所述二次塑模。
20.根据权利要求19所述的晶圆级封装，其特征在于，所述第一晶粒和所述第二晶粒具有至少大致相同的热膨胀系数。
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