CN103064807B - Hyperchannel DMA controller - Google Patents
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- CN103064807B CN103064807B CN201210550249.0A CN201210550249A CN103064807B CN 103064807 B CN103064807 B CN 103064807B CN 201210550249 A CN201210550249 A CN 201210550249A CN 103064807 B CN103064807 B CN 103064807B
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Abstract
The invention discloses a kind of multi-channel DMA controller, several DMA passage and data transmission units are set in dma controller, the control operation transmit data and data carrying work are separated, the control operation transmitted by several DMA passage process DMA data, each DMA passage carries out BD bookkeeping and generates transfer instruction operation, the data carrying work transmitted by the number DMA data that reportedly defeated cell processing is whole, data transmission unit is arbitrated the transfer instruction from several DMA passages, according to arbitrating the clooating sequence obtained, perform each transfer instruction successively, data are transmitted between CPU internal memory and peripheral hardware buffer memory, the line production of the control operation of data transmission can be formed in DMA passage, the line production of the data carrying operation of data transmission is formed in data transmission unit, the data rate of dma controller can be improved, be applicable to the application scenarios of high speed data transfer.
Description
Technical field
The present invention relates to data communication field, particularly, relate to a kind of hyperchannel DMA controller.
Background technology
Direct memory access (DMA) (DMA, Direct Memory Access) be a kind of data transfer operation of high speed, allow direct read/write data between external unit and storer, whole data transfer operation carries out under the control of dma controller, central processing unit (CPU is not needed in transmitting procedure, Central ProcessUnit) intervention, CPU can carry out other work, thus drastically increases the operational efficiency of CPU.
Fig. 1 a is the structured flowchart of typical DMA system in prior art.In CPU, dma controller, sheet, external storage (comprising Flash, Flash controller, chip external memory, Memory Controller in ram in slice, RAM controller, sheet) and High Speed I/O are connected on high-speed bus, various low-speed peripheral (comprising low-speed peripheral 1, low-speed peripheral 2, low-speed peripheral 3) is connected on low speed bus, and is connected with high-speed bus by bus bridge.If the equipment in bus will carry out DMA transmission, then initiate request to dma controller, dma controller, after the acquisition bus right to use, controls to carry out data transmission at CPU internal memory and miscellaneous equipment, and after end of transmission (EOT), gives back the bus right to use.Participate in without the need to CPU in DMA transmitting procedure, save the overhead of CPU.
Chinese patent (application number: 200910080751, publication number: 101504633) disclose a kind of multi-channel DMA controller, this dma controller comprises multiple DMA channel module and a multiplexing module, each DMA channel module comprises a data buffer-stored and control module thereof and one group of control register respectively, and the data buffering of all passages stores and control module is all connected to a multiplexing module.This dma controller can reduce the expense of bus arbitration block and storage unit in SOC (system on a chip) to a certain extent, and improves the reusability of system.
But; in the technical scheme of this Chinese patent; each DMA passage all performs Data Control and data transmission work; particularly; DMA passage reads request of data to the data genaration that need read; and after sending reading request of data to CPU internal memory; must wait until CPU internal memory return ask read data; just can carry out the next operation generating reading request of data; but; usually can there is time delay in CPU internal memory return data, this problem just causing data rate slow, causes this dma controller to be not suitable for the application scenarios of high speed data transfer.
Summary of the invention
In view of this, embodiments provide a kind of multi-channel DMA controller, slow in order to the transmission speed solving dma controller of the prior art, to be not suitable for high speed data transfer application scene problem.
Embodiment of the present invention technical scheme is as follows:
A kind of dma controller, comprising: several DMA passage and data transmission units; Described DMA passage, after according with (BD, Buffer Descriptor) updating message, reads BD for the cashing indication received from central processor CPU from CPU internal memory, according to the data storage condition in BD and peripheral hardware buffer memory, generates transfer instruction; Described data transmission unit, for arbitrating from the transfer instruction of DMA passage described in several, according to arbitrating the clooating sequence obtained, performing each transfer instruction successively, between described CPU internal memory and described peripheral hardware buffer memory, transmitting data.
The embodiment of the present invention by arranging several DMA passage and data transmission units in dma controller, the data carrying work of the control operation transmit data and data transmission is separated, also the control operation namely transmitted by several DMA passage process DMA data, particularly, each DMA passage carries out BD bookkeeping and generates transfer instruction operation, the data carrying work transmitted by the number DMA data that reportedly defeated cell processing is whole, particularly, data transmission unit is arbitrated the transfer instruction from several DMA passages, according to arbitrating the clooating sequence obtained, perform each transfer instruction successively, data are transmitted between CPU internal memory and peripheral hardware buffer memory, visible, the data control operation that data transmission unit performs need not depend on the data carrying operation that data transmission unit performs, the line production of the control operation of data transmission can be formed in DMA channel side, data transmission unit processes the transfer instruction from several DMA passages successively, the line production of the data carrying operation of data transmission is formed in data transmission unit side, and then the data rate of dma controller can be improved, the application scenarios of high speed data transfer can be applicable to.
Other features and advantages of the present invention will be set forth in the following description, and, partly become apparent from instructions, or understand by implementing the present invention.Object of the present invention and other advantages realize by structure specifically noted in write instructions, claims and accompanying drawing and obtain.
Accompanying drawing explanation
Fig. 1 a is the structured flowchart of typical DMA system in prior art;
Fig. 1 b is the structured flowchart of the multi-channel DMA controller that the embodiment of the present invention provides;
Fig. 1 c is the workflow diagram of multi-channel DMA controller shown in Fig. 1 b;
Fig. 2 is the preferred structure block diagram of the multi-channel DMA controller shown in Fig. 1 b;
Fig. 3 is the preferred structure block diagram of the multi-channel DMA controller shown in Fig. 2;
Fig. 4 is the workflow diagram of the downlink command generation module in Fig. 3;
Fig. 5 is the work for the treatment of process flow diagram of the read data module in Fig. 3 to downlink data;
Fig. 6 is the workflow diagram of the descending write-back module in Fig. 3;
Fig. 7 is another preferred structure block diagram of the multi-channel DMA controller shown in Fig. 2;
Fig. 8 is the workflow diagram of the up-on command generation module in Fig. 7;
Fig. 9 writes the work for the treatment of process flow diagram of data module to upstream data in Fig. 7;
Figure 10 is the workflow diagram of the up write-back module in Fig. 7.
Embodiment
Below in conjunction with accompanying drawing, embodiments of the invention are described, should be appreciated that embodiment described herein is only for instruction and explanation of the present invention, is not intended to limit the present invention.
The problem that the embodiment of the present invention is slow for dma controller data rate of the prior art, be not suitable for the application scenarios of high speed data transfer, proposes a kind of multi-channel DMA controller, to solve this problem.The control operation that DMA data are transmitted by the embodiment of the present invention and data carrying work are separated, several DMA passage and data transmission units are set in dma controller, the control operation of DMA passage process DMA data transmission, namely generate and be used to indicate the transfer instruction how carrying out data carrying, the data carrying work transmitted by data transmission unit process DMA data, namely concrete data carrying operation is carried out according to transfer instruction, the control operation of DMA passage does not rely on the data carrying work of data transmission unit, can in the line production of DMA channel side formation control operation, data transmission unit processes the transfer instruction from several DMA passages successively, the line production of data carrying operation is formed in data transmission unit side, and then the data rate of dma controller can be improved, the application scenarios of high speed data transfer can be applicable to.
The following detailed description of the multi-channel DMA controller that the embodiment of the present invention provides.
Fig. 1 b shows the structured flowchart of the multi-channel DMA controller that the embodiment of the present invention provides, and this multi-channel DMA controller comprises several DMA passages 11 and data transmission unit 12.
DMA passage 11, after receiving the BD updating message from CPU, reads BD from CPU internal memory, according to the data storage condition in BD and peripheral hardware buffer memory, generates transfer instruction;
Data transmission unit 12, is connected to DMA passage 11, for arbitrating the transfer instruction from several DMA passages, according to arbitrating the clooating sequence obtained, performing each transfer instruction successively, between CPU internal memory and peripheral hardware buffer memory, transmitting data.
The workflow diagram of multi-channel DMA controller shown in Fig. 1 c, as illustrated in figure 1 c, comprising:
After step 101, several DMA passages 11 receive the BD updating message from CPU respectively, from CPU internal memory, read BD, and respectively according to the data storage condition in the BD read and peripheral hardware buffer memory, generate transfer instruction;
Step 102, data transmission unit 12 receive the transfer instruction from each DMA passage 11, arbitrate, obtain the clooating sequence to transfer instruction to several transfer instructions received;
Step 103, data transmission unit 12, according to arbitrating the clooating sequence obtained, perform each transfer instruction successively, between CPU internal memory and peripheral hardware buffer memory, transmit data.
By the principle of work shown in multi-channel DMA controller as shown in Figure 1 b and Fig. 1 c, the data carrying work of control operation DMA data can transmitted and data transmission is separated, also the control operation namely transmitted by several DMA passage process data, the data carrying work transmitted by data transmission unit process DMA data, the control operation of DMA passage does not rely on the data carrying work of data transmission unit, and data transmission unit is arbitrated the transfer instruction from several DMA passages, according to arbitrating the clooating sequence obtained, perform the data carrying operation indicated by each transfer instruction successively, DMA passage carries out control operation next time after the data carrying of data transmission unit operation need not be waited to terminate again, can in the line production of DMA channel side formation control operation, and the line production of data carrying operation is formed in data transmission unit side, and then the data rate of dma controller can be improved, the application scenarios of high speed data transfer can be applicable to.
Before the principle of work of Fig. 1 b shown device is described in detail, first BD is described.
BD is a data structure for the control information of data of description read-write operation, several BD occupy a slice continuous print storage space in CPU internal memory, the structure of BD is as shown in table 1, comprises instruction (Eop) that whether instruction (Sop) that whether data address, data length, data slice are the start-up portion of packet, data slice are the latter end of packet, whether error message instruction (Err), control information instruction (Owner), BD effectively indicate (Valid).
Table 1
| Data address | Data length | SOP | EOP | Err | Owner | valid |
Before bus control right is given multi-channel DMA controller by CPU, understand in the data address territory and data length field that the address of data to be read and data length are write BD respectively, and Owner territory is rewritten as the information representing multi-channel DMA controller, then BD updating message is sent to multi-channel DMA controller, after multi-channel DMA controller receives BD updating message, BD is read from CPU internal memory, judge that bus control right belongs to self according to the information in Owner territory in BD, thus data can be read according to the data address territory in BD and the information in data length field from CPU internal memory.When multi-channel DMA controller writes data in CPU internal memory, according to the information in data address territory in BD, data are write in CPU internal memory, and by the data length field of the data length write BD stored in data, and Owner territory is rewritten as the information representing CPU, revised BD is sent to CPU internal memory, CPU by monitoring CPU internal memory newly stored in the information in Owner territory of BD, learn that bus control right comes back to CPU.
Particularly, DMA passage 11 for respectively to DMA data transmission the control operation of downlink data and the control operation of upstream data process, downlink data is read from CPU internal memory and be written to the data peripheral hardware buffer memory, upstream data is read from peripheral hardware buffer memory and be written to the data CPU internal memory, correspondingly, transfer instruction is also divided into reads instruction and write command, and data transmission unit 12 also correspondingly carries out data carrying operation according to reading instruction to downlink data, carries out data carrying operation according to write command to upstream data.
Fig. 2 shows the preferred structure block diagram of the multi-channel DMA controller shown in Fig. 1 b, specifically comprises down going channel 111 and data feedback channel 112 in DMA passage 11, and data transmission unit 12 comprises read data module 121 and writes data module 122.
Down going channel 111, after receiving the BD updating message from CPU, reads BD from CPU internal memory, according to the data volume size of the data accepted stored in the reading data length information in the BD read and peripheral hardware buffer memory, generates and reads instruction;
Read data module 121, be connected to the down going channel 111 of several DMA passages 11, for arbitrating the instruction of reading of the down going channel 111 from several DMA passages 11, according to arbitrating the clooating sequence obtained, read instruction according to each successively and read corresponding data from CPU internal memory, and the data of reading are sent to peripheral hardware buffer memory.
Data feedback channel 112, after receiving the BD updating message from CPU, reads BD from CPU internal memory, according to the address information of the data to be written in the data volume size of the data to be sent stored in peripheral hardware buffer memory and the BD of reading, generates write command;
Write data module 122, be connected to the data feedback channel 112 of several DMA passages 11, for arbitrating the write command of the data feedback channel 112 from several DMA passages, according to arbitrating the clooating sequence obtained, from peripheral hardware buffer memory, read corresponding data according to each write command successively, and the data of reading are sent to CPU internal memory.
By arranging data feedback channel and down going channel in DMA passage, and read data module is set in data transmission unit and writes data module, upstream data process and downlink data treatment region can be separated, and the control operation all data transmitted for downlink data and upstream data and data carrying operational zone separate, the line production of the control operation of upstream data and downlink data effectively can be formed respectively in DMA channel side, and the line production that the data carrying forming upstream data and downlink data in data transmission unit side respectively operates, and then the data rate of dma controller can be improved, the application scenarios of high speed data transfer can be applicable to.
And, owing to arranging corresponding functional unit respectively according to downlink data and upstream data in the embodiment of the present invention, the dma controller that the invention process is provided has good Scalability, namely according to the difference of application scenarios, when only needing dma controller process downlink data, only down going channel can be set in DMA passage, read data module is set in data transmission unit, when only needing dma controller process upstream data, only data feedback channel can be set in DMA passage, arrange in data transmission unit and write data module, when needs dma controller process downlink data and upstream data, dma controller as shown in Figure 2 can be set.
Describe the process of the multi-channel DMA controller shown in Fig. 2 to downlink data and upstream data respectively in detail below.
(1), downlink data process
Fig. 3 shows the preferred structure of multi-channel DMA controller shown in Fig. 2 block diagram, this multi-channel DMA controller comprises: down going channel 111 and read data module 121, and down going channel 111 comprises: descendingly read BD module 1111, downlink command generation module 1112 and descending write-back module 1113.
1, descendingly read BD module 1111, after receiving the BD updating message from CPU, from described CPU internal memory, read several BD, and preserve several BD read.
Particularly, after the descending BD of reading module 1111 receives the BD updating message from CPU, send the descending BD that reads to CPU internal memory to ask, the quantity of the BD that request is read is carried in the descending BD of reading request, wherein, the quantity of the BD that this request is read is: from the quantity of the readable BD indicated in the BD updating message of CPU, the quantity of the BD shown in current BD pointer to BD ring tail in BD ring, and the BD quantity of quantity reckling in this three of quantity of the reading BD preset, according to the difference of application scenarios, the quantity of the reading BD preset is also different, therefore, visible each quantity of asking the BD read is indefinite, it can be one, also can be many, and, receive from CPU internal memory for these descending several BD reading BD request, and preserve several BD received.
2, downlink command generation module 1112, for the data volume size according to the data accepted stored in the reading data length information in the BD of the descending BD of reading module 1111 reading and peripheral hardware buffer memory, generates and reads instruction;
Particularly, downlink command generation module 1112 performs following operation: read current BD operation, judge operation, command operating is read in generation and command operating is read in transmission; Wherein,
(1), read current BD operation to comprise: in current time sheet, when having idle storage space in downlink command generation module 1112, downlink command generation module 1112 obtains a BD as current BD from descending reading BD module 1111; When not having idle storage space in downlink command generation module 1112, downlink command generation module 1112 continues to wait for, until when having idle storage space, obtains a BD as current BD from descending reading BD module 1111;
(2), judge that operation comprises: judge whether contrast condition is set up, contrast condition for: contrast store in the data length shown in the reading data length information in current BD and downlink command generation module 1112 corresponding and generate the data length sum shown in the reading data length information read in each BD of instruction, whether be less than the size of the idle storage space in storage space corresponding with the down going channel of this DMA passage in peripheral hardware buffer memory, when judging that contrast condition is set up, perform generation and read command operating, otherwise, continue to wait for, until contrast condition is set up, namely wait for that the data in peripheral hardware buffer memory are read away, being discharged of storage space in peripheral hardware buffer memory, contrast condition is set up,
(3), generate and read command operating and comprise: generate and corresponding with current BD read instruction, reading the address information of carrying the reading data length information in current BD and the reading data in current BD in instruction; And, preserve current BD, preferably, fifo queue can be adopted preserve correspondence to generate the BD reading instruction;
(4) send and read command operating: the instruction of reading of current for the correspondence of generation BD is sent to read data module 121.
3, read data module 121, be connected to the downlink command generation module 1112 of each down going channel 111, for reading instruction for arbitrate in the clooating sequence that obtains current, read the address information in instruction according to current and read data length information, from CPU internal memory appropriate address storage space in read the data of corresponding length, and the data of reading are sent in storage space corresponding with sending the current DMA passage reading instruction in peripheral hardware buffer memory;
Particularly, the read instruction of read data module 121 to the down going channel 111 from several DMA passages 11 is arbitrated, such as arbitrate according to taking turns the principle of making (Round Robin) to dispatch, instruction is read for arbitrate in the clooating sequence that obtains current, read the address information in instruction according to current and read data length information, send read data request to CPU internal memory, read data request comprises currently to be read address information in instruction and reads data length information; Receive from the packet of CPU internal memory for read data request, and the data received are sent in storage space corresponding with sending the current DMA passage reading instruction in peripheral hardware buffer memory;
Further, be polled to current when reading instruction, read data module 121 is read to respond to sending current down going channel (i.e. the downlink command generation module 1112 of the down going channel 111) feedback reading the DMA passage of instruction; In sense data from CPU internal memory and after sending to peripheral hardware buffer memory, also feed back run through response to sending the current down going channel (i.e. the downlink command generation module 1112 of down going channel 111) reading the DMA passage of instruction;
Correspondingly, downlink command generation module 1112, also for: receive from read data module 121 read response after, preserve current BD; Receive from read data module 121 run through response after, from downlink command generation module 1112 preserve BD take out a BD send to descending write-back module 1113; Preferably, as mentioned above, downlink command generation module 1112 is preserved correspondence by fifo queue and is generated the BD reading instruction, herein, takes out a BD send to descending write-back module 1113 from team's head of fifo queue.
4, descending write-back module 1113, for: the control information in the BD received is rewritten as CPU, revised BD is sent to CPU internal memory.Particularly, descending write-back module 1113 preserves revised BD, when judging to store revised BD in descending write-back module 1113, carries out timing to predetermined write back cycle; Within time-count cycle, when the quantity of preserved revised BD is more than or equal to predetermined quantity, using the revised BD of predetermined quantity as BD to be sent, BD to be sent is sent to CPU internal memory, when the quantity of preserved revised BD is less than predetermined quantity, in timing then, using preserved revised BD as BD to be sent, BD to be sent is sent to CPU internal memory.
Fig. 4 shows the workflow diagram of the downlink command generation module 1112 in Fig. 3, and also namely Fig. 4 shows the principle of work that down going channel carries out the control operation of downlink data transmission, comprises following processing procedure:
Step 401, the descending BD of reading module 1111 are after receiving the BD updating message from CPU, several BD are read from CPU internal memory, particularly, the descending BD of reading module 1111 sends the descending BD that reads to CPU internal memory and asks, and carries the quantity of the BD that request is read in the descending BD of reading request; As mentioned above, the quantity of BD can be a BD or multiple BD; The descending BD of reading module 1111 receive from CPU internal memory for these descending several BD reading BD request, and preserve several BD of receiving; The descending BD of reading module 1111 batch reads BD, can reduce the bus bandwidth taken, improve treatment effeciency;
Step 402, downlink command generation module 1112, in current time sheet, when having idle storage space in downlink command generation module 1112, obtain a BD as current BD from descending reading BD module 1111; Particularly, in current time sheet, downlink command generation module 1112 judges to store BD in the descending BD of reading module 1111, and in downlink command generation module 1112 when available free storage space, obtains a BD as current BD from descending reading BD module 1111;
Step 403, downlink command generation module 1112, according to the data volume size of the data accepted stored in the reading data length information in current BD and peripheral hardware buffer memory, generate and read instruction;
Particularly, when judging that contrast condition is set up, what store in the data length shown in reading data length information namely in current BD and downlink command generation module 1112 correspondingly generates the data length sum shown in reading data length information read in each BD of instruction, when being less than the size of the idle storage space in storage space corresponding with the down going channel of this DMA passage in peripheral hardware buffer memory, generate and corresponding with current BD read instruction, reading the address information of carrying the reading data length information in current BD and the reading data in current BD in instruction, process proceeds to step 404,
Under judging the invalid situation of contrast condition, what store in the data length shown in reading data length information in current BD and downlink command generation module 1112 correspondingly generates the data length sum shown in reading data length information read in each BD of instruction, when being more than or equal to the size of the idle storage space in storage space corresponding with the down going channel of this DMA passage in described peripheral hardware buffer memory, process turns back to step 403, until contrast condition is set up;
In contrast condition, need to judge: what store in the data length shown in reading data length information in current BD and downlink command generation module 1112 correspondingly generates the data length sum shown in reading data length information read in each BD of instruction, with the relativity of the size of the idle storage space in storage space corresponding with the down going channel of this DMA passage in peripheral hardware buffer memory, its reason is: described in following steps 405, read data module 121 be polled to one read instruction after, read response can to transmission downlink command generation module 1112 feedback that this reads instruction, read data module 121 does not now read data from CPU internal memory, because read data module 121 waiting for CPU internal memory return data needs certain hour, so, after read data module 121 reads response to descending directive generation module 1112 transmission, in downlink command generation module 1112, read to respond the corresponding data read indicated by instruction really do not read with this, now, downlink command generation module 1112 should be preserved and read to respond corresponding BD with this, namely preserve correspondence and generate the BD reading instruction, so, when instruction is read in downlink command generation module 1112 generation, judge whether the length of data to be handled is less than the size of the idle storage space in storage space corresponding with the down going channel of this DMA passage in peripheral hardware buffer memory, and the length of data to be handled just comprises reading data length in current BD and the corresponding reading data length sum read in each BD of instruction that generates,
The instruction of reading of current for the correspondence of generation BD is sent to read data module 121 by step 404, downlink command generation module 1112, carries out data carrying operation to make read data module 121 according to reading instruction;
Step 405; Downlink command generation module 1112 receive from read data module 121 read response after, preserve current BD, preferably, the buffer queue preserving BD can be fifo queue, wherein read to respond be read data module 121 to be polled to that downlink command generation module 1112 sends read instruction time, read data module 121 is fed back to descending directive generation module 1112; The processing returns to step 403.
Fig. 5 shows the work for the treatment of process flow diagram of read data module 121 pairs of downlink datas in Fig. 3, and namely Fig. 5 shows the fundamental diagram that read data module 121 pairs of downlink datas carry out data carrying, comprises following treatment step:
The instruction of reading to the down going channel 111 from several DMA passages 11 of step 501, read data module 121 is arbitrated; Preferably, RR can be adopted to dispatch and arbitrate, specifically can carry out sequence obtain clooating sequence to reading instruction according to the clooating sequence of several DMA passages 11, also namely this clooating sequence is consistent with the clooating sequence of several DMA passages 11;
Step 502, read data module 121 read instruction for arbitrate in the clooating sequence that obtains current, read the address information in instruction according to current and read data length information, from CPU internal memory appropriate address storage space in read the data of corresponding length; Particularly, read data module 121 sends read data request to CPU internal memory, and read data request comprises currently to be read address information in instruction and reads data length information; And read response to sending current downlink command generation module 1112 feedback reading the down going channel of the DMA passage of instruction;
The data of reading are sent in storage space corresponding with sending the current DMA passage reading instruction in peripheral hardware buffer memory by step 503, read data module 121, particularly, read data module 121 receives the packet for read data request from CPU internal memory, and the data received is sent in storage space corresponding with sending the current DMA passage reading instruction in peripheral hardware buffer memory; The processing returns to step 501.
In above-mentioned processing procedure, the descending BD of reading module 1111 batch from CPU internal memory reads several BD and preserves the BD read, so that downlink command generation module 1112 takes out BD one by one and generates according to BD read instruction, carry out data carrying work to make read data module 121 according to reading instruction; And, what downlink command generation module 1112 fed back according to read data module 121 reads response, preserve to read to respond corresponding BD after, generate according to next BD and read instruction, whether the operation that instruction is read in the generation that downlink command generation module 1112 is performed does not rely on read data module 121 and data is read from CPU internal memory, can form the line production of the control operation to downlink data; And, the read instruction of read data module 121 to the down going channel from several DMA passages is arbitrated, according to arbitrating the clooating sequence obtained, reading instruction according to each successively and carrying out data carrying operation, the line production of the data carrying operation to downlink data can be formed; Thus the transmission speed of descending DMA data transmission can be improved, the application scenarios of high-speed down data transmission can be applicable to.
On the basis of the principle of work of above-mentioned downlink data transmission, for adopting in the application scenarios of BD ring, the transmission of DMA data also comprises the processing procedure of descending BD write-back.
Here first illustrate that the structure of BD ring and effect thereof are described.The end to end ring texture that BD ring is made up of several BD, the structure of each BD can be as shown in Table 1, BD ring occupies a slice continuous print storage space in CPU internal memory, after the descending BD of reading module 1111 have read several BD from CPU internal memory, downlink command generation module 1112 generates successively according to each BD and reads instruction, after read data module 121 reads data, descending DMA passage 111 should be rewritten BD, Owner territory in BD is rewritten as the information representing CPU, then revised BD is sent it back in CPU internal memory, with the change making CPU monitor bus control right.
Fig. 6 shows the workflow diagram of the descending write-back module 1113 in Fig. 3, and also namely Fig. 6 shows the principle of work of the BD write-back to downlink data, comprises following processing procedure:
Step 601, downlink command generation module 1112 receive and run through response from read data module 121, run through response be read data module 121 poll process downlink command generation module 1112 send read instruction, also i.e. sense data after sending to peripheral hardware buffer memory from CPU internal memory, feeds back to descending directive generation module 1112;
Step 602, downlink command generation module 1112 take out a BD and send to descending write-back module 1113 from the BD that downlink command generation module 1112 is preserved, preferably, from the queue of the first in first out of preservation BD, take out the BD coming team's head and send to descending write-back module 1113;
Control information in the BD received is rewritten as CPU by step 603, descending write-back module 1113, and revised BD is sent to CPU internal memory;
Particularly, descending write-back module 1113 sends revised BD according to chronograph mechanism; Control information in the BD received is rewritten as CPU by descending write-back module 1113, preserves revised BD; When descending write-back module 1113 judges to store revised BD in the storage space of self, timing is carried out to predetermined write back cycle; Within time-count cycle, after preserved rewriting, the quantity of BD is more than or equal to predetermined quantity, using the revised BD of predetermined quantity as BD to be sent, BD to be sent is sent to CPU internal memory, when the quantity of preserved revised BD is less than predetermined quantity, after timing then, using preserved revised BD as BD to be sent, BD to be sent is sent to CPU internal memory.
By above-mentioned processing procedure, descending write-back module 1113 can write-back BD in bulk, can reduce the number of times of write-back BD, reduce the bus bandwidth shared by write-back BD, thus improve the speed of DMA data transmission.And, introduce chronograph mechanism and send revised BD to CPU internal memory, can when the quantity of revised BD be more than or equal to predetermined quantity, in time the revised BD of predetermined quantity is sent to CPU internal memory, congested or the BD of BD is caused to lose when the quantity of the revised BD in down going channel 111 can be avoided to increase too much instantaneously, when the quantity of revised BD is less than predetermined quantity, after timing then, revised BD is sent to CPU internal memory, when avoiding the quantity of revised BD to be less than predetermined quantity for a long time, revised BD cannot be returned to CPU, CPU is caused to monitor the problem of the overlong time of the BD waiting for write-back, CPU can be made to monitor the situation of bus control right change in time.
(2) upstream data process
Fig. 7 shows the preferred structure of multi-channel DMA controller shown in Fig. 2 block diagram, this multi-channel DMA controller comprises: data feedback channel 112 and write data module 122, and data feedback channel 112 comprises: uply read BD module 1121, up-on command generation module 1122 and up write-back module 1123.
Uply read BD module 1121, for after receiving the BD updating message from CPU, from described CPU internal memory, read several BD, and preserve several BD read; Particularly, the up BD of reading module 1121 sends the up BD that reads to CPU internal memory and asks, and carries the quantity of the BD that request is read in the up BD of reading request; Receive from CPU internal memory for these up several BD reading BD request;
Up-on command generation module 1122, for the address information according to the data volume size of the data to be sent stored in peripheral hardware buffer memory and the up data to be written read in the BD that BD module 1121 reads, generates described write command; Particularly, in current time sheet, up-on command generation module 1122 obtains a BD as current BD from up reading BD module 1121, generate write command according to the data volume size of the data to be sent stored in peripheral hardware buffer memory, in the write command generated, carry the address information of data to be written in the CPU internal memory in the data length information of data to be sent in peripheral hardware buffer memory and current BD; Preserve current BD; The write command of generation is sent to and writes data module 122.
Write data module 122, for for the current write command arbitrated in the clooating sequence that obtains, according to the data length information in current write command, read the data of corresponding length during storage corresponding with the DMA passage sending current write command from peripheral hardware buffer memory controls, and the data of reading are sent in the respective stored space in the described CPU internal memory of the address information indication in current write command; Further, when being polled to current write command, the data feedback channel (i.e. the up-on command generation module 1122 of data feedback channel 112) to the DMA passage sending current write command feeds back write response; In sense data from peripheral hardware buffer memory and after being sent to CPU internal memory, also feeding back to the data feedback channel (i.e. the up-on command generation module 1122 of data feedback channel 112) of the DMA passage sending current write command and write into response;
Up-on command generation module 1123, also for: after receiving from the write response writing data module 122, preserve current BD; Receive from write data module 122 write into response after, from up-on command generation module 1122 preserve BD take out a BD send to up write-back module 1123;
Up write-back module 1123, for: the control information in the BD received is rewritten as CPU, the data length information in write command is written in BD, revised BD is sent to CPU internal memory; Particularly, up write-back module 1123 preserves revised BD, when judging to store revised BD in up write-back module 1123, carries out timing to predetermined write back cycle; Within time-count cycle, when the quantity of preserved revised BD is more than or equal to predetermined quantity, using the revised BD of predetermined quantity as BD to be sent, BD to be sent is sent to CPU internal memory, when the quantity of preserved revised BD is less than predetermined quantity, after timing then, using preserved revised BD as BD to be sent, BD to be sent is sent to CPU internal memory, sends to scheduling unit 13 by BD to be sent.
Fig. 8 shows the workflow diagram of up-on command generation module 1122 in Fig. 7, and also namely Fig. 8 shows the principle of work that data feedback channel carries out the control operation of transmitting uplink data, comprises following processing procedure:
After step 801, the up BD of reading module 1121 receive the BD updating message from CPU, from CPU internal memory, read several BD, and preserve several BD read; Particularly, the up BD of reading module 1121 sends the up BD that reads to CPU internal memory and asks, and carries the quantity of the BD that request is read in the up BD of reading request; As mentioned above, the quantity of BD can be one, also can be multiple; The up BD of reading module 1121 receive from CPU internal memory for these up several BD reading BD request, and preserve several BD of receiving;
Step 802, in current time sheet, when there is idle storage space in up-on command generation module 1122, up-on command generation module 1122 from up read BD module 1121 obtain a BD as current BD; Particularly, up-on command generation module 1122 judges to store BD in the up BD of reading module 1121, and in up-on command generation module 1122 when available free storage space, in current time sheet, obtain a BD BD module 1121 as current BD from up reading;
Step 803, up-on command generation module 1122 generate the write command corresponding with current BD, carry the address information of data to be written in the CPU internal memory in the data length information of data to be sent in peripheral hardware buffer memory and current BD in the write command of generation;
The write command of generation sends to and writes data module 122 by step 804, up-on command generation module 1122, carries out data carrying operation to make writing data module 122 according to write command;
Step 805, up-on command generation module 1122 are after receiving from the write response writing data module 122, preserve current BD, the buffer queue preserving BD is fifo queue, wherein write response writes data module 122 to when being polled to write command that up-on command generation module 1122 sends, writes that data module 122 feeds back to up directive generation module 1122; The processing returns to step 803.
Fig. 9 shows in Fig. 7 the work for the treatment of process flow diagram writing data module 122 pairs of upstream datas, and namely Fig. 9 shows and writes the fundamental diagram that data module 122 pairs of upstream datas carry out data carrying, comprises following treatment step:
Step 901, write the write command of data module 122 to the data feedback channel 112 from several DMA passages 11 and arbitrate, preferably, RR can being adopted to dispatch and arbitrate, obtaining the clooating sequence to reading instruction;
Step 902, write data module 122 for the current write command arbitrated in the clooating sequence that obtains, the up-on command generation module 1122 of data feedback channel to the DMA passage sending current write command sends write response;
Step 903, write data module 122 according to the data length information in current write command, the data of corresponding length are read in storage space corresponding with the DMA passage sending current write command from peripheral hardware buffer memory, the data of reading are sent to CPU internal memory, the processing returns to step 901.
In above-mentioned processing procedure, up BD module 1121 batch from CPU internal memory of reading reads BD and preserves the BD read, so that up-on command generation module 1122 takes out BD one by one and generates write command according to BD, data carrying work is carried out according to write command to make writing data module 122, up-on command generation module 1122 is according to the write response writing data module 122 feedback, after preserving the BD corresponding to write response, write command is generated according to next BD, whether the operation of the generation write command that the up BD of reading module 1121 is performed does not rely on writes data module 122 and writes in CPU internal memory by data, can to the line production formed the control operation of upstream data, and, write the write command of data module 122 to the data feedback channel from several DMA passages to arbitrate, according to arbitrating the clooating sequence obtained, carrying out data carrying operation according to each write command successively, the line production of the data carrying operation to upstream data can be formed, thus the transmission speed of up DMA data transmission can be improved, the application scenarios of high speed uplink data transmission can be applicable to.
On the basis of the handling principle of above-mentioned transmitting uplink data, for adopting in the application scenarios of BD ring, the transmission of DMA data also comprises the processing procedure of up BD write-back.
Figure 10 shows the workflow diagram of the up write-back module 1123 in Fig. 7, and also namely Figure 10 shows the principle of work of the BD write-back to upstream data, comprises following processing procedure:
Step 1001, up-on command generation module 1122 receive and write into response from what write data module 122, writing into response is write the write command that data module 122 poll processes up-on command generation module 1112 transmission, also i.e. sense data after sending to CPU internal memory from peripheral hardware buffer memory, feeds back to up directive generation module 1122;
Step 1002, up-on command generation module 1122 take out a BD and send to up write-back module 1123 from the BD that up-on command generation module 1122 is preserved, and also namely from the queue of the first in first out of preservation BD, take out the BD coming team's head and send to up write-back module 1123;
Control information in the BD received is rewritten as CPU by step 1003, up write-back module 1123, is written in BD, revised BD is sent to CPU internal memory by the data length information in write command; Particularly, the control information in the BD received is rewritten as CPU by up write-back module 1123, preserves revised BD; When up write-back module 1123 judges to store revised BD in the storage space of self, timing is carried out to predetermined write back cycle; Within time-count cycle, after preserved rewriting, the quantity of BD is more than or equal to predetermined quantity, using the revised BD of predetermined quantity as BD to be sent, BD to be sent is sent to CPU internal memory, when the quantity of preserved revised BD is less than predetermined quantity, after timing then, using preserved revised BD as BD to be sent, BD to be sent is sent to CPU internal memory.
By above-mentioned processing procedure, up write-back module 1123 can write-back BD in bulk, can reduce the number of times of write-back BD, reduce the bus bandwidth shared by write-back BD, thus improve the speed of DMA data transmission.Cause the congested or BD of BD to lose when the quantity of the revised BD in down going channel 111 can also be avoided to increase too much instantaneously, when avoiding the quantity of revised BD to be less than predetermined quantity for a long time, revised BD cannot be returned to CPU.
In sum, according to the technical scheme of the embodiment of the present invention, several DMA passage and data transmission units are set in dma controller, the data carrying work of the control operation transmit data and data transmission is separated, also the control operation namely transmitted by several DMA passage process DMA data, particularly, each DMA passage carries out BD bookkeeping and generates transfer instruction operation, the data carrying work transmitted by the number DMA data that reportedly defeated cell processing is whole, particularly, data transmission unit is arbitrated the transfer instruction from several DMA passages, according to arbitrating the clooating sequence obtained, perform each transfer instruction successively, data are transmitted between CPU internal memory and peripheral hardware buffer memory, visible, the data control operation that DMA passage performs need not depend on the data carrying operation that data transmission unit performs, the line production of the control operation of data transmission can be formed in DMA channel side, data transmission unit processes the transfer instruction from several DMA passages successively, the line production of the data carrying operation of data transmission is formed in data transmission unit side, and then the data rate of dma controller can be improved, the application scenarios of high speed data transfer can be applicable to.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (7)
1. a hyperchannel direct memory access (DMA) dma controller, is characterized in that, comprising: several DMA passage and data transmission units;
Described DMA passage, after receiving the cashing indication symbol BD updating message from central processor CPU, reads BD, according to the data storage condition in BD and peripheral hardware buffer memory, generates transfer instruction from CPU internal memory;
Described data transmission unit, for arbitrating from the transfer instruction of DMA passage described in several, according to arbitrating the clooating sequence obtained, performing each transfer instruction successively, between described CPU internal memory and described peripheral hardware buffer memory, transmitting data;
Described transfer instruction comprises: read instruction; Then,
Described DMA passage, specifically comprise: down going channel, described down going channel specifically comprises: descendingly read BD module and downlink command generation module, wherein, descendingly read BD module, for after receiving the BD updating message from CPU, from described CPU internal memory, read several BD, and preserve several BD read; Downlink command generation module, for the data volume size according to the data accepted stored in the reading data length information in the BD of the described descending BD of reading module reading and described peripheral hardware buffer memory, reads instruction described in generation;
Described data transmission unit, specifically comprise: read data module, for arbitrating the instruction of reading of the down going channel from DMA passage described in several, according to arbitrating the clooating sequence obtained, read instruction according to each successively and read corresponding data from described CPU internal memory, and the data of reading are sent to described peripheral hardware buffer memory;
Described downlink command generation module, specifically for: perform and read current BD operation, judge operation, command operating is read in generation and command operating is read in transmission; Wherein,
Read current BD to operate: in current time sheet, when there is idle storage space in described downlink command generation module, obtain a BD BD module as current BD from described descending reading;
Judge operation: judge whether contrast condition is set up, contrast condition for: contrast store in the data length shown in the reading data length information in current BD and described downlink command generation module corresponding and generate the data length sum shown in the reading data length information read in each BD of instruction, whether be less than the size of the idle storage space in storage space corresponding with the down going channel of this DMA passage in described peripheral hardware buffer memory, when judging that contrast condition is set up, perform generation and read command operating, otherwise, continue to wait for, until contrast condition is set up;
Command operating is read in generation: generate and corresponding with current BD read instruction, reading the address information of carrying the reading data length information in current BD and the reading data in current BD in instruction; And current BD is preserved in described downlink command generation module;
Command operating is read in transmission: the read instruction corresponding with current BD generated is sent to described read data module; And/or,
Described transfer instruction comprises: write command; Then,
Described DMA passage, specifically comprise: data feedback channel, described data feedback channel specifically comprises: uply read BD module and up-on command generation module, wherein, uply read BD module, for after receiving the BD updating message from CPU, from described CPU internal memory, read several BD, and preserve several BD read; Up-on command generation module, for the address information according to the data volume size of the data to be sent stored in described peripheral hardware buffer memory and the described up data to be written read in the BD that BD module reads, generates described write command;
Described data transmission unit, specifically comprise: write data module, for arbitrating from the write command of the data feedback channel of DMA passage described in several, according to arbitrating the clooating sequence obtained, from described peripheral hardware buffer memory, read corresponding data according to each write command successively, and the data of reading are sent to described CPU internal memory;
Described up-on command generation module, specifically for:
In current time sheet, when there is idle storage space in described up-on command generation module, obtain a BD BD module as current BD from described up reading;
Generate the write command corresponding with current BD, in the write command generated, carry the address information of data to be written in the CPU internal memory in the data length information of data to be sent in described peripheral hardware buffer memory and current BD;
Current BD is preserved in described up-on command generation module;
The write command of generation is sent to write data module.
2. multi-channel DMA controller according to claim 1, is characterized in that, described read data module, specifically for:
Instruction is read for arbitrate in the clooating sequence that obtains current, read the address information in instruction according to current and read data length information, from described CPU internal memory appropriate address storage space in read the data of corresponding length, and the data of reading to be sent in storage space corresponding with sending the current DMA passage reading instruction in described peripheral hardware buffer memory.
3. multi-channel DMA controller according to claim 1, it is characterized in that, described read data module, also for: read instruction for arbitrate in the clooating sequence that obtains current, being polled to current when reading instruction, reading response to sending the current down going channel feedback reading the DMA passage of instruction; In sense data from described CPU internal memory and after sending to described peripheral hardware buffer memory, also run through response to sending the current down going channel feedback reading the DMA passage of instruction; Then,
Described down going channel, also comprises: descending write-back module; Wherein,
Described downlink command generation module, also for: receive from described read data module read response after, in described downlink command generation module, preserve current BD; Receive from described read data module run through response after, from the BD that described downlink command generation module is preserved, take out a BD send to described descending write-back module;
Described descending write-back module, for: the control information in the BD received is rewritten as CPU, revised BD is sent to described CPU internal memory.
4. multi-channel DMA controller according to claim 3, is characterized in that, described descending write-back module, specifically for:
Preserving revised BD, when judging to store revised BD in described descending write-back module, timing being carried out to predetermined write back cycle; Within time-count cycle, after preserved rewriting, the quantity of BD is more than or equal to predetermined quantity, using the revised BD of predetermined quantity as BD to be sent, BD to be sent is sent to described CPU internal memory, when the quantity of preserved revised BD is less than predetermined quantity, after timing then, using preserved revised BD as BD to be sent, BD to be sent is sent to described CPU internal memory.
5. multi-channel DMA controller according to claim 1, is characterized in that, write data module, specifically for:
For the current write command in the clooating sequence that arbitration obtains, according to the data length information in current write command, read the data of corresponding length during storage corresponding with the DMA passage sending current write command from described peripheral hardware buffer memory controls, and the data of reading are sent in the respective stored space in the described CPU internal memory of the address information indication in current write command.
6. multi-channel DMA controller according to claim 5, is characterized in that, write data module, also for: when being polled to current write command, to send current write command DMA passage data feedback channel feedback write response; In sense data from described peripheral hardware buffer memory and after being sent to described CPU internal memory, the data feedback channel feedback also to the DMA passage sending current write command writes into response; Then,
Described data feedback channel, also comprises: up write-back module; Wherein,
Described up-on command generation module, also for: after receiving the write response from write data module, preserve current BD at described up-on command generation module; Receive from write data module write into response after, from the BD that described up-on command generation module is preserved, take out a BD send to described up write-back module;
Described up write-back module, for: the control information in the BD received is rewritten as CPU, the data length information in described write command is written in BD, revised BD is sent to described CPU internal memory.
7. multi-channel DMA controller according to claim 6, is characterized in that, described up write-back module, specifically for:
Preserve revised BD; When judging to store revised BD in described up write-back module, timing is carried out to predetermined write back cycle; Within time-count cycle, after preserved rewriting, the quantity of BD is more than or equal to predetermined quantity, using the revised BD of predetermined quantity as BD to be sent, BD to be sent is sent to described CPU internal memory, when the quantity of preserved revised BD is less than predetermined quantity, after timing then, using preserved revised BD as BD to be sent, BD to be sent is sent to described CPU internal memory.
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| CN105988953B (en) * | 2015-02-12 | 2019-03-12 | 深圳市中兴微电子技术有限公司 | A kind of direct memory access dma controller and the method for data transmission |
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