CN103064807A - Multi-channel direct memory access controller - Google Patents
Multi-channel direct memory access controller Download PDFInfo
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Abstract
The invention discloses a multi-channel direct memory access (DMA) controller. A plurality of DMA channels and a data transmission unit are arranged in the DMA controller, the control operation and the data transportation work of data transmission are separated, the control operation of DMA data transmission is processed by the plurality of DMA channels, each DMA channel performs buffer descriptor (BD) management operation and operation for generating a transmission instruction, one data transmission unit is used for processing total data transportation work of DMA data transmission, the data transmission unit performs arbitration on transmission instructions from the plurality of DMA channels, each transmission instruction is sequentially executed according to a ranking sequence obtained by the arbitration, data are transmitted between a central processing unit (CPU) internal memory and an external cache, a flow process of the control operation of the data transmission can be formed in the DMA channels, a flow process of the data transportation work of data transmission is formed in the data transmission unit, the data transmission speed of the DMA controller can be increased, and the DMA controller is suitable for an application scene of high speed data transmission.
Description
Technical field
The present invention relates to data communication field, particularly, relate to the direct memory access controller of a kind of hyperchannel.
Background technology
Direct memory access (DMA) (DMA, Direct Memory Access) be a kind of data transfer operation of high speed, allow externally direct read/write data between the equipment and storer, whole data transfer operation carries out under the control of dma controller, in transmission course, do not need central processing unit (CPU, Central ProcessUnit) intervention, CPU can carry out other work, thereby has greatly improved the operational efficiency of CPU.
Fig. 1 a is the structured flowchart of typical DMA system in the prior art.External storage in CPU, dma controller, the sheet (comprising Flash, Flash controller, chip external memory, Memory Controller in ram in slice, RAM controller, the sheet) and High Speed I/O are connected on the high-speed bus, various low speed peripheral hardwares (comprising low speed peripheral hardware 1, low speed peripheral hardware 2, low speed peripheral hardware 3) are connected on the low speed bus, and link to each other with high-speed bus by bus bridge.Equipment on the bus is then initiated request to dma controller if carry out DMA transmission, and dma controller is controlled at CPU internal memory and miscellaneous equipment and carries out data transmission, and give back the bus right to use after end of transmission (EOT) after obtaining the bus right to use.Need not CPU in the DMA transmission course and participate in, save the overhead of CPU.
Chinese patent (application number: 200910080751, publication number: 101504633) disclose a kind of multi-channel DMA controller, this dma controller comprises a plurality of DMA channel modules and a multiplexing module, each DMA channel module comprises respectively a data buffer-stored and control module and one group of control register, and data buffering storage and the control module thereof of all passages all are connected to a multiplexing module.This dma controller can reduce the expense of bus arbitration piece and storage unit on the SOC (system on a chip) to a certain extent, and improves the reusability of system.
But; in the technical scheme of this Chinese patent; the equal executing data control of each DMA passage and data transmission work; particularly; the DMA passage generates the reading out data request to the data that need read; and after the request of CPU internal memory transmission reading out data; must wait until the CPU internal memory return ask the data that read; just can carry out the next operation that generates the reading out data request; but; can there be time delay in CPU internal memory return data usually, and this just causes the slow problem of data rate, causes this dma controller to be not suitable for the application scenarios of high speed data transfer.
Summary of the invention
In view of this, the embodiment of the invention provides a kind of multi-channel DMA controller, slow in order to the transmission speed that solves dma controller of the prior art, as to be not suitable for high speed data transfer application scene problem.
Embodiment of the invention technical scheme is as follows:
A kind of dma controller comprises: several DMA passage and data transmission units; Described DMA passage after buffer memory identifier (BD, the Buffer Descriptor) updating message that receives from central processor CPU, reads BD from the CPU internal memory, according to the data storage condition in BD and the peripheral hardware buffer memory, generate transfer instruction; Described data transmission unit is used for arbitrating from the transfer instruction of several described DMA passages, according to the clooating sequence that arbitration obtains, carries out successively each transfer instruction, the transmission of data between described CPU internal memory and described peripheral hardware buffer memory.
The embodiment of the invention is by arranging several DMA passage and data transmission units in dma controller, the control operation of data transmission and the data carrying work of data transmission are separated, also namely processed the control operation of DMA data transmission by several DMA passages, particularly, each DMA passage carries out the BD bookkeeping and generates the transfer instruction operation, data carrying work by the whole DMA data transmission of data transmission cell processing, particularly, data transmission unit is to arbitrating from the transfer instruction of several DMA passages, the clooating sequence that obtains according to arbitration, carry out successively each transfer instruction, the transmission of data between CPU internal memory and peripheral hardware buffer memory, as seen, the data control operation that data transmission unit is carried out needn't depend on the data carrying operation that data transmission unit is carried out, can form in the DMA channel side line production of the control operation of data transmission, data transmission unit is successively to processing from the transfer instruction of several DMA passages, form the line production of the data carrying operation of data transmission in the data transmission unit side, and then can improve the data rate of dma controller, can be applicable to the application scenarios of high speed data transfer.
Other features and advantages of the present invention will be set forth in the following description, and, partly from instructions, become apparent, perhaps understand by implementing the present invention.Purpose of the present invention and other advantages can realize and obtain by specifically noted structure in the instructions of writing, claims and accompanying drawing.
Description of drawings
Fig. 1 a is the structured flowchart of typical DMA system in the prior art;
Fig. 1 b is the structured flowchart of the multi-channel DMA controller that provides of the embodiment of the invention;
Fig. 1 c is the workflow diagram of multi-channel DMA controller shown in Fig. 1 b;
Fig. 2 is the preferred structure block diagram of the multi-channel DMA controller shown in Fig. 1 b;
Fig. 3 is the preferred structure block diagram of multi-channel DMA controller shown in Figure 2;
Fig. 4 is the workflow diagram of the downlink command generation module among Fig. 3;
Fig. 5 is that read data module among Fig. 3 is to the work for the treatment of process flow diagram of downlink data;
Fig. 6 is the workflow diagram of the descending write-back module among Fig. 3;
Fig. 7 is another preferred structure block diagram of multi-channel DMA controller shown in Figure 2;
Fig. 8 is the workflow diagram of the up-on command generation module among Fig. 7;
Fig. 9 writes data module to the work for the treatment of process flow diagram of upstream data among Fig. 7;
Figure 10 is the workflow diagram of the up write-back module among Fig. 7.
Embodiment
Below in conjunction with accompanying drawing embodiments of the invention are described, should be appreciated that embodiment described herein only is used for description and interpretation the present invention, is not intended to limit the present invention.
The problem that the embodiment of the invention is slow for dma controller data rate of the prior art, be not suitable for the application scenarios of high speed data transfer proposes a kind of multi-channel DMA controller, to address this problem.The embodiment of the invention is separated control operation and the data carrying work of DMA data transmission, several DMA passage and data transmission units are set in dma controller, the DMA passage is processed the control operation of DMA data transmission, namely generate and be used to indicate the transfer instruction that how to carry out the data carrying, processed the data carrying work of DMA data transmission by data transmission unit, namely carry out concrete data carrying operation according to transfer instruction, the control operation of DMA passage does not rely on the data carrying work of data transmission unit, can be in the line production of DMA channel side formation control operation, data transmission unit is successively to processing from the transfer instruction of several DMA passages, form the line production of data carrying operation in the data transmission unit side, and then can improve the data rate of dma controller, can be applicable to the application scenarios of high speed data transfer.
The below describes the multi-channel DMA controller that the embodiment of the invention provides in detail.
Fig. 1 b shows the structured flowchart of the multi-channel DMA controller that the embodiment of the invention provides, and this multi-channel DMA controller comprises several DMA passages 11 and data transmission unit 12.
DMA passage 11 after the BD updating message that receives from CPU, reads BD from the CPU internal memory, according to the data storage condition in BD and the peripheral hardware buffer memory, generate transfer instruction;
The workflow diagram of multi-channel DMA controller shown in Fig. 1 c shown in Fig. 1 c, comprising:
The transfer instruction that step 102, data transmission unit 12 receive from each DMA passage 11 is arbitrated several transfer instructions that receive, and obtains the clooating sequence to transfer instruction;
The clooating sequence that step 103, data transmission unit 12 obtain according to arbitration is carried out each transfer instruction, the transmission of data between CPU internal memory and peripheral hardware buffer memory successively.
By the principle of work shown in the multi-channel DMA controller shown in Fig. 1 b and Fig. 1 c, the control operation of DMA data transmission and the data carrying work of data transmission can be separated, the control operation of also namely being transmitted by several DMA passage deal with data, processed the data carrying work of DMA data transmission by data transmission unit, the control operation of DMA passage does not rely on the data carrying work of data transmission unit, and data transmission unit is to arbitrating from the transfer instruction of several DMA passages, the clooating sequence that obtains according to arbitration, carry out successively the indicated data carrying operation of each transfer instruction, the DMA passage carries out next time control operation after needn't waiting the data of data transmission unit to carry EO again, can be in the line production of DMA channel side formation control operation, and the line production that forms data carrying operation in the data transmission unit side, and then can improve the data rate of dma controller, can be applicable to the application scenarios of high speed data transfer.
Before the principle of work of Fig. 1 b shown device is elaborated, first BD is described.
BD is a data structure that is used for the control information of data of description read-write operation, several BD occupy the continuous storage space of a slice in the CPU internal memory, the structure of BD is as shown in table 1, comprises that whether data address, data length, data slice be whether effectively whether the indication (Sop), data slice of the start-up portion of packet be indication (Eop), error message indication (Err), control information indication (Owner), the BD indication (Valid) of the latter end of packet.
Table 1
| Data address | Data length | SOP | EOP | Err | Owner | valid |
CPU gives bus control right before the multi-channel DMA controller, in the data address territory and data length field that address and the data length of data to be read can be write respectively BD, and with the Owner territory be rewritten as the expression multi-channel DMA controller information, then send the BD updating message to multi-channel DMA controller, after multi-channel DMA controller receives the BD updating message, from the CPU internal memory, read BD, judge that according to the information in the Owner territory among the BD bus control right belongs to self, thus can be according to the data address territory among the BD and the information in the data length field reading out data from the CPU internal memory.When multi-channel DMA controller is write data in the CPU internal memory, according to the information in the data address territory among the BD data are write in the CPU internal memory, and the data length that will deposit data in writes in the data length field of BD, and the information that the Owner territory is rewritten as expression CPU, revised BD is sent to the CPU internal memory, CPU learns that by the information in the Owner territory of the BD that newly deposits in the monitoring CPU internal memory bus control right comes back to CPU.
Particularly, DMA passage 11 is used for respectively the control operation of the downlink data of DMA data transmission and the control operation of upstream data are processed, downlink data is for reading and be written to the data the peripheral hardware buffer memory from the CPU internal memory, upstream data is for reading and be written to the data the CPU internal memory from the peripheral hardware buffer memory, correspondingly, transfer instruction also is divided into reads instruction and write command, and data transmission unit 12 also correspondingly carries out data carrying operation, according to write command upstream data carried out data carrying operation downlink data according to reading instruction.
Fig. 2 shows the preferred structure block diagram of the multi-channel DMA controller shown in Fig. 1 b, specifically comprises down going channel 111 and data feedback channel 112 in the DMA passage 11, and data transmission unit 12 comprises read data module 121 and writes data module 122.
Down going channel 111 after the BD updating message that receives from CPU, reads BD from the CPU internal memory, the data volume size according to the data accepted of storing in the reading out data length information among the BD that reads and the peripheral hardware buffer memory generates and reads instruction;
Read data module 121, be connected to the down going channel 111 of several DMA passages 11, be used for the instruction of reading from the down going channel 111 of several DMA passages 11 is arbitrated, the clooating sequence that obtains according to arbitration, read instruction according to each successively and from the CPU internal memory, read corresponding data, and the data of reading are sent to the peripheral hardware buffer memory.
Write data module 122, be connected to the data feedback channel 112 of several DMA passages 11, be used for the write command from the data feedback channel 112 of several DMA passages is arbitrated, the clooating sequence that obtains according to arbitration, from the peripheral hardware buffer memory, read corresponding data according to each write command successively, and the data of reading are sent to the CPU internal memory.
By data feedback channel and down going channel are set in the DMA passage, and the read data module is set in data transmission unit and writes data module, upstream data processing and downlink data processing can be made a distinction, and all control operation and the data carrying operation of data transmission are made a distinction for downlink data and upstream data, can effectively form respectively the line production of the control operation of upstream data and downlink data in the DMA channel side, and the line production that forms respectively the data carrying operation of upstream data and downlink data in the data transmission unit side, and then can improve the data rate of dma controller, can be applicable to the application scenarios of high speed data transfer.
And, owing to according to downlink data and upstream data corresponding functional unit is set respectively in the embodiment of the invention, so that the dma controller that the invention process provides has good Scalability, namely according to the difference of application scenarios, when only needing dma controller to process downlink data, can only in the DMA passage, down going channel be set, the read data module is set in data transmission unit, when only needing dma controller to process upstream data, can only in the DMA passage, data feedback channel be set, in data transmission unit, arrange and write data module, when the needs dma controller is processed downlink data and upstream data, dma controller as shown in Figure 2 can be set.
The below describes respectively the multi-channel DMA controller shown in Fig. 2 in detail to the processing of downlink data and upstream data.
(1), downlink data is processed
Fig. 3 shows multi-channel DMA controller preferred structure block diagram shown in Figure 2, this multi-channel DMA controller comprises: down going channel 111 and read data module 121, down going channel 111 comprises: the descending BD of reading module 1111, downlink command generation module 1112 and descending write-back module 1113.
1, the descending BD module 1111 of reading after the BD updating message that receives from CPU, reads several BD from described CPU internal memory, and preserves several BD that read.
Particularly, after the descending BD of reading module 1111 receives BD updating message from CPU, send the descending BD request of reading to the CPU internal memory, the quantity of the BD that the request that carries in the descending BD of the reading request is read, wherein, the quantity of the BD that this request is read is: from the quantity of the readable BD of the BD updating message indicating of CPU, current BD pointer is to the quantity of the BD shown in the BD ring tail in the BD ring, and the BD quantity of the quantity reckling among default this three of the quantity that reads BD, difference according to application scenarios, the default quantity that reads BD is also different, therefore, as seen each to ask the quantity of the BD that reads be indefinite, can be one, also can be many; And, receive from the CPU internal memory for these descending several BD that read the BD request, and preserve several BD that receive.
2, the downlink command generation module 1112, are used for the data volume size of the data accepted stored in the reading out data length information of the BD that reads according to the descending BD of reading module 1111 and the peripheral hardware buffer memory, generate and read instruction;
Particularly, downlink command generation module 1112 is carried out following operation: read current BD operation, decision operation, command operating is read in generation and command operating is read in transmission; Wherein,
(1), reading current BD operation comprises: in the current time sheet, have in downlink command generation module 1112 in the situation of idle storage space, downlink command generation module 1112 obtains a BD as current BD from the descending BD of reading module 1111; Do not have in downlink command generation module 1112 in the situation of idle storage space, downlink command generation module 1112 continues to wait for, until have in the situation of idle storage space, obtains a BD as current BD from the descending BD of reading module 1111;
(2), decision operation comprises: judge whether the contrast condition is set up, the contrast condition is: the data length sum shown in the corresponding reading out data length information that generates among each BD that reads instruction that contrasts storage in the data length shown in the reading out data length information among the current BD and the downlink command generation module 1112, whether less than the size of the idle storage space in the storage space corresponding with the down going channel of this DMA passage in the peripheral hardware buffer memory, judging in the situation that the contrast condition is set up, carry out to generate and read command operating, otherwise, continue to wait for, until the contrast condition is set up, wait for that namely the data in the peripheral hardware buffer memory are read away, the obtaining of storage space in the peripheral hardware buffer memory discharges, so that the contrast condition is set up;
(3), generate and to read command operating and comprise: generate the instruction of reading corresponding with current BD, in reading instruction, carry reading out data length information among the current BD and the address information of the reading out data among the current BD; And, preserve current BD, preferably, can adopt fifo queue to preserve the corresponding BD that reads instruction that generated;
(4) send and read command operating: the instruction of reading of the corresponding current BD that will generate sends to read data module 121.
3, the read data module 121, be connected to the downlink command generation module 1112 of each down going channel 111, what be used for the clooating sequence that obtains for arbitration currently reads instruction, according to current address information and the reading out data length information of reading in the instruction, from the CPU internal memory, read the data of corresponding length in the storage space of appropriate address, and the data of reading are sent in the peripheral hardware buffer memory in the storage space corresponding with sending the current DMA passage of reading instruction;
Particularly, 121 pairs of instructions of reading from the down going channel 111 of several DMA passages 11 of read data module are arbitrated, for example make the principle of (Round Robin) scheduling arbitrate according to wheel, current in the clooating sequence that obtains for arbitration read instruction, according to current address information and the reading out data length information of reading in the instruction, send read data request to the CPU internal memory, comprise current address information and the reading out data length information of reading in the instruction in the read data request; Reception is from the packet of CPU internal memory for read data request, and the data that receive are sent in the peripheral hardware buffer memory in the storage space corresponding with sending the current DMA passage of reading instruction;
And, be polled to currently when reading instruction, read data module 121 is read response to sending current down going channel (being the downlink command generation module 1112 of the down going channel 111) feedback of reading the DMA passage of instruction; In sense data from the CPU internal memory and after sending to the peripheral hardware buffer memory, also run through response to sending current down going channel (being the downlink command generation module 1112 of the down going channel 111) feedback of reading the DMA passage of instruction;
Correspondingly, downlink command generation module 1112 also is used for: receive from read data module 121 read the response after, preserve current BD; Receiving from the running through after the response of read data module 121, from the BD that downlink command generation module 1112 is preserved, take out a BD and send to descending write-back module 1113; Preferably, as mentioned above, downlink command generation module 1112 is preserved by fifo queue and has correspondingly been generated the BD that reads instruction, herein, takes out a BD from team's head of fifo queue and sends to descending write-back module 1113.
4, descending write-back module 1113 is used for: the control information of the BD that receives is rewritten as CPU, revised BD is sent to the CPU internal memory.Particularly, descending write-back module 1113 is preserved revised BD, stores in the situation of revised BD in judging descending write-back module 1113, and predetermined write back cycle is carried out timing; Within time-count cycle, in the situation of quantity more than or equal to predetermined quantity of the revised BD that preserves, with the revised BD of predetermined quantity as BD to be sent, BD to be sent is sent to the CPU internal memory, in the situation of quantity less than predetermined quantity of the revised BD that preserves, in timing then, the revised BD that preserves as BD to be sent, is sent to the CPU internal memory with BD to be sent.
Fig. 4 shows the workflow diagram of the downlink command generation module 1112 among Fig. 3, also is that Fig. 4 shows the principle of work that down going channel carries out the control operation of downlink data transmission, comprises following processing procedure:
Particularly, judge in the situation of contrast condition establishment, it is the data length sum shown in the corresponding reading out data length information that generates among each BD that reads instruction of storage in the data length shown in the reading out data length information among the current BD and the downlink command generation module 1112, in the situation less than the size of the idle storage space in the storage space corresponding with the down going channel of this DMA passage in the peripheral hardware buffer memory, generate the read instruction corresponding with current BD, in reading instruction, carry reading out data length information among the current BD and the address information of the reading out data among the current BD, process proceeding to step 404;
Judge in the invalid situation of contrast condition, the data length sum shown in the corresponding reading out data length information that generates among each BD that reads instruction of storage in data length shown in the reading out data length information in current BD and the downlink command generation module 1112, in the situation more than or equal to the size of the idle storage space in the storage space corresponding with the down going channel of this DMA passage in the described peripheral hardware buffer memory, processing turns back to step 403, until the contrast condition is set up;
In the contrast condition, need to judge: the data length sum shown in the corresponding reading out data length information that generates among each BD that reads instruction of storage in the data length shown in the reading out data length information among the current BD and the downlink command generation module 1112, with in the peripheral hardware buffer memory with the corresponding storage space of the down going channel of this DMA passage in the relativity of size of idle storage space, its reason is: following steps 405 are described, read data module 121 be polled to one read instruction after, read response can for these downlink command generation module 1112 feedbacks of reading instruction of transmission, read data module 121 this moment is reading out data from the CPU internal memory not, because read data module 121 waiting for CPU internal memory return datas need certain hour, so, after read data module 121 is read response to 1112 transmissions of downlink command generation module, reading to respond the corresponding indicated data of instruction of reading with this in downlink command generation module 1112 does not really read, at this moment, downlink command generation module 1112 should be preserved with this and read to respond corresponding BD, namely preserves the corresponding BD that reads instruction that generated; So, when instruction is read in 1112 generations of downlink command generation module, judge whether the length of data to be carried is less than the size of the idle storage space in the storage space corresponding with the down going channel of this DMA passage in the peripheral hardware buffer memory, and the length of data to be carried just comprises reading out data length and the corresponding reading out data length sum that generates among each BD that reads instruction among the current BD;
The instruction of reading of the corresponding current BD that step 404, downlink command generation module 1112 will generate sends to read data module 121, so that read data module 121 is carried out data carrying operation according to reading instruction;
Fig. 5 shows the work for the treatment of process flow diagram of 121 pairs of downlink datas of read data module among Fig. 3, and namely Fig. 5 shows the fundamental diagram that 121 pairs of downlink datas of read data module carry out the data carrying, comprises following treatment step:
Step 501,121 pairs of instructions of reading from the down going channel 111 of several DMA passages 11 of read data module are arbitrated; Preferably, can adopt RR scheduling to arbitrate, specifically can sort and obtain clooating sequence reading instruction according to the clooating sequence of several DMA passages 11, also namely this clooating sequence be consistent with the clooating sequence of several DMA passages 11;
Current in the clooating sequence that step 502, read data module 121 obtain for arbitration read instruction, according to current address information and the reading out data length information of reading in the instruction, reads the data of corresponding length in the storage space of appropriate address from the CPU internal memory; Particularly, read data module 121 sends read data request to the CPU internal memory, comprises current address information and the reading out data length information of reading in the instruction in the read data request; And read response to downlink command generation module 1112 feedbacks of the down going channel that sends the current DMA passage of reading instruction;
In above-mentioned processing procedure, the descending BD of reading module 1111 reads in batches several BD and preserves the BD that reads from the CPU internal memory, so that downlink command generation module 1112 takes out BD one by one and generate according to BD and to read instruction, so that read data module 121 is carried out data carrying work according to reading instruction; And, downlink command generation module 1112 is according to the response of reading of read data module 121 feedbacks, preserve with read to respond corresponding BD after, read instruction according to next BD generation, do not rely on read data module 121 and whether data are read from the CPU internal memory so that the operation of instruction is read in the generation that downlink command generation module 1112 is carried out, can form the line production to the control operation of downlink data; And, 121 pairs of instructions of reading from the down going channel of several DMA passages of read data module are arbitrated, according to the clooating sequence that arbitration obtains, read instruction according to each successively and carry out data carrying operation, can form the line production to the data carrying operation of downlink data; Thereby can improve the transmission speed of descending DMA data transmission, can be applicable to the application scenarios of high-speed down data transmission.
On the basis of the principle of work of above-mentioned downlink data transmission, in the application scenarios that adopts the BD ring, the DMA data transmission also comprises the processing procedure of descending BD write-back.
Here illustrate first that BD structure of rings and effect thereof describe.The end to end ring texture that the BD ring is comprised of several BD, the structure of each BD is as above shown in the table 1, the BD ring occupies the continuous storage space of a slice in the CPU internal memory, the descending BD of reading module 1111 has read several BD from the CPU internal memory after, downlink command generation module 1112 generates successively according to each BD and reads instruction, behind read data module 121 reading out datas, descending DMA passage 111 should be rewritten BD, Owner territory among the BD is rewritten as the information of expression CPU, then revised BD is sent it back in the CPU internal memory, so that CPU monitors the variation of bus control right.
Fig. 6 shows the workflow diagram of the descending write-back module 1113 among Fig. 3, also is that Fig. 6 shows the principle of work to the BD write-back of downlink data, comprises following processing procedure:
The response that runs through that step 601, downlink command generation module 1112 receive from read data module 121, running through response is the instruction of reading that read data module 121 polls are handled 1112 transmissions of downlink command generation module, also namely from the CPU internal memory sense data and send to the peripheral hardware buffer memory after, to downlink command generation module 1112 feedback;
Particularly, descending write-back module 1113 sends revised BD according to chronograph mechanism; Descending write-back module 1113 is rewritten as CPU with the control information among the BD that receives, and preserves revised BD; Store in the situation of revised BD in the storage space of descending write-back module 1113 judgements self, predetermined write back cycle is carried out timing; Within time-count cycle, in the situation of quantity more than or equal to predetermined quantity of BD after the rewriting of preserving, with the revised BD of predetermined quantity as BD to be sent, BD to be sent is sent to the CPU internal memory, in the situation of quantity less than predetermined quantity of the revised BD that preserves, after timing then, the revised BD that preserves as BD to be sent, is sent to the CPU internal memory with BD to be sent.
By above-mentioned processing procedure, descending write-back module 1113 is write-back BD in bulk, can reduce the number of times of write-back BD, reduce owing to the shared bus bandwidth of write-back BD, thus the speed of raising DMA data transmission.And, introduce chronograph mechanism and sending revised BD to the CPU internal memory, can be in the quantity of revised BD during more than or equal to predetermined quantity, revised BD with predetermined quantity sends to the CPU internal memory in time, can avoid the quantity moment of the revised BD in the down going channel 111 to increase causing when too much congested the or BD of BD to lose, in the quantity of revised BD during less than predetermined quantity, after timing then, revised BD is sent to the CPU internal memory, the quantity of avoiding revised BD is for a long time in the situation less than predetermined quantity, can't return revised BD to CPU, cause CPU to monitor the problem of the overlong time of the BD that waits for write-back, can make CPU monitor in time the situation that bus control right changes.
(2) upstream data is processed
Fig. 7 shows multi-channel DMA controller preferred structure block diagram shown in Figure 2, this multi-channel DMA controller comprises: data feedback channel 112 and write data module 122, data feedback channel 112 comprises: the up BD of reading module 1121, up-on command generation module 1122 and up write-back module 1123.
The up BD module 1121 of reading is used for reading several BD from described CPU internal memory after the BD updating message that receives from CPU, and preserves several BD that read; Particularly, the up BD of reading module 1121 sends the up BD request of reading, the quantity of the BD that the request that carries in the up BD of the reading request is read to the CPU internal memory; Reception from the CPU internal memory for these up several BD that read BD request;
Up-on command generation module 1122, the address information for the data to be written among the BD that data volume is big or small and the up BD of reading module 1121 reads of the data to be sent of storing according to the peripheral hardware buffer memory generates described write command; Particularly, in the current time sheet, up-on command generation module 1122 obtains a BD as current BD from the up BD of reading module 1121, generate write command according to the data volume of the data to be sent of storing in peripheral hardware buffer memory size, in the write command that generates, carry the address information of data to be written in the data length information of data to be sent in the peripheral hardware buffer memory and the CPU internal memory among the current BD; Preserve current BD; The write command that generates sent to write data module 122.
Write data module 122, current write command for the clooating sequence that obtains for arbitration, according to the data length information in the current write command, from the peripheral hardware buffer memory, read the data of corresponding length in the storage control corresponding with the DMA passage that sends current write command, and the data of reading are sent in the respective stored space in the described CPU internal memory of the address information indication in the current write command; And, when being polled to current write command, to data feedback channel (being the up-on command generation module 1122 of data feedback channel 112) the feedback write response of the DMA passage that sends current write command; In sense data from the peripheral hardware buffer memory and after sending to the CPU internal memory, also write to data feedback channel (being the up-on command generation module 1122 of the data feedback channel 112) feedback of the DMA passage that sends current write command and finish response;
Up-on command generation module 1123 also is used for: after receiving from the write response of writing data module 122, preserve current BD; Receiving from writing after writing of data module 122 finish response, from the BD that up-on command generation module 1122 is preserved, take out a BD and send to up write-back module 1123;
Up write-back module 1123 is used for: the control information of the BD that receives is rewritten as CPU, the data length information in the write command is written among the BD, revised BD is sent to the CPU internal memory; Particularly, up write-back module 1123 is preserved revised BD, stores in the situation of revised BD in judging up write-back module 1123, and predetermined write back cycle is carried out timing; Within time-count cycle, in the situation of quantity more than or equal to predetermined quantity of the revised BD that preserves, with the revised BD of predetermined quantity as BD to be sent, BD to be sent is sent to the CPU internal memory, in the situation of quantity less than predetermined quantity of the revised BD that preserves, after timing then, with the revised BD that preserves as BD to be sent, BD to be sent is sent to the CPU internal memory, be about to BD to be sent and send to scheduling unit 13.
Fig. 8 shows the workflow diagram of up-on command generation module 1122 among Fig. 7, also is that Fig. 8 shows the principle of work that data feedback channel carries out the control operation of transmitting uplink data, comprises following processing procedure:
Step 801, the up BD of reading module 1121 read several BD after receiving BD updating message from CPU from the CPU internal memory, and preserve several BD that read; Particularly, the up BD of reading module 1121 sends the up BD request of reading, the quantity of the BD that the request that carries in the up BD of the reading request is read to the CPU internal memory; As mentioned above, the quantity of BD can be one, also can be a plurality of; The up BD of reading module 1121 receive from the CPU internal memory for these up several BD that read the BD request, and preserve several BD that receive;
Step 802, in the current time sheet, in up-on command generation module 1122, have in the situation of idle storage space, up-on command generation module 1122 obtains a BD as current BD from the up BD of reading module 1121; Particularly, store BD in the up BD of the reading module 1121 of up-on command generation module 1122 judgements, and in the situation of available free storage space, in the current time sheet, from the up BD of reading module 1121, obtain a BD as current BD in the up-on command generation module 1122;
Step 803, up-on command generation module 1122 generates the write command corresponding with current BD, carries the address information of data to be written in the data length information of data to be sent in the peripheral hardware buffer memory and the CPU internal memory among the current BD in the write command of generation;
Step 804, up-on command generation module 1122 send to the write command that generates and write data module 122, carry out data carrying operation so that write data module 122 according to write command;
Step 805, up-on command generation module 1122 are after receiving from the write response of writing data module 122, preserve current BD, the buffer queue of preserving BD is fifo queue, wherein write response is when writing 122 pairs of data modules and being polled to the write command that up-on command generation module 1122 sends, and writes data module 122 to up-on command generation module 1122 feedbacks; Step 803 is returned in processing.
Fig. 9 shows the work for the treatment of process flow diagram of writing 122 pairs of upstream datas of data module among Fig. 7, and namely Fig. 9 shows and writes the fundamental diagram that 122 pairs of upstream datas of data module carry out the data carrying, comprises following treatment step:
In above-mentioned processing procedure, the up BD of reading module 1121 reads in batches BD and preserves the BD that reads from the CPU internal memory, so that up-on command generation module 1122 takes out one by one BD and generates write command according to BD, carry out data carrying work so that write data module 122 according to write command, up-on command generation module 1122 is according to the write response of writing data module 122 feedbacks, behind preservation and the corresponding BD of write response, generate write command according to next BD, so that whether the operation of the generation write command that the up BD of reading module 1121 is carried out do not rely on and write data module 122 and data are write in the CPU internal memory, can be to forming the line production to the control operation of upstream data; And, writing 122 pairs of write commands from the data feedback channel of several DMA passages of data module arbitrates, clooating sequence according to arbitration obtains carries out data carrying operation according to each write command successively, can form the line production to the data carrying operation of upstream data; Thereby can improve the transmission speed of up DMA data transmission, can be applicable to the application scenarios of high speed uplink data transmission.
On the basis of the handling principle of above-mentioned transmitting uplink data, in the application scenarios that adopts the BD ring, the DMA data transmission also comprises the processing procedure of up BD write-back.
Figure 10 shows the workflow diagram of the up write-back module 1123 among Fig. 7, also is that Figure 10 shows the principle of work to the BD write-back of upstream data, comprises following processing procedure:
By above-mentioned processing procedure, up write-back module 1123 is write-back BD in bulk, can reduce the number of times of write-back BD, reduce owing to the shared bus bandwidth of write-back BD, thus the speed of raising DMA data transmission.Can also avoid the quantity moment of the revised BD in the down going channel 111 to increase causing when too much congested the or BD of BD to lose, the quantity of avoiding revised BD in the situation less than predetermined quantity, can't be returned revised BD to CPU for a long time.
In sum, technical scheme according to the embodiment of the invention, several DMA passage and data transmission units are set in dma controller, the control operation of data transmission and the data carrying work of data transmission are separated, also namely processed the control operation of DMA data transmission by several DMA passages, particularly, each DMA passage carries out the BD bookkeeping and generates the transfer instruction operation, data carrying work by the whole DMA data transmission of data transmission cell processing, particularly, data transmission unit is to arbitrating from the transfer instruction of several DMA passages, the clooating sequence that obtains according to arbitration, carry out successively each transfer instruction, the transmission of data between CPU internal memory and peripheral hardware buffer memory, as seen, the data control operation that the DMA passage is carried out needn't depend on the data carrying operation that data transmission unit is carried out, can form in the DMA channel side line production of the control operation of data transmission, data transmission unit is successively to processing from the transfer instruction of several DMA passages, form the line production of the data carrying operation of data transmission in the data transmission unit side, and then can improve the data rate of dma controller, can be applicable to the application scenarios of high speed data transfer.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (13)
1. the direct memory access dma controller of hyperchannel is characterized in that, comprising: several DMA passage and data transmission units;
Described DMA passage after the buffer memory identifier BD updating message that receives from central processor CPU, reads BD from the CPU internal memory, according to the data storage condition in BD and the peripheral hardware buffer memory, generate transfer instruction;
Described data transmission unit is used for arbitrating from the transfer instruction of several described DMA passages, according to the clooating sequence that arbitration obtains, carries out successively each transfer instruction, the transmission of data between described CPU internal memory and described peripheral hardware buffer memory.
2. multi-channel DMA controller according to claim 1 is characterized in that, described transfer instruction comprises: read instruction; Then,
Described DMA passage, specifically comprise: down going channel, be used for after the BD updating message that receives from CPU, from described CPU internal memory, read BD, data volume size according to the data accepted of storing in the reading out data length information among the BD that reads and the described peripheral hardware buffer memory generates the described instruction of reading;
Described data transmission unit, specifically comprise: the read data module, be used for the instruction of reading from the down going channel of several described DMA passages is arbitrated, the clooating sequence that obtains according to arbitration, read instruction according to each successively and from described CPU internal memory, read corresponding data, and the data of reading are sent to described peripheral hardware buffer memory.
3. multi-channel DMA controller according to claim 2 is characterized in that, described down going channel specifically comprises:
The descending BD module of reading is used for reading several BD from described CPU internal memory after the BD updating message that receives from CPU, and preserves several BD that read;
The downlink command generation module is used for the data volume size of the data accepted stored in the reading out data length information of the BD that reads according to the described descending BD of reading module and the described peripheral hardware buffer memory, generates the described instruction of reading.
4. multi-channel DMA controller according to claim 3 is characterized in that, described downlink command generation module specifically is used for: current BD operation, decision operation are read in execution, command operating is read in generation and command operating is read in transmission; Wherein,
Read current BD operation: in the current time sheet, in described downlink command generation module, have in the situation of idle storage space, from the described descending BD of reading module, obtain a BD as current BD;
Decision operation: judge whether the contrast condition is set up, the contrast condition is: contrast the data length sum shown in the corresponding reading out data length information that generates among each BD that reads instruction of storing in the data length shown in the reading out data length information among the current BD and the described downlink command generation module, whether less than the size of the idle storage space in the storage space corresponding with the down going channel of this DMA passage in the described peripheral hardware buffer memory, judging in the situation that the contrast condition is set up, carry out to generate and read command operating, otherwise, continue to wait for, until the contrast condition is set up;
Command operating is read in generation: generate the read instruction corresponding with current BD, carry reading out data length information among the current BD and the address information of the reading out data among the current BD in reading instruction; And in described downlink command generation module, preserve current BD;
Command operating is read in transmission: the read instruction corresponding with current BD that will generate sends to described read data module.
5. multi-channel DMA controller according to claim 4 is characterized in that, described read data module specifically is used for:
Current in the clooating sequence that obtains for arbitration read instruction, according to current address information and the reading out data length information of reading in the instruction, from described CPU internal memory, read the data of corresponding length in the storage space of appropriate address, and the data of reading are sent in the described peripheral hardware buffer memory in the storage space corresponding with sending the current DMA passage of reading instruction.
6. multi-channel DMA controller according to claim 4, it is characterized in that described read data module also is used for: the clooating sequence that obtains for arbitration current read instruction, be polled to currently when reading instruction, read response to sending the current down going channel feedback of reading the DMA passage of instruction; In sense data from described CPU internal memory and after sending to described peripheral hardware buffer memory, also run through response to sending the current down going channel feedback of reading the DMA passage of instruction; Then,
Described down going channel also comprises: descending write-back module; Wherein,
Described downlink command generation module also is used for: receive from described read data module read in described downlink command generation module, preserve current BD after the response; Receiving from the running through after the response of described read data module, from the BD that described downlink command generation module is preserved, take out a BD and send to described descending write-back module;
Described descending write-back module is used for: the control information of the BD that receives is rewritten as CPU, revised BD is sent to described CPU internal memory.
7. multi-channel DMA controller according to claim 6 is characterized in that, described descending write-back module specifically is used for:
Preserve revised BD, in judging described descending write-back module, store in the situation of revised BD, predetermined write back cycle is carried out timing; Within time-count cycle, in the situation of quantity more than or equal to predetermined quantity of BD after the rewriting of preserving, with the revised BD of predetermined quantity as BD to be sent, BD to be sent is sent to described CPU internal memory, in the situation of quantity less than predetermined quantity of the revised BD that preserves, after timing then, the revised BD that preserves as BD to be sent, is sent to described CPU internal memory with BD to be sent.
8. multi-channel DMA controller according to claim 1 is characterized in that, described transfer instruction comprises: write command; Then,
Described DMA passage, specifically comprise: data feedback channel, after being used for receiving the BD updating message from CPU, from described CPU internal memory, read BD, address information according to the data to be written among the big or small BD with reading of the data volume of the data to be sent of storing in the described peripheral hardware buffer memory generates described write command;
Described data transmission unit, specifically comprise: write data module, be used for the write command from the data feedback channel of several described DMA passages is arbitrated, the clooating sequence that obtains according to arbitration, from described peripheral hardware buffer memory, read corresponding data according to each write command successively, and the data of reading are sent to described CPU internal memory.
9. multi-channel DMA controller according to claim 8 is characterized in that, described data feedback channel specifically comprises:
The up BD module of reading is used for reading several BD from described CPU internal memory after the BD updating message that receives from CPU, and preserves several BD that read;
The up-on command generation module, the address information for the data to be written among the BD that data volume is big or small and the described up BD of reading module reads of the data to be sent of storing according to described peripheral hardware buffer memory generates described write command.
10. multi-channel DMA controller according to claim 9 is characterized in that, described up-on command generation module specifically is used for:
In the current time sheet, in described up-on command generation module, have in the situation of idle storage space, from the described up BD of reading module, obtain a BD as current BD;
Generate the write command corresponding with current BD, in the write command that generates, carry the address information of data to be written in the data length information of data to be sent in the described peripheral hardware buffer memory and the CPU internal memory among the current BD;
In described up-on command generation module, preserve current BD;
The write command that generates is sent to the write data module.
11. multi-channel DMA controller according to claim 10 is characterized in that, the write data module specifically is used for:
Current write command in the clooating sequence that obtains for arbitration, according to the data length information in the current write command, from described peripheral hardware buffer memory, read the data of corresponding length in the storage control corresponding with the DMA passage that sends current write command, and the data of reading are sent in the respective stored space in the described CPU internal memory of the address information indication in the current write command.
12. multi-channel DMA controller according to claim 11 is characterized in that, the write data module also is used for: when being polled to current write command, to the data feedback channel feedback write response of the DMA passage that sends current write command; In sense data from described peripheral hardware buffer memory and after sending to described CPU internal memory, also write to the data feedback channel feedback of the DMA passage that sends current write command and finish response; Then,
Described data feedback channel also comprises: up write-back module; Wherein,
Described up-on command generation module also is used for: after the write response that receives from the write data module, preserve current BD at described up-on command generation module; Receive finish response from writing of write data module after, from the BD that described up-on command generation module is preserved, take out a BD and send to described up write-back module;
Described up write-back module is used for: the control information of the BD that receives is rewritten as CPU, the data length information in the described write command is written among the BD, revised BD is sent to described CPU internal memory.
13. multi-channel DMA controller according to claim 12 is characterized in that, described up write-back module specifically is used for:
Preserve revised BD; In judging described up write-back module, store in the situation of revised BD, predetermined write back cycle is carried out timing; Within time-count cycle, in the situation of quantity more than or equal to predetermined quantity of BD after the rewriting of preserving, with the revised BD of predetermined quantity as BD to be sent, BD to be sent is sent to described CPU internal memory, in the situation of quantity less than predetermined quantity of the revised BD that preserves, after timing then, the revised BD that preserves as BD to be sent, is sent to described CPU internal memory with BD to be sent.
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Address after: Cangshan District of Fuzhou City, Fujian province 350002 Jinshan Road No. 618 Garden State Industrial Park 19 floor Patentee after: RUIJIE NETWORKS CO., LTD. Address before: Cangshan District of Fuzhou City, Fujian province 350002 Jinshan Road No. 618 Garden State Industrial Park 19 floor Patentee before: Fujian Xingwangruijie Network Co., Ltd. |