CN109145397B

CN109145397B - External memory arbitration system supporting parallel running water access

Info

Publication number: CN109145397B
Application number: CN201810853292.1A
Authority: CN
Inventors: 龙斌
Original assignee: Changsha Jingmei Integrated Circuit Design Co ltd
Current assignee: Changsha Jingmei Integrated Circuit Design Co ltd
Priority date: 2018-07-30
Filing date: 2018-07-30
Publication date: 2023-04-28
Anticipated expiration: 2038-07-30
Also published as: CN109145397A

Abstract

The invention discloses a memory access arbitration system for parallel running water. Aiming at the characteristics of the existing high-speed external memory, namely the characteristics that an access command and a data channel are completely independent and can be executed in a full-flow way, a group of external memory access arbitration systems which can be accessed in a parallel flow way are designed, and arbitration mechanisms of a command sending channel, a write data sending channel and a read data receiving channel are completely independent; the write data transmission and the read data reception of the multiple access request port are ensured to be mutually independent and can be executed in parallel; meanwhile, aiming at one end of the external memory, when one group of access commands are executed, the analysis and execution of the next group of access commands can be processed in parallel while the data transmission process is being processed; and so on. This ensures that the external memory unit can execute at full speed and efficiently, giving full play to the actual throughput efficiency of the external memory as much as possible.

Description

External memory arbitration system supporting parallel running water access

Technical Field

The invention mainly relates to the field of read-write management of random access memories in chip design. In particular to multi-channel arbitration and continuous read-write operation for external memory access in a chip.

Background

In chip design, a large number of read and write operations for external memory are required. Such as extensive read and write operations of instructions and data in a GPGPU, and switching and synchronization operations of video input-output data frames. In these applications, there are a large number of memory read-write interfaces inside the chip, which require a large amount of read-write and data exchange to the external cache. The storage arbitration unit bears command forwarding between the multiple access interface and the external storage unit, data transmission and global control; therefore, the efficiency and the conversion speed of the storage arbitration unit between the multi-path storage read-write operation interface and the external memory become the key of the actual working performance of the chip.

At present, various external memory chips are rapidly advanced, most of the memory chips adopt mechanisms for continuously transmitting and executing command and access data, the clock frequency, the data width and other aspects are greatly improved, and a large amount of memory resources and high-speed data bandwidth can be provided; meanwhile, the defects of long access time, transmission delay and the like are brought.

The existing multi-path storage arbitration unit is designed based on the instant storage principle, and an arbitration mechanism is realized by adopting an exclusive strategy, namely when one access port applies for the right of occupation of an access channel, the arbitration unit can only allocate the access channel to other access ports after the current data read-write transmission is completely finished. In this case, there is a serial operation process of transmitting and receiving commands and data of each access port, and commands and data channels of the external memory cannot be operated in parallel, which greatly reduces the actual throughput efficiency of the external memory. Therefore, the design of the high-efficiency parallel access storage arbitration unit ensures that the access command and the data channel realize full stream, and simultaneously gives consideration to the coordination and high-efficiency work of the multi-access interface and the full utilization of the data bandwidth of the external memory, which is particularly important for improving the overall actual performance of the chip.

Disclosure of Invention

Aiming at the characteristics of the existing high-speed external memory, namely the characteristics that an access command and a data channel are completely independent and can be executed in a full-flow way, a group of external memory access arbitration systems which can be accessed in a parallel flow way are designed, and arbitration mechanisms of a command sending channel, a write data sending channel and a read data receiving channel are completely independent; the write data transmission and the read data reception of the multiple access request port are ensured to be mutually independent and can be executed in parallel; meanwhile, aiming at one end of the external memory, when one group of access commands are executed, the analysis and execution of the next group of access commands can be processed in parallel while the data transmission process is being processed; and so on. This ensures that the external memory unit can execute at full speed and efficiently, giving full play to the actual throughput efficiency of the external memory as much as possible.

Compared with the prior art, the invention has the advantages that: 1. the logic is simple: the memory access arbitration system for parallel running water access provided by the invention does not adopt complex algorithms, is an algorithm which is more beneficial to hardware realization, and has clear organization structure; 2. the performance is excellent: the arbitration system provided by the invention adopts the method of executing the access command transmission, the write data transmission and the read data reception of the full-flow water, so that the hardware resources are reduced and reduced as much as possible while the overall transmission efficiency of the data is ensured; 3. the use is convenient: the arbitration system provided by the invention is clear and independent of the process, and has good reusability and portability.

Drawings

FIG. 1 illustrates the location of a memory arbitration system in a system-on-chip according to the present invention;

FIG. 2 shows the internal structure of the memory arbitration system according to the present invention.

Detailed Description

The invention will be described in further detail below with reference to the drawings and the specific examples.

As shown in FIG. 1, one side of the memory arbitration unit disclosed by the invention is connected with a plurality of memory access ports in the chip, and the other side is connected with a memory controller; wherein the arbitration of multiple accesses and the bridging effect are undertaken.

As shown in fig. 2, the internal structure of the memory arbitration unit disclosed in the present invention includes an external set of access allocation units, four sets of access receiving queues (FIFOs) (a priority write operation queue, a normal write operation queue, a priority read operation queue, and a normal read operation queue), a read/write data management module (a data to be written receiving module, a data to be written queue, a write command queue, a read data sending module, a read data receiving queue, a read waiting queue), and a memory command sending module, and two operation modes (read operation and write operation) for data access are described below as examples.

The write operation flow is as follows, access allocation unit: receiving a write operation command; according to the priority of the write operation port, the port number, the initial address, the single data continuous access length and other information of the write operation are packed and integrated; to a priority write operation queue or a normal write operation queue (priority is determined by port number). The data receiving module to be written: detecting that the two write operation queues are not empty, reading write operation access information from the selected write operation queue (priority write operation queue is priority), and extracting a port number and a single data continuous access length from the write operation access information; the write operation port number and the write data receiving response signal are returned to the access allocation unit, and write data and corresponding write data byte enabling are received after corresponding delay beats and temporarily stored in a data queue to be written; when all write data of a single write operation are received completely, a write operation ending signal is sent, and the starting address of the write operation and the single data continuous access length information are integrally sent to a write command queue (at the moment, the write operation is completed relative to an upper access interface). The external memory command sending module detects that the write command queue is not empty, reads the starting address of the write operation and the single-time data continuous access length, sends an external memory write operation command according to the external memory access time sequence interface requirement, and forwards data to be written and corresponding byte enabling from the data queue to be written.

The read operation flow is as follows, access command distribution unit: receiving a read operation command; according to the priority of the read operation port, the port number, the starting address, the single data continuous access length and other information of the read operation are packed and integrated; to a priority read operation queue or a normal read operation queue (priority is determined by port number). The external memory command sending module detects that two read operation queues are not empty, reads read operation access information from the selected read operation queue (priority read operation queue priority), and separates a start address of read operation and a single-time data continuous access length from the read operation access information; sending a memory read operation command according to the memory access time sequence requirement; and simultaneously, the port number of the read operation and the single-data continuous access length information are integrated and sent to a read waiting queue. The read data sending module detects that the read waiting queue is not empty, and extracts an access port number and a single-data continuous access length from the read waiting queue; the effective reading data sent by the external memory is returned to the access allocation unit; transmitting by the access allocation unit to the designated port; a read data valid signal is generated at the same time and when all data has been returned correctly, a read operation end signal is generated (at which time the read operation has been completed with respect to the last access to the interface).

As shown in fig. 2, in the actual design process, the four main body modules of the access allocation unit, the data receiving module to be written, the data sending module to be read and the external memory command sending module are independent (the interior is designed in the form of a finite state machine), the four modules can be executed simultaneously, and the read and write operations between different ports can be executed simultaneously (for example, when the external memory is responding to the read and write request of the port No. 0, the arbitration unit can receive the data to be written from the port No. 1 or send the read data to the port No. 2 at the same time), so that the efficiency of read and write access can be accelerated, the port conversion delay is reduced, and the effective matching of the data rate between the access port and the external memory controller module is realized.

Claims

1. In the field of graphic processing chips, a storage arbitration system for read-write operation of multiple ports with priority strategies; in the implementation process, firstly, access requests sent by multiple ports are organized in sequence according to the difference of port priorities, then, according to the ordered sequence, the running access commands and the data to be written are orderly sent to the external memory unit, and the read data obtained from the external memory unit are orderly distributed and returned to the respective access request ports, and the method comprises the following four units:

a. an access allocation module: receiving an upper access request, packaging and integrating the initial address, the port number and the single data continuous access length information of the access, and distributing the initial address, the port number and the single data continuous access length information to a priority write access queue, a common write access queue, a priority read access queue and a common read access queue according to different port priorities and different read-write access directions;

b. the data receiving module to be written: reading the waiting write access from the write access queue, separating the port number of the current access and the single data continuous access length according to the data packaging format of the access allocation unit, receiving write data and byte enabling from a designated port through the access allocation module according to a write data response mechanism, and temporarily storing the write data and byte enabling in the data queue to be written;

c. the read data sending module reads the read access request which is sent by the read access command and waits for the read data from the read waiting queue, separates the current accessed port number and single data continuous access length, reads the read data from the read data receiving queue or directly receives the external memory, and sends back the read data to the appointed port through the access allocation module according to the read data response mechanism;

d. the external memory command sending module: detecting whether the priority read access queue, the common read access queue and the write command queue are not empty, if so, sending a read request to the corresponding queue and setting the valid flag of the read data of the corresponding queue to be high; and simultaneously, according to the state of the current access queue, sending the external memory access command according to the external memory interface time sequence.