CN103064476A - Design method of mainboard with dual CPUs (central processing units) with asymmetric memories - Google Patents
Design method of mainboard with dual CPUs (central processing units) with asymmetric memories Download PDFInfo
- Publication number
- CN103064476A CN103064476A CN2013100179642A CN201310017964A CN103064476A CN 103064476 A CN103064476 A CN 103064476A CN 2013100179642 A CN2013100179642 A CN 2013100179642A CN 201310017964 A CN201310017964 A CN 201310017964A CN 103064476 A CN103064476 A CN 103064476A
- Authority
- CN
- China
- Prior art keywords
- memories
- mainboard
- cpu0
- cpu1
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Microcomputers (AREA)
Abstract
The invention provides a design method of a mainboard with dual CPUs (central processing units) with asymmetric memories. The method includes the design steps: dividing the mainboard into a left portion and a right portion, arranging one CPU on each portion, vertically arranging four memory slots on the CPU1 on the left portion respectively, vertically arranging six memory slots on the CPU0 on the right portion respectively, arranging a south bridge chip below the bottom memory slot of the right portion, arranging six PCIE (peripheral component interface express) slots below the memory slots of the left portion, enabling the CPU0 to be externally connected with twelve memories, and enabling the CPU1 to be externally connected with eight memories. Since the CPU0 is externally connected with the twelve memories, the CPU1 is externally connected with the eight memories, and the PCIE slots are six, PCIE I/O (input/output) of the mainboard is expanded effectively.
Description
Technical field
The present invention relates to a kind of Computer Applied Technology field, specifically a kind of pair of CPU asymmetry internal memory motherboard design method.
Background technology
Nearly 24 of the internal memories that Intel RomleyEP platform can dispose, at present industry mainstream standard mainboard be designed and sized to 12x13inch, if but in the mainboard of 12x13inch, design 24 root memories and will cause the PCIE I/O expansion of mainboard to be extremely restricted.
Summary of the invention
Technical assignment of the present invention is to solve the deficiencies in the prior art, and a kind of pair of CPU asymmetry internal memory motherboard design method is provided.
Technical scheme of the present invention realizes in the following manner, design procedure is as follows: with mainboard few two parts about me, each part arranges a CPU, the CPU1 of left half arranges respectively up and down 4 memory banks, and the CPU0 of right half arranges respectively up and down 6 memory banks, and the below of right half below memory bank arranges South Bridge chip, the memory bank below of left half arranges 6 PCIE slot slots, external 12 root memories of this design CPU0, external 8 root memories of CPU1, totally 6 of PCIE slot.
Outstanding beneficial effect of the present invention: mainboard adopts two CPU internal memory asymmetric design, and the PCIE I/O of the mainboard that makes is effectively expanded.
Description of drawings
The structural representation of the mainboard that accompanying drawing 1 is.
Embodiment
Below in conjunction with accompanying drawing method of the present invention is described in further detail.
Now design a kind of pair of asymmetrical mainboard of CPU internal memory (internal memories of two identical external varying numbers of CPU), guaranteeing to guarantee in the more situation of amount of memory that PCIE Slot quantity is more than enough.
Design procedure is as follows:
With mainboard few two parts about me, each part arranges a CPU, the CPU1 of left half arranges respectively up and down 4 memory banks, the CPU0 of right half arranges respectively up and down 6 memory banks, the below of right half below memory bank arranges South Bridge chip, and the memory bank below of left half arranges 6 PCIE slot slots, external 12 root memories of this design CPU0, external 8 root memories of CPU1, totally 6 of PCIE slot.
External 12 root memories of this design CPU0, external 8 root memories of CPU1, totally 6 of PCIE slot.As shown in Figure 1.The PCIE I/O of mainboard is effectively expanded.
Except the disclosed technical characterictic of instructions of the present invention, be the public office technology of those skilled in the art.
Claims (1)
1. two CPU asymmetry internal memory motherboard design method, it is characterized in that, design procedure is as follows: with mainboard few two parts about me, each part arranges a CPU, the CPU1 of left half arranges respectively up and down 4 memory banks, the CPU0 of right half arranges respectively up and down 6 memory banks, the below of right half below memory bank arranges South Bridge chip, the memory bank below of left half arranges 6 PCIE slot slots, external 12 root memories of this design CPU0, external 8 root memories of CPU1, totally 6 of PCIE slot.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013100179642A CN103064476A (en) | 2013-01-18 | 2013-01-18 | Design method of mainboard with dual CPUs (central processing units) with asymmetric memories |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013100179642A CN103064476A (en) | 2013-01-18 | 2013-01-18 | Design method of mainboard with dual CPUs (central processing units) with asymmetric memories |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103064476A true CN103064476A (en) | 2013-04-24 |
Family
ID=48107134
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013100179642A Pending CN103064476A (en) | 2013-01-18 | 2013-01-18 | Design method of mainboard with dual CPUs (central processing units) with asymmetric memories |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103064476A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102520768A (en) * | 2011-12-29 | 2012-06-27 | 曙光信息产业股份有限公司 | Blade server motherboard and system |
| CN102768561A (en) * | 2012-05-30 | 2012-11-07 | 曙光信息产业股份有限公司 | Design method for twinbridge piece mainboard redundancy |
| CN102789290A (en) * | 2011-05-20 | 2012-11-21 | 鸿富锦精密工业（深圳）有限公司 | Server and mainboard thereof |
-
2013
- 2013-01-18 CN CN2013100179642A patent/CN103064476A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102789290A (en) * | 2011-05-20 | 2012-11-21 | 鸿富锦精密工业（深圳）有限公司 | Server and mainboard thereof |
| CN102520768A (en) * | 2011-12-29 | 2012-06-27 | 曙光信息产业股份有限公司 | Blade server motherboard and system |
| CN102768561A (en) * | 2012-05-30 | 2012-11-07 | 曙光信息产业股份有限公司 | Design method for twinbridge piece mainboard redundancy |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20200233803A1 (en) | Efficient hardware architecture for accelerating grouped convolutions | |
| CN107111451B (en) | Apparatus and method for managing multiple sequential write streams | |
| CN203909710U (en) | Multifunctional low-level reset circuit suitable for SoC chips | |
| CN106970894A (en) | A kind of FPGA isomery accelerator cards based on Arria10 | |
| Qiao et al. | FANS: FPGA-accelerated near-storage sorting | |
| CN107346170A (en) | A kind of FPGA Heterogeneous Computings acceleration system and method | |
| CN202383569U (en) | Mainboard with multifunctional extensible peripheral component interconnect express (PCIE) interface device | |
| CN101930422A (en) | Multi-core CPU interconnection structure based on multilayer AHB bus | |
| Kogge et al. | Yearly update: exascale projections for 2013. | |
| CN104636089A (en) | Method for accelerating performance of servers of domestic central processing units on basis of NVME (nonvolatile memory express) technology | |
| CN104951268A (en) | Method for implementing extended high-performance graphics card based on CPCI | |
| CN205353908U (en) | Quick heat abstractor of computer CPU | |
| CN103064476A (en) | Design method of mainboard with dual CPUs (central processing units) with asymmetric memories | |
| CN105892931A (en) | heterogeneous CPU-GPU system configuration based on intelligent flash cache | |
| CN208538124U (en) | A kind of server master board based on 1621 processor of Shen prestige | |
| CN208766658U (en) | A kind of server system | |
| CN203759602U (en) | Nest plate-based CPCI (Compact Peripheral Component Interconnect) industrial control computer mainboard | |
| CN105988954B (en) | Area description element management method and its electronic device | |
| CN202102433U (en) | Device for expanding IO (input and output) bandwidth of dragon core CPU (central processing unit) | |
| CN204883678U (en) | High performance shows accuse unit based on homemade treater godson 3B | |
| CN208938051U (en) | Mainboard and computer based on Feiteng processor | |
| CN204288069U (en) | A kind of server memory | |
| CN202771309U (en) | Mainboard based on SR5690 | |
| WO2015117524A1 (en) | Clock tree implementation method, system-on-chip and computer storage medium | |
| CN202771422U (en) | Interconnection device for Godson 3 CPUs and chipsets |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130424 |