CN202771422U

CN202771422U - Interconnection device for Godson 3 CPUs and chipsets

Info

Publication number: CN202771422U
Application number: CN 201220250384
Authority: CN
Inventors: 郑臣明; 邵宗有; 沙超群; 王晖; 柳胜杰
Original assignee: Dawning Information Industry Beijing Co Ltd
Current assignee: Dawning Information Systems (liaoning) Co Ltd
Priority date: 2012-05-30
Filing date: 2012-05-30
Publication date: 2013-03-06
Anticipated expiration: 2022-05-30

Abstract

The utility model relates to a CPU (Central Processing Unit) interconnection technology, in particular to an interconnection device for Godson 3 CPUs and chipsets. The interconnection device comprises Godson CPU sets and chipsets, wherein CPUs of the CPU sets are sequentially connected in series, and at least two Godson CPUs of the CPU sets are connected with the chipsets through 16-digit HT (Hyper Transport) buses, so that the IO (Input/output) property of a Godson 3 CPU interconnection framework is improved.

Description

The device that No. 3 serial CPU of a kind of Godson and chipset are interconnected

Technical field

The utility model relates to the CPU interconnection technique, particularly relates to the interconnected device of No. 3 serial CPU of a kind of Godson and chipset.

Background technology

No. 3 serial CPU of Godson that research and develop calculate in the Chinese Academy of Sciences, the present known 4 core 3A that comprise, 8 core 3B, the CPU of 8 cores or 16 core 3C, the Godson 3A CPU of 4 cores emerged in October, 2009, the Godson 3B CPU of 8 cores emerged in November, 2010, and Godson 3C CPU is in development, and they are CPU with complete independent intellectual property right that the complete self-dependent strength of Chinese oneself is is independently researched and developed; But because the time that No. 3 serial CPU of Godson emerge is short, many interconnected application schemes of No. 3 CPU of Godson and various supporting application scheme all have to be designed and create, the known interconnect scheme of No. 3 CPU of Godson is two-way and four road interconnect architectures at present, Fig. 1 is the present existing two-way interconnect architecture schemes of No. 3 CPU of Godson, and Fig. 2 is at present existing four road interconnect architecture schemes of No. 3 CPU of Godson.

Because No. 3 CPU of each Godson have 2 16 HT bus, as shown in Figure 1, in the interconnected framework of No. 3 CPU of two Godsons, wherein in 2 16 the HT bus of No. 3 CPU of the first Godson is connected with chipset, its another 16 HT bus connects No. 3 CPU of the second Godson, and for No. 3 CPU of the second Godson, its No. 3 CPU of one 16 HT bus and the first Godson are connected, and another HT bus of 16 is idle.

Because each HT bus of 16 can be divided into 28 HT bus, therefore in No. 3 CPU interconnect architectures of four road Godsons as shown in Figure 2, No. 3 CPU of four Godsons connect successively by 8 HT bus, and join end to end, but, wherein only 16 HT buses of No. 3 CPU of a Godson are connected with chipset, and 16 HT buses of No. 3 CPU of other three Godsons are idle.

Can find out from Fig. 1 and Fig. 2, this two schemes has only been paid attention to the operational performance of No. 3 CPU of Godson, and does not solve the IO performance of No. 3 CPU of Godson; And the IO performance bottleneck has become the principal element that the restriction computing power improves in recent years, and the IO performance that how can improve again No. 3 CPU of Godson when guaranteeing No. 3 CPU operational performances of Godson is difficult problems that everybody faces.

The utility model content

For solving the problem that when guaranteeing No. 3 CPU operational performances of Godson, can improve again the IO performance of No. 3 CPU of Godson, the utility model adopts 16 HT buses with cpu idle in No. 3 CPU interconnect architectures of Godson to be connected with chipset, thereby improves the IO performance of No. 3 CPU interconnect architectures of Godson.

In order to achieve the above object, technical scheme provided by the utility model is:

The device that No. 3 serial CPU of a kind of Godson and chipset are interconnected, this device comprises Godson CPU group and chipset, the CPU in the described Godson CPU group connects successively, has at least two Godson CPUs to be connected with described chipset by 16 HT buses in the described Godson CPU group.

Further, described Godson CPU group comprises two Godson CPUs, and described two Godson CPUs are connected by 16 HT buses and are connected with described chipset by 16 HT buses respectively.

Further, described Godson CPU group comprises four Godson CPUs, and described four Godson CPUs are connected successively by 8 HT buses, and forms loop configuration, wherein has at least two Godson CPUs to be connected with chipset by 16 HT buses.

Further, described two Godson CPUs comprise Godson 3A CPU, Godson 3B CPU or Godson 3C CPU.

Further, described four Godson CPUs (1) are Godson 3A CPU.

Further, the north bridge chips in the described chipset comprises SR5690, SR5670 or SR5650 chipset.

Further, the South Bridge chip in the described chipset is SP5100, SP5100R or SP5100RS chipset.

Adopt technique scheme, technique effect of the present utility model has:

The utility model is by connecting chipset with HT bus idle in No. 3 CPU interconnect architectures of original Godson, solved the problem that when guaranteeing No. 3 CPU operational performances of Godson, can improve again the IO performance of No. 3 CPU of Godson, the IO performance of No. 3 CPU interconnect architectures of original Godson has been improved 2 times or 4 times.

Description of drawings

Fig. 1 is the interconnect scheme of known No. 3 CPU of two-way Godson;

Fig. 2 is the interconnect scheme of known No. 3 CPU of four road Godsons;

Fig. 3 is the interconnect scheme of No. 3 CPU of two-way Godson of the present utility model;

Fig. 4 is the interconnect scheme of No. 3 CPU of four road Godsons of the present utility model;

Wherein: 1 Godson CPU, 2 chipsets.

Embodiment

Below be embodiment provided by the utility model, only be to further specify application of the present utility model, rather than limit, as shown in Figure 3, this device comprises 1, two Godson CPU of two Godson CPUs 1 by 16 HT bus series connection, and each Godson CPU 1 all is connected with a chipset 2 by 16 HT buses, make the utility model when guaranteeing No. 3 CPU operational performances of Godson, its IO performance has been improved 2 times; In addition, the Godson CPU 1 in this device is preferably Godson 3A CPU, Godson 3B CPU or Godson 3C CPU, makes Godson CPU supporting more reasonable of this device.

As shown in Figure 4, this device comprises four Godson CPUs 1, four Godson CPUs 1 are connected successively by 8 HT buses, and join end to end, four Godson CPUs 1 all are connected with chipset 2 by 16 HT buses, make the utility model when guaranteeing No. 3 CPU operational performances of Godson, its IO performance 4 times have been improved, the design of this kind framework has namely guaranteed the cpu performance of original architecture design, has expanded again the IO bandwidth of this framework, make the 22lanes of PCIE bus be extended to 88lanes, and support 24 hard disks by supporting 6 SATA hard disks to be extended to, and make other IO interfaces, for example the USB mouth is also corresponding becomes 4 times; The utility model also can according to the needs of IO bandwidth, select to connect 2～4 chipsets 2 flexibly in four Godson CPUs 1 of this device; In addition, the Godson CPU 1 in this device is preferably 3A CPU, makes Godson CPU supporting more reasonable of this device.

North bridge chips in the utility model chipset 2 is preferably SR5690, SR5670 or SR5650 chipset, and South Bridge chip is SP5100, SP5100R or SP5100RS chipset.

It should be noted that at last, above embodiment is only unrestricted in order to the technical solution of the utility model to be described, although with reference to preferred embodiment the utility model is had been described in detail, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement the technical solution of the utility model, and not breaking away from the spirit and scope of technical solutions of the utility model, it all should be encompassed in the middle of the claim scope of the present utility model.

Claims

1. the interconnected device of No. 3 serial CPU of a Godson and chipset, this device comprises Godson CPU (1) group and chipset (2), CPU in described Godson CPU (1) group connects successively, it is characterized in that: have at least two Godson CPUs (1) to be connected with described chipset (2) by 16 HT buses in described Godson CPU (1) group.

2. device as claimed in claim 1 is characterized in that: described Godson CPU (1) group comprises two Godson CPUs (1), and described two Godson CPUs (1) are by 16 HT buses series connection and be connected with described chipset (2) by 16 HT buses respectively.

3. device as claimed in claim 1, it is characterized in that: described Godson CPU (1) group comprises four Godson CPUs (1), described four Godson CPUs (1) are connected successively by 8 HT buses, and the formation loop configuration, wherein have at least two Godson CPUs (1) to be connected with chipset (2) by 16 HT buses.

4. device as claimed in claim 2, it is characterized in that: described two Godson CPUs (1) comprise Godson 3A CPU, Godson 3B CPU or Godson 3C CPU.

5. device as claimed in claim 3, it is characterized in that: described four Godson CPUs (1) are Godson 3A CPU.

6. such as claim 1,2,3 arbitrary described devices, it is characterized in that: the north bridge chips in the described chipset (2) comprises SR5690, SR5670 or SR5650 chipset.

7. device as claimed in claim 6, it is characterized in that: the South Bridge chip in the described chipset (2) is SP5100, SP5100R or SP5100RS chipset.