CN103022138B - High-reliability depletion type power semiconductor device and manufacture method thereof - Google Patents
High-reliability depletion type power semiconductor device and manufacture method thereof Download PDFInfo
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Abstract
The invention provides a kind of High-reliability depletion type power semiconductor device and manufacture method thereof, this semiconductor device includes: Semiconductor substrate；The epitaxial layer of the first doping type being positioned in described Semiconductor substrate；It is sequentially located at the gate dielectric layer on described epitaxial layer and gate electrode；Being positioned at the well region of the second doping type of described gate electrode both sides, described epitaxial layer, described second doping type is contrary with described first doping type, and the surface of described well region has the inversion layer of the first doping type；Wherein, the epi-layer surface below described gate dielectric layer leaves the low concentration region of unimplanted first doping type ion.The present invention can weaken the electric field intensity of gate dielectric layer thus ensureing that gate dielectric layer is operated under low-stress to improve device reliability.
Description
Technical field
The present invention relates to depletion type power semiconductor device technology field, more specifically, relate to a kind of High-reliability depletion type power semiconductor device and manufacture method thereof.
Background technology
It is the key factor causing most of grid-control depletion type power semiconductor to be damaged that the time-varying of gate dielectric layer punctures (TDDB), in order to avoid gate dielectric layer punctures to improve the reliability of semiconductor device, generally can strictly limit the gate voltage being applied on gate electrode in actual applications, to ensure that gate dielectric layer is operated under low-stress.
Industry wishes to break through the above-mentioned restriction of grid-control depletion type power semiconductor.Concrete, it would be desirable to from inherent performance of semiconductor device, by proposing new semiconductor device structure to improve reliability.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of High-reliability depletion type power semiconductor device and manufacture method thereof, it is possible to weaken the electric field intensity of gate dielectric layer thus ensureing that gate dielectric layer is operated under low-stress to improve device reliability.
For solving above-mentioned technical problem, the invention provides a kind of High-reliability depletion type power semiconductor device, including:
Semiconductor substrate；
The epitaxial layer of the first doping type being positioned in described Semiconductor substrate；
It is sequentially located at the gate dielectric layer on described epitaxial layer and gate electrode；
Being positioned at the well region of the second doping type of described gate electrode both sides, described epitaxial layer, described second doping type is contrary with described first doping type, and the surface of described well region has the inversion layer of the first doping type；
Wherein, the epi-layer surface below described gate dielectric layer leaves the low concentration region of unimplanted first doping type ion.
According to one embodiment of present invention, the width of described low concentration region accounts for the 10% ~ 50% of the well region spacing of described gate electrode both sides.
According to one embodiment of present invention, the ion implantation dosage Q1 of described well region and the ion implantation dosage Q2 of described inversion layer is selected as: 1e13cm-2≤Q1≤1e14cm-2, 2e12cm-2≤Q2≤2e13cm-2, and in the span meeting pressure and threshold voltage requirements, Q1 and Q2 takes the maximum of respective scope respectively.
According to one embodiment of present invention, the thickness of described gate dielectric layer is
Present invention also offers the manufacture method of a kind of High-reliability depletion type power semiconductor device, including: Semiconductor substrate is provided；
Form the epitaxial layer of the first doping type on the semiconductor substrate；
Forming the well region of the second doping type in described epitaxial layer, described second doping type is contrary with described first doping type；
The inversion layer of the first doping type is formed on the surface of described well region；And
Epitaxial layer between adjacent well region sequentially forms gate dielectric layer and gate electrode,
Wherein, the injection mask of described inversion layer has shield portions so that the low concentration region of unimplanted first doping type ion is left on the surface of described epitaxial layer, and described gate dielectric layer is positioned at above described low concentration region.
According to one embodiment of present invention, the width of described low concentration region accounts for the 10% ~ 50% of the well region spacing of described gate electrode both sides.
According to one embodiment of present invention, the ion implantation dosage Q1 of described well region and the ion implantation dosage Q2 of described inversion layer is selected as: 1e13cm-2≤Q1≤1e14cm-2, 2e12cm-2≤Q2≤2e13cm-2, and in the span meeting pressure and threshold voltage requirements, Q1 and Q2 takes the maximum of respective scope respectively.
According to one embodiment of present invention, the thickness of described gate dielectric layer is
Compared with prior art, the invention have the advantages that
In the High-reliability depletion type power semiconductor device of the embodiment of the present invention, the epi-layer surface below gate dielectric layer remains with the low concentration region of unimplanted first doping type ion, in other words, is not related to this part when by injecting transoid ion and forming inversion layer.The moiety concentrations injecting transoid ion is strengthened, and the moiety concentrations of unimplanted transoid ion remains original concentration, thus forming the Concentraton gradient of a transverse direction.The partial electric-field intensity that concentration remains original concentration is more weak so that the electric field intensity of gate dielectric layer is also more weak, it is ensured that gate dielectric layer is operated under low-stress thus being conducive to improving device reliability.
Additionally, the present embodiment additionally provides well region implantation dosage Q1 and the preferred version of inversion layer implantation dosage Q2 and the preferred version of gate dielectric layer thickness, be conducive to improving further the reliability of device.
Accompanying drawing explanation
Figure 1A to Fig. 1 C is the manufacture process of the High-reliability depletion type power semiconductor device of the embodiment of the present invention；
Fig. 2-3 is the impurities concentration distribution figure of silicon face below the High-reliability depletion type power semiconductor device gate dielectric layer of different experiments example in first embodiment of the invention；
Fig. 4-5 is the electric-field intensity distribution figure of the High-reliability depletion type power semiconductor device gate dielectric layer lower surface of different experiments example in first embodiment of the invention；
Fig. 6-7 is the electric-field intensity distribution figure of silicon upper surface below the High-reliability depletion type power semiconductor device gate dielectric layer of different experiments example in first embodiment of the invention；
Fig. 8-9 is the impurities concentration distribution figure of silicon face below the High-reliability depletion type power semiconductor device gate dielectric layer of different experiments example in second embodiment of the invention；
Figure 10-11 is the electric-field intensity distribution figure of the High-reliability depletion type power semiconductor device gate dielectric layer lower surface of different experiments example in second embodiment of the invention；
Figure 12-13 is the electric-field intensity distribution figure of silicon upper surface below the High-reliability depletion type power semiconductor device gate dielectric layer of different experiments example in second embodiment of the invention；
Figure 14-15 is the electric-field intensity distribution figure of the High-reliability depletion type power semiconductor device gate dielectric layer lower surface of different experiments example in third embodiment of the invention；
Figure 16-17 is the electric-field intensity distribution figure of silicon upper surface below the High-reliability depletion type power semiconductor device gate dielectric layer of different experiments example in third embodiment of the invention；
Figure 18 is the electric-field intensity distribution figure of the High-reliability depletion type power semiconductor device gate dielectric layer lower surface in fourth embodiment of the invention；
Figure 19 is the electric-field intensity distribution figure of silicon upper surface below the High-reliability depletion type power semiconductor device gate dielectric layer in fourth embodiment of the invention.
Detailed description of the invention
Below in conjunction with specific embodiments and the drawings, the invention will be further described, but should not limit the scope of the invention with this.
Figure 1A to Fig. 1 C illustrates the cross-sectional view that in the manufacture method of the High-reliability depletion type power semiconductor device of the present embodiment, each step is corresponding, is specifically described below.
With reference to Figure 1A, it is provided that Semiconductor substrate 1, this Semiconductor substrate 1 forms the epitaxial layer 2 of the first doping type, after forming epitaxial layer 2, it is also possible on epitaxial layer 2, form dielectric layer 5 '.Afterwards, forming the well region 3 of the second doping type in epitaxial layer 2, more specifically, use well region to inject mask 7A and epitaxial layer 2 is carried out ion implanting, the ion of injection is the second doping type, and implantation dosage is Q1.Wherein, the first doping type and the second doping type are contrary, respectively n-type doping and the doping of P type.
With reference to Figure 1B, form the inversion layer 4A of the first doping type on the surface of well region 3.More specifically, using inversion layer to inject mask 7B and well region 3 is carried out ion implanting, the ion of injection is the first doping type, and implantation dosage is Q2.When well region 3 is carried out ion implanting, the ion of the first doping type also injects in the epitaxial layer 2 of next-door neighbour's well region 3 in the lump so that the doping content of the surface portion of the epitaxial layer 2 of next-door neighbour's well region 3 is strengthened, thus forming accumulation layer 4B.The doping type of accumulation layer 4B is identical with epitaxial layer 2, and doping content is more than the doping content of epitaxial layer 2.After ion implantation, being removed by dielectric layer 5 ', minimizing technology can be such as etching.
In the present embodiment, inversion layer injection mask 7B has shield portions so that the surface of epitaxial layer 2 remains with the low concentration region 4C of unimplanted first doping type ion, and the gate dielectric layer being subsequently formed and gate electrode are positioned at above the 4C of low concentration region.Preferably, this low concentration region 4C is positioned at below the middle of the gate dielectric layer being subsequently formed.
In fig. ib, the width of the shield portions that inversion layer injects mask 7B is designated as a, owing to the width of the low concentration region 4C of effect of the blocking formation of shield portions is designated as b, owing to mask pattern would be likely to occur proportional zoom when projection, therefore width a and width b is numerically not necessarily the same.
With reference to Fig. 1 C, the epitaxial layer 2 between adjacent well region 3 sequentially forms gate dielectric layer 5 and gate electrode 6.More specifically, forming gate dielectric layer 5 on epitaxial layer 2, forming method can be such as thermal oxidation method；Forming gate electrode layer afterwards on the gate dielectric layer 5 formed, this gate electrode layer can be such as polysilicon layer；Adopt mask 7C that gate dielectric layer 5 and gate electrode layer are performed etching afterwards, form the gate dielectric layer 5 after graphically and gate electrode 6.Wherein, low concentration region 4C is positioned at below gate dielectric layer 5 and gate electrode 6, it is preferred to be positioned at below the middle of gate dielectric layer 5.
Owing to accumulation layer 4B being filled with the first doping type ion, its doping content is strengthened, and the doping content of low concentration region 4C remains original concentration, therefore between accumulation layer 4B and low concentration region 4C, form horizontal Concentraton gradient, the electric field intensity at 4C place, low concentration region is more weak, making when identical gate voltage, the overall electric field intensity of gate dielectric layer 5 weakens.
Further, in a preferred embodiment, the width b of low concentration region 4C accounts for the 10% ~ 50% of well region 3 spacing of gate electrode 6 both sides, and in this proportion, it is preferably that the electric field intensity of gate dielectric layer 5 weakens effect.
It addition, the ion implantation dosage Q2 of the ion implantation dosage Q1 and inversion layer 4A of well region 3 is preferably 1e13cm-2≤Q1≤1e14cm-2, 2e12cm-2≤Q2≤2e13cm-2, and in the span meeting pressure and threshold voltage requirements, Q1 and Q2 takes the maximum of respective scope respectively.
Further, the thickness of this dielectric layer 5 is preferablyUnder identical gate voltage, gate dielectric layer 5 is more thick, and its electric field intensity is more low.
It is described separately these technological means being intended to reduce the electric field intensity of gate dielectric layer 5 above-mentioned below by different embodiments.These technological means will be set forth in the examples below respectively.It is noted that the description order of these embodiments is not intended to limit they importances in the art.The present invention should be able to contain the various combinations of these technological means.
First embodiment, inversion layer injecting mask 7B is set to there is shield portions in gate electrode middle.
According to the first embodiment of the present invention, when using inversion layer injecting mask 7B to carry out selectivity ion implanting, owing to inversion layer injecting mask 7B has shield portions (width is a) in the middle of gate electrode 6, which prevent ion implanting, therefore leaving unimplanted low concentration region 4C(width in the epitaxial layer 2 below gate electrode 6 accordingly is b).
Specifically, by selecting specific inversion layer injecting mask 7B, in the epitaxial layer 2 except well region 3, only have subregion (i.e. accumulation layer 4B) and be injected into transoid ion so that the concentration of accumulation layer 4B is strengthened.And the low concentration region 4C(width of unimplanted transoid ion is that concentration b) remains original concentration.Between accumulation layer 4B and 4C region, low concentration region, thus form the Concentraton gradient of a transverse direction.The electric field intensity of low concentration region 4C is more weak so that when identical gate voltage, the overall electric field intensity of gate dielectric layer 5 weakens.
Below gate electrode 6, the width b's of low concentration region 4C preferably ranges from 1 μm≤b≤3 μm.
The effect of the present embodiment can be passed through different experimental examples and be verified.In experimental example one and experimental example two, two kinds of a values are respectively adopted it to achieve same threshold V T H.In experimental example one, Q1=3e13cm-2, Q2=7e12cm-2, gate dielectric layer 5 adopts silicon dioxide, its thicknessWhen width a=0 μm (namely not the blocking) of shield portions, now the surface of the epitaxial layer 2 except well region 3 all will formation accumulation layer 4B.For experimental example one, silicon surface dopant concentration is distributed as in figure 2 it is shown, accumulation layer 4B regional concentration is 4.3e17cm-3；For experimental example one, as shown in Figure 4, electric field intensity maximum is 2e6V/cm to gate dielectric layer 5 lower surface electric-field intensity distribution；For experimental example one, below gate dielectric layer 5, silicon surface electric field intensity distributions is as shown in Figure 6, and electric field intensity maximum is 5.4e5V/cm.
In experimental example two, shield portions a=2.9 μm, now the only subregion, epitaxial layer 2 surface beyond well region 3 forms accumulation layer 4B, and another part is low concentration region 4C, accordingly, now the width b of low concentration region 4C accounts for below gate electrode 6 between 2 well regions 3 the 44.6% of spacing.For experimental example two, silicon surface dopant concentration is distributed as it is shown on figure 3, concentration is by the 4.3e17cm of accumulation layer 4B-3Change to the 2.5e16cm of low concentration region 4C-3；For experimental example two, gate dielectric layer 5 lower surface electric-field intensity distribution is as it is shown in figure 5, electric field intensity maximum is 1.85e6V/cm；For experimental example two, silicon surface electric field intensity distributions below gate dielectric layer 5 is as it is shown in fig. 7, electric field intensity maximum is 3.7e5V/cm.
By contrast it appeared that: experimental example two makes gate dielectric layer 5 lower surface electric field intensity maximum be reduced to 1.85e6V/cm by 2e6V/cm, reduces by 7.5% on year-on-year basis；Experimental example two makes silicon surface electric field maximum of intensity below gate dielectric layer 5 be reduced to 3.7e5V/cm by 5.4e5V/cm, reduces 31.5% on year-on-year basis.The reduction of electric field intensity, it is meant that the reliability obtaining device gets a promotion.
Second embodiment: the best of breed collocation of well region implantation dosage Q1 and inversion layer implantation dosage Q2.
In a second embodiment, by selecting the optimum combination collocation of the implantation dosage Q2 of the implantation dosage Q1 and inversion layer 4A of well region 3, the electric field intensity making gate dielectric layer 5 under the requirement meeting pressure and threshold voltage is the most weak.The preferred span of Q1 and Q2 is: 1e13cm-2≤Q1≤1e14cm-2, 2e12cm-2≤Q2≤2e13cm-2.In above-mentioned span, higher dosage combination can make electric field intensity reduce.Q1 and Q2 is taken respectively the maximum in scope, then obtains optimum combination collocation.
The effect of the present embodiment can be passed through different experimental examples and be verified.In experimental example three and experimental example four, shield portions width a=1.1 μm of inversion layer injecting mask 7B, gate dielectric layer 5 adopts silicon dioxide, its thicknessIn experimental example three and experimental example four, being respectively adopted two groups of dosage collocation and achieved same threshold V T H, the dosage combination of experimental example three is Q1=2.2e13cm-2, Q2=5e12cm-2, and the dosage combination of experimental example four is Q1=8e13cm-2, Q2=9e12cm-2.The dosage combination of experimental example three is relatively low-dose combination, and the dosage combination of experimental example four is higher dosage combination.
In the dosage combination of experimental example three, adopting relatively low Q1, in order to match, Q2 is relatively low.Now silicon surface dopant concentration is distributed as shown in Figure 8, and the concentration of accumulation layer 4B is 4.3e17cm-3, the concentration of low concentration region 4C is 2.5e16cm-3；As shown in Figure 10, electric field intensity maximum is 1.6e6V/cm to gate dielectric layer 5 lower surface electric-field intensity distribution；Below gate dielectric layer 5, silicon surface electric field intensity distributions is as shown in figure 12, and electric field intensity maximum is 4.4e5V/cm.
In the dosage combination of experimental example four, adopting higher Q1, in order to match, Q2 is also higher.Now silicon surface dopant concentration is distributed as it is shown in figure 9, the concentration of accumulation layer 4B is 7e17cm-3, the concentration of low concentration region 4C is 2.5e16cm-3；As shown in figure 11, electric field intensity maximum is 1.35e6V/cm to gate dielectric layer 5 lower surface electric-field intensity distribution；Below gate dielectric layer 5, silicon surface electric field intensity distributions is as shown in figure 13, and electric field intensity maximum is 3.2e5V/cm.
Contrast it appeared that: the dosage combination of experimental example four is compared with the first dosage combination of experimental example three, and the former makes gate dielectric layer 5 lower surface electric field intensity maximum be reduced to 1.35e6V/cm by 1.6e6V/cm, reduces by 15.6% on year-on-year basis；Below gate dielectric layer 5, silicon surface electric field maximum of intensity is reduced to 3.2e5V/cm by 4.4e5V/cm, reduces 27.3% on year-on-year basis.The reduction of electric field intensity, it is meant that the reliability obtaining device gets a promotion.
3rd embodiment: thicken gate dielectric layer thickness G ox.
In the third embodiment, by adopting thicker gate dielectric layer 5 can reduce the electric field intensity of gate dielectric layer 5.When identical gate voltage, gate dielectric layer 5 its electric field intensity more thick is more weak.According to the present embodiment, the thickness range of gate dielectric layer 5 is preferably
The effect of the present embodiment can be passed through different experimental examples and be verified.In experimental example five and experimental example six, it is respectively adopted two kinds of gate oxide thicknesses to achieve same threshold V T H, shield portions width a=1.1 μm of inversion layer injecting mask 7B, gate dielectric layer 5 adopts silicon dioxide, Q1=3e13cm-2, Q2=8e12(4.8e12) cm-2, gate voltage is-10V.
In experimental example five, shield portions width a=1.1 μm of inversion layer injecting mask 7B, gate dielectric layer 5 adopts silicon dioxide, Q1=3e13cm-2, Q2=8e12cm-2, gate voltage is-10V,For experimental example five, as shown in figure 14, electric field intensity maximum is 2.3e6V/cm to gate dielectric layer 5 lower surface electric-field intensity distribution；Below gate dielectric layer 5, silicon surface electric field intensity distributions is as shown in figure 16, and electric field intensity maximum is 6.1e5V/cm.
In experimental example six, shield portions width a=1.1 μm of inversion layer injecting mask 7B, gate dielectric layer 5 adopts silicon dioxide, Q1=3e13cm-2, Q2=4.8e12cm-2, gate voltage is-10V,For experimental example six, as shown in figure 15, electric field intensity maximum is 1.28e6V/cm to gate dielectric layer 5 lower surface electric-field intensity distribution；Below gate dielectric layer 5 shown in silicon surface electric field intensity distributions Figure 17, electric field intensity maximum is 3.5e5V/cm.
Contrast it appeared that: experimental example sixWith experimental example fiveComparing, the former makes gate dielectric layer 5 lower surface electric field intensity maximum be reduced to 1.28e6V/cm by 2.3e6V/cm, reduces by 44.4% on year-on-year basis；Below gate dielectric layer 5, silicon surface electric field maximum of intensity is reduced to 3.5e5V/cm by 6.1e5V/cm, reduces 42.6% on year-on-year basis.The reduction of electric field intensity, it is meant that the reliability of device gets a promotion.
4th embodiment: be arranged below low concentration region 4C at gate electrode 6, optimize implantation dosage Q1 and Q2 and increase by three kinds of technological means combinations of thickness of gate dielectric layer 5.
The effect of the present embodiment can example seven be verified by experiment.In experimental example seven, shield portions width a=1.9 μm of inversion layer injecting mask 7B, gate dielectric layer 5 adopts silicon dioxide, its thicknessQ1=8e13cm-2, Q2=6e12cm-2.For experimental example seven, as shown in figure 18, electric field intensity maximum is 0.78e6V/cm to gate dielectric layer 5 lower surface electric-field intensity distribution；Below gate dielectric layer 5, silicon surface electric field intensity distributions is as shown in figure 19, and electric field intensity maximum is 2.4e5V/cm.
Contrast it appeared that: experimental example seven is compared with previous experimental example one to six, experimental example seven makes gate dielectric layer 5 lower surface electric field intensity maximum by the 1.85e6V/cm of experimental example one, two, the 1.35e6V/cm of experimental example three, four, the 1.28e6V/cm of experimental example five, six is reduced to 0.78e6V/cm, reduces by 57.8%, 42.2%, 39.1% on year-on-year basis respectively；Below gate dielectric layer 5, silicon surface electric field maximum of intensity is by the 3.7e5V/cm of experimental example one, two, the 3.2e5V/cm of experimental example three, four, and the 3.5e5V/cm of embodiment five, six is reduced to 2.4e5V/cm, reduces by 35.1%, 25%, 31.4% on year-on-year basis respectively.The further reduction of electric field intensity, it is meant that the reliability of device is further promoted.
To sum up, the present invention is by one or more in above-mentioned means so that gate dielectric layer electric field intensity weakens, and then the time-varying of gate medium punctures (TDDB, TimeDependentDielectricBreakdown) and is improved, and improves reliability.The present invention can be used for improving depletion type grid-control semiconductor device, such as the reliability of metal-oxide semiconductor fieldeffect transistor (MOSFET), insulated gate bipolar transistor (IGBT) etc..
Although the present invention is with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art are without departing from the spirit and scope of the present invention; can making possible variation and amendment, therefore protection scope of the present invention should be as the criterion with the scope that the claims in the present invention define.
Claims (2)
1. a High-reliability depletion type power semiconductor device, including:
Semiconductor substrate；
The epitaxial layer of the first doping type being positioned in described Semiconductor substrate；
It is sequentially located at the gate dielectric layer on described epitaxial layer and gate electrode；
Being positioned at the well region of the second doping type of described gate electrode both sides, described epitaxial layer, described second doping type is contrary with described first doping type, and the surface of described well region has the inversion layer of the first doping type；
It is characterized in that, the epi-layer surface below described gate dielectric layer leaves the low concentration region of unimplanted first doping type ion；
Wherein, the width of described low concentration region accounts for the 10%～50% of the well region spacing of described gate electrode both sides, and the ion implantation dosage Q1 of described well region and the ion implantation dosage Q2 of described inversion layer is selected as: 1e13cm-2≤Q1≤1e14cm-2, 2e12cm-2≤Q2≤2e13cm-2, and in the span meeting pressure and threshold voltage requirements, Q1 and Q2 takes the maximum of respective scope respectively, and the thickness of described gate dielectric layer is
2. a manufacture method for High-reliability depletion type power semiconductor device, including:
Semiconductor substrate is provided；
Form the epitaxial layer of the first doping type on the semiconductor substrate；
Forming the well region of the second doping type in described epitaxial layer, described second doping type is contrary with described first doping type；
The inversion layer of the first doping type is formed on the surface of described well region；And
Epitaxial layer between adjacent well region sequentially forms gate dielectric layer and gate electrode,
It is characterized in that, the injection mask of described inversion layer has shield portions so that the low concentration region of unimplanted first doping type ion is left on the surface of described epitaxial layer, and described gate dielectric layer is positioned at above described low concentration region；
Wherein, the width of described low concentration region accounts for the 10%～50% of the well region spacing of described gate electrode both sides, and the ion implantation dosage Q1 of described well region and the ion implantation dosage Q2 of described inversion layer is selected as: 1e13cm-2≤Q1≤1e14cm-2, 2e12cm-2≤Q2≤2e13cm-2, and in the span meeting pressure and threshold voltage requirements, Q1 and Q2 takes the maximum of respective scope respectively, and the thickness of described gate dielectric layer is
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| CN203013735U (en) * | 2012-12-26 | 2013-06-19 | 杭州士兰微电子股份有限公司 | High-reliability depletion type power semiconductor device |
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| CN203013735U (en) * | 2012-12-26 | 2013-06-19 | 杭州士兰微电子股份有限公司 | High-reliability depletion type power semiconductor device |
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